JPS6362135B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method of converting input audio into analog/
The digital audio data obtained by digital conversion is separated into different frequency bands,
The present invention relates to a cyclic secondary filter circuit for voice recognition that extracts N-channel digital voice data.

Generally, in order to perform speech recognition, it is necessary to convert input speech from analog to digital at regular intervals to obtain digital speech data, and to use the digital speech data as a recognition target. However, since this digital voice data contains various frequency components, it is usually separated into predetermined frequency bands (channels) by applying a cyclic secondary filter circuit for voice recognition, a so-called IIR (Infinite Inpulse Response) filter. , the procedure for extracting the corresponding digital audio data must be performed for multiple frequency bands. Figure 1 shows a general IIR filter model. (Input) digital audio data _xo obtained by analog/digital conversion of input audio at regular intervals is processed by the IIR filter into a predetermined frequency band. (output) of (channel) is extracted as digital audio data _yo . However, in the example of FIG. 1, y _o =A ₀ x _o +A ₁ x _o-1 +A ₂ x _o-2 -B ₁ y _o-1 -B ₂ y _o-2 . Here, x _o-1 and x _o-2 are (input) digital audio data one cycle and two cycles before the corresponding cycle, respectively, and y _o-1 and y _o-2 are the same one cycle each of the corresponding cycle. This is (output) digital audio data two cycles ago. Also, A ₀ , A ₁ , A ₂ ,
B ₁ and B ₂ are linear regression parameters specific to a specific frequency band (channel). By using, for example, 16 types of IIR filters with different linear regression parameters A ₀ , A ₁ , A ₂ , B ₁ , and B ₂ , the (input) digital audio data is divided into 16 frequency bands. It can be separated into 16 channels (output) and extracted as digital audio data. In addition, when obtaining 16 channels of (output) digital audio data, as shown in Figure 1,
It is common to use IIR filters connected in two stages.

By the way, in order to improve recognition accuracy in speech recognition, it is first necessary to shorten the sampling period of input speech and increase the number of samplings.
However, conventionally, the processing operation of the above-mentioned IIR filter has been carried out under software control such as microprogram control, which has the drawback of slow processing speed and inability to cope with high-speed sampling.

The present invention has been made in view of the above circumstances, and its purpose is to perform multiplication of digital audio data input at a constant period T by M types of linear regression parameters unique to each channel at a constant cycle for all channels. By executing within T, we obtain the multiplication results required in the relevant cycle, the multiplication results required in the next cycle, and the multiplication results required in the next cycle, and then calculate these M types of multiplication results. handle
By sequentially storing each channel in the FIFO memory and utilizing the output delay due to the difference in the configuration of these FIFO memories, the multiplication results in the relevant cycle, the multiplication results in the previous cycle, and the multiplication results in the previous cycle can be stored in the FIFO memory. It is an object of the present invention to provide a cyclic secondary filter circuit for speech recognition, which can perform mixing processing of multiplication results for all channels within a fixed period T, and which can perform high-speed processing by pipeline calculation.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Figure 2 shows the first stage pipeline calculation circuit applied to the cyclic secondary filter circuit for speech recognition (hereinafter referred to as IIR filter) of the present invention, and Figure 3 shows the next stage (in this example, the final stage). This figure shows the configuration of the pipeline arithmetic circuit. Note that this embodiment is a case where the present invention is implemented in an IIR filter that separates digital audio data obtained by analog/digital conversion of input audio at regular intervals into 16 channels of digital audio data and extracts the data. In FIG. 2, 201 is digital audio data _{x o} obtained by converting input audio from analog to digital at a fixed period T, for example, every 125 ns.
This is a gate whose output is controlled according to a gate clock signal T with a period of 125 ns/16. 202 is gate 2
FIFO memory (first
4FIFO memory), and the FIFO becomes full (FULL) with 16 pieces of data (digital audio data x _o )
(First In First Out) structure memory. 2
03 to 207 are FIFOs in which, for example, five types of linear regression type parameters A ⁱ ₀ , A ⁱ ₁ , A ⁱ ₂ , −B ⁱ ₁ , −B ⁱ ₂ are stored in advance in a fixed order for 16 channels each.
These parameters A ⁱ ₀ , A ⁱ ₁ , A ⁱ ₂ , −B ⁱ ₁ , −B ⁱ ₂ (i=0 to 15) are obtained from the corresponding FIFO memories 203 to 207 over time.
The signals are output sequentially at intervals of 125ns/16. In this embodiment, FIFO memories 203 to 2
Parameters A ⁱ ₀ , A ⁱ ₁ , A ⁱ ₂ , − output from 07
B ⁱ ₁ and -B ⁱ ₂ are again input to the FIFO memories 203 to 207. Therefore, parameters A ⁰ ₀ to A ¹⁵ ₀ , A ⁰ ₁ are obtained from the FIFO memories 203 to 207.
˜A ¹⁵ ₁ , A ⁰ ₂ ˜A ¹⁵ ₂ , −B ⁰ ₁ ˜−B ¹⁵ ₁ , −B ⁰ ₂ ˜−B ¹⁵ ₂ are repeatedly output in a fixed order at intervals of 125 ns/16. 208 to 212 are gates for initializing parameters. Gates 208 to 212 input parameters A ⁰ ₀ to A ¹⁵ ₀ , A ⁰ ₁ to A ¹⁵ ₁ , A ⁰ ₂ to ^{A 15} ₂ , −B ⁰ ₁ to
−B ¹⁵ ₁ , −B ⁰ ₂ to −B ¹⁵ ₂ are initial clock signals
Control output according to INT. 213-218 are
These gates control the outputs of the FIFO memories 202 to 207 in accordance with the gate clock signal T.

219 is a multiplier that performs multiplication between each output of gates 213 and 214; 220 is a multiplier that performs multiplication between the outputs of gates 213 and 214;
A multiplier 221 performs multiplication between the respective outputs of gates 213 and 216. 222 is the output of the gate 217 and the primary operation result y ⁱ _o output from the gate 233 which will be described later.
A multiplier 223 is a gate 218 that performs multiplication with
This is a multiplier that multiplies the output of y i o by the above primary operation result y ⁱ _o .

224 is the time when the multiplication result of the multiplier 219 is
It is a FIFO memory (first FIFO memory) that stores data sequentially at intervals of 125ns/16, and becomes full (FULL) with 16 pieces of data (multiplication results). 225 and 226 are FIFO memories (second FIFO memories) provided corresponding to the multipliers 220 and 222, respectively, in which the multiplication results of the corresponding multipliers 220 and 222 are sequentially stored at intervals of 125 ns/16; memory 22
FIFO memories 225 ₁ , 225 ₂ with the same structure as 4.
It consists of two stages of FIFO memories 226 ₁ and 226 ₂ each connected in cascade. Further, 227 and 228 are provided corresponding to the multipliers 221 and 223, respectively.
The multiplication results of the corresponding multipliers 221 and 223 are
It is a FIFO memory (third FIFO memory) that is stored sequentially at an interval of 125 ns/16, and has the same _structure as the FIFO memory ₂₂₄ .
The memory 228 ₁ to 228 ₃ are each connected in three stages.

229 is an adder that adds each output data from the FIFO memories 224 and 225 ₂ , and 230 is an adder that adds the addition result of this adder 229 and the output data from the FIFO memory 227 ₃ . 23
1 is an adder that adds each output data from the FIFO memories 226 ₂ and 228 ₃ , and 232 is an adder 23
This is an adder that adds up each addition result of 0,231. Reference numeral 233 denotes a gate that controls the output of the addition result of the adder 232 as the primary operation _{result yio} ⁱⁿ response to the gate clock signal T. The output (y ⁱ _o ) of the gate 233 is output to the multipliers 222 and 223 (of its own stage) and is also transferred to the gate of the next stage corresponding to the gate 201.

Next, the configuration of the next stage pipeline arithmetic circuit will be briefly described. In this embodiment, the configuration of the pipeline arithmetic circuit is basically the same as that of the preceding stage pipeline arithmetic circuit shown in FIG.
301 is a gate similar to the gate 201 in FIG. However, the gate 301 does not receive the digital audio data obtained by analog/digital conversion of the input audio, ^but the calculation result of the previous stage _.
(that is, digital audio data separated into predetermined frequency bands and extracted) is input. 302
~307 are FIFO memories 202~207 in Figure 2
FIFO memory similar to , and 308-312 are gates similar to gates 208-212 of FIG.
However, the FIFO memories 303 to 308 have linear regression type parameters A' ⁰ ₀ to A' ¹⁵ ₀ and A' ⁰ ₁ to
A′ ¹⁵ ₁ , A′ ⁰ ₂ ~A′ ¹⁵ ₂ , −B′ ⁰ ₁ ~ −B′ ¹⁵ ₁ , −B′ ⁰ ₂
~−B′ ¹⁵ ₂ is stored in advance. 313-318 are gates similar to gates 213-218 in FIG.
19-323 are multipliers similar to multipliers 219-223 in FIG. 324-328 are in Figure 2
FIFO memories 224-228 and 329-332 are adders 229-2 in FIG.
Adder similar to 32, 333 is gate 2 in FIG.
This is a gate similar to No. 33. The output of this gate 333 is the final calculation result z ⁱ _o in this embodiment.

Next, the operation of the configuration shown in FIGS. 2 and 3 will be explained. Now, FIFO memory 203 to 207,303
~307 respectively have linear regression type parameters for 16 channels A ⁰ ₀ ~ A ¹⁵ ₀ , A ⁰ ₁ ~ ^{A 15} ₁ , A ⁰ ₂ ~ A ¹⁵ ₂ , −B ⁰ ₁ ~
−B ¹⁵ ₁ , −B ⁰ ₂ ~ −B ¹⁵ ₂ , A' ⁰ _{0 ~} A' ¹⁵ ₀ , A' ⁰ _{1 ~} A' ¹⁵
₁ ，A′ ⁰ ₂
〜A′ ¹⁵ ₂ , −B′ ⁰ ₁ 〜−B′ ¹⁵ ₁ , −B′ ⁰ ₂ 〜−B′ ¹⁵ ₂ are shown in Figure 2,
It is assumed that the information is stored as shown in FIG. In this state, input audio is transmitted at a constant period T.
Digital audio data obtained by sampling every (T=125ns) and performing analog/digital conversion is sequentially input to the gate 201. Now, a certain period T
At the start of , digital audio data x _o-2 is sent to gate 2
01 is input. This gate 201
The input contents remain the same until the start of the next cycle T. The gate 201 outputs digital audio data x _o-2 in response to a gate clock signal with a period of 125 ns/16.
is output to the FIFO memory 202. Therefore, the gate 201 outputs the same digital audio data x _o-2 16 times during a certain period T (T=125 ns). For convenience, these 16 pieces of the same digital audio data x _o-2 are arranged in order from the oldest to x ⁰ _o-2 ,
Let us express it as x ¹ _o-2 ,...x ¹⁵ _o-2 . These 16 digital audio data x ⁰ _o-2 ~ x ¹⁵ _o-2 have a time of 125 ns/16
The data are sequentially input to the FIFO memory 202 and stored at intervals of . At this time, every time new data is stored in the first storage area of the FIFO memory 202, old data is moved to the output section side, and the oldest data is
It is output from the FIFO memory 202. On the other hand, FIFO
The memories 203 to 207 are also controlled at the same timing as the FIFO memory 202, and as a result, the five parameters A ⁱ ₀ , A ⁱ ₁ , A ⁱ ₂ , −B ⁱ ₁ , −B ⁱ ₂ are controlled at the same timing as the FIFO memory 202. They are output sequentially in the order in which they are stored at intervals of 16. The outputs of these FIFO memories 203-207 are input again to the FIFO memories 203-207.
Therefore, the parameters for 16 channels A ⁰ ₀ ~
A ¹⁵ ₀ , A ⁰ ₁ ~ A ¹⁵ ₁ , A ⁰ ₂ ~ A ¹⁵ ₂ , −B ⁰ ₁ ~ −B ¹⁵ ₁ , −B ⁰ ₂ ~
−
B ¹⁵ ₂ is 1 in its memory order at intervals of 125 ns/16
It is repeatedly output for each channel. It is clear that the period of this repetition is a constant period T, that is, 125 ns.

In this way, 16 digital audio data
After x ⁰ _o-2 to x ¹⁵ _o-2 are stored in the FIFO memory 202,
New digital audio data at the start of the next period T
x ⁰ _o-1 passes through gate 201 to FIFO memory 202
is assumed to have been input. As a result, the new digital audio data x ⁰ _o-1 is stored in the first storage area of the FIFO memory 202, and the 16 old digital audio data x ⁰ _o-2 to x ¹⁵ _o-2 are stored on the output side. The oldest digital audio data x ⁰ _o-2 is output from the FIFO memory 202 . At this time, five parameters A ⁰ ₀ , A ⁰ ₁ , A ⁰ ₂ , -B ⁰ ₁ , -B ⁰ ₂ for channel 0 are output from the FIFO memories 203 to 207.
The digital audio data x ⁰ _o-2 output from the FIFO memory 202 is sent to the multiplier 21 via the gate 213.
9 to 221. Also, FIFO memory 2
Parameters A ⁰ ₀ , A ⁰ ₁ , output from 03 to 205
A ⁰ ₂ is also input to multipliers 219-221 via gates 214-216. As a result, the multipliers 219 to 221 multiply the parameter A ⁰ ₀ by the digital audio data x ⁰ _o-2 , and the parameter A ⁰ ₁
Multiplication of and digital audio data x ⁰ _o-2 , parameters
Multiply A ⁰ ₂ and digital audio data x ⁰ _o-2 ,
Outputs the multiplication results A ⁰ ₀ x ⁰ _o-2 , A ⁰ ₁ x ⁰ _o-2 , A ⁰ ₂ x ⁰ _o-2 .
On the other hand, the parameters -B ⁰ ₁ and -B ⁰ ₂ output from the FIFO memories 206 and 207 are
are input to multipliers 222 and 223 via. The primary operation result y ⁰ _o-2 outputted via the gate 233 is commonly input to the multipliers 222 and 223 . As a result, the multipliers 222 and 223 respectively multiply the parameter -B ⁰ ₁ and the primary calculation result y ⁰ _o-2 , and multiply the parameter -B ⁰ ₂ and the primary calculation result y ⁰ _o-2 , Outputs the multiplication results −B ⁰ ₁ y ⁰ _o-2 and −B ⁰ ₂ y ⁰ _o-2 . The multiplication results of these multipliers 219 to 223 A ⁰ ₀ x ⁰ _o-2 ,
A ⁰ ₁ x ⁰ _o-2 , A ⁰ ₂ x ⁰ _o-2 , −B ⁰ ₁ y ⁰ _o-2 , −B ⁰ ₂ y ⁰ _o-2 correspond
FIFO memory 224, 225 ₁ , 227 ₁ , 226
_{1,228 1} is stored in the first storage area.

Next, digital audio data x ¹ _o-1 is sent to gate 201
The data is input to the FIFO memory 202 from
When x ¹ _o-1 is stored in the first storage area of the FIFO memory 202, digital audio data x ¹ _o-2 is output from the FIFO memory 202. At this time, five types of parameters A ¹ ₀ , A ¹ ₁ , A ¹ ₂ , -B ¹ ₁ , -B ¹ ₂ for channel 1 are output from the FIFO memories 203 to 207.
However, the multiplier 219
Multiplication by ~223 is performed, and the multiplication result is
A ¹ ₀ x ¹ _o-2 , A ¹ ₁ x ¹ _o-2 , A ¹ ₂ x ¹ _o-2 , −B ¹ ₁ y ¹ _o-2 , −B ¹ ₂ y ¹ _o
-2 are the corresponding FIFO memories 224, 225 ₁ ,
It is stored in the first storage area of 227 ₁ , 226 ₁ , and 228 ₁ . Note that each multiplier 219 to 223 has
Since data is input sequentially at a time interval of 125ns/16, each multiplier 219 to 223 has a time interval of 125ns/16.
It is necessary to finish executing one multiplication within. Thereafter, a similar operation is performed every time subsequent digital audio data x ² _o-1 to x ¹⁵ _o-1 is input to the FIFO memory 202 via the gate 201. Therefore, the time when the final digital audio data x ¹⁵ _o-1 of a certain period T (T = 125 ns) is stored in the first storage area of the FIFO memory 202, that is, the FIFO memory 20
2 to 16 identical digital audio data x ⁰ _o-1 ~ x ¹⁵ _o-1
At the time when is stored, the FIFO memory 224,
225 ₁ , 227 ₁ , 226 ₁ , 228 ₁ have the multiplication results A ⁰ ₀ x ⁰ _o-2 〜A ¹⁵ ₀ x ¹⁵ _o-2 , A ⁰ ₁ x ⁰ _o-2 〜A ¹⁵ _1, respectively.
x ¹⁵ _o-2 , A ⁰ ₂ x ⁰ _o-2 ~ ^{A 15} ₂ x ¹⁵ _o-2 , −B ⁰ ₁ y ⁰ _o-2 ~ −B ¹⁵ ₁ y ^1
5 _o-2 ,−
This means that B ⁰ ₂ x ⁰ _o-2 ~−B ¹⁵ ₂ x ¹⁵ _o-2 is stored.

In this state, the next cycle T starts, and in this cycle T, the digital audio data x ⁰ _o to x ¹⁵ _o are sequentially transferred to the FIFO memory 20 at intervals of 125 ns/16.
2, digital audio data x ⁰ _o-1 to x ¹⁵ _o-1 in the period T before the period T is input from the FIFO memory 202 at an interval of 125 ns/16 accordingly.
are output sequentially. Similarly FIFO memory 203 ~
Parameter A ⁰ ₀ at intervals of time 125ns/16 from 207
~A ¹⁵ ₀ , A ⁰ ₁ ~A ¹⁵ ₁ , A ⁰ ₂ ~A ¹⁵ ₂ , −B ⁰ ₁ ~ −B ¹⁵ ₁ , −B ⁰ ₂
~
−B ¹⁵ ₂ are output sequentially. Furthermore, the primary operation results y ⁰ _o-1 ~ y ¹⁵ _o-1 are obtained from the gate 233 at intervals of 125 ns/16.
are output sequentially. Multipliers 219 to 223 multiply the parameters A ⁰ ₀ to ^{A 15} ₀ by the digital audio data x ⁰ _o-1 to x ¹⁵ _o-1 , and the parameter A ⁰ ₁ as in the case described above.
Multiplication of ~A ¹⁵ ₁ and digital audio data x ⁰ _o-1 ~x ¹⁵ _o-1 ,
Parameters A ⁰ ₂ ~ A ¹⁵ ₂ and digital audio data x ⁰ _o-1 ~
Multiplication by x ¹⁵ _o-1 , parameter −B ⁰ ₁ ~ −B ¹⁵ ₁ and primary operation result y ⁰ _o-1 ~ y ¹⁵ _o-1 , parameter −B ⁰ ₂ ~ −
B ¹⁵ ₂ is multiplied by the primary operation results y ⁰ _o-1 to y ¹⁵ _o-1 .
Multiplication results of these multipliers 219 to 223 A ⁰ ₀ x ⁰ _o-1
~A ¹⁵ ₀ x ¹⁵ _o-1 ,A ⁰ ₁ x ⁰ _o-1 ~A ¹⁵ ₁ x ¹⁵ _o-1 ,A ⁰ ₂ x ⁰ _o-1 ~A ¹⁵ ₂
x ^15o _-1
−B ⁰ ₁ y ⁰ _o-1 〜−B ¹⁵ ₁ y ¹⁵ _o-1 ，−B ⁰ ₂ y ⁰ _o-1 〜−B ¹⁵ ₂ y ¹⁵ _o-1
is FIFO memory 2 that corresponds sequentially at an interval of 125 ns/16
24, 225 ₁ , 227 ₁ , 226 ₁ , and 228 ₁ are input and stored. And each of these FIFO memories 2
Each time the latest 1 multiplication result is input and stored in 24, 225 ₁ , 227 ₁ , 226 ₁ , 228 ₁ , the corresponding
FIFO memory 224, 225 ₁ , 227 ₁ , 226
₁ , 228 ₁ , the oldest multiplication result in the corresponding time period is output. FIFO memory 2
Among the outputs of 24, 225 ₁ , 227 ₁ , 226 ₁ , 228 ₁ , the output of the FIFO memory 224 is sent to the adder 23
6, FIFO memory 225 ₁ , 227 ₁ ,
The outputs of 226 ₁ and 228 ₁ are input and stored in FIFO memories 225 ₂ , 227 ₂ , 226 ₂ , and 228 ₂ , respectively. However, at the end of the period T,
The same digital audio data x ⁰ _o to ^{x 15} _o is stored in the FIFO memory 202, and the FIFO memories 224, 22
5 ₁ , 227 ₁ , 226 ₁ , 228 ₁ have the multiplication results A ⁰ ₀ x ⁰ _o-1 ~ A ¹⁵ ₀ x ¹⁵ _o-1 , A ⁰ ₁ x ⁰ _o-1 ~ A ¹⁵ ₁ in the period T.
x ¹⁵ _o-1 , A ⁰ ₂ x ⁰ _o-1 ~ ^{A 15} ₂ x ¹⁵ _o-1 , −B ⁰ ₁ y ⁰ _o-1 ~ −B ¹⁵ ₁ y ^1
5 _o-1 ,−
B ⁰ ₂ y ⁰ _o-1 ~−B ¹⁵ ₂ y ¹⁵ _o-1 is stored in the FIFO memory 22
5 ₂ , 227 ₂ , 226 ₂ , 228 ₂ are the multiplication results A ⁰ ₁ x ⁰ _o-2 to A ¹⁵ ₁ in the period T immediately before the period T.
x ¹⁵ _o-2 , A ⁰ ₂ x ⁰ _o-2 ~ ^{A 15} ₂ x ¹⁵ _o-2 , −B ⁰ ₁ y ⁰ _o-2 ~ −B ¹⁵ ₁ y ^1
5 _o-2 ,−
B ⁰ ₂ y ⁰ _o-2 ~−B ¹⁵ ₂ y ¹⁵ _o-2 is stored.

In this state, the next period T is started, and in this period T, digital audio data x ⁰ _o+1 to x ¹⁵ _o+1 are sequentially input to the FIFO memory 202 at intervals of 125 ns/16. The corresponding FIFO
Digital audio data x ⁰ _o ~ in the period T before the period T from the memory 202 at an interval of time 125 ns/16
x ¹⁵ _o are output sequentially. Furthermore, the primary calculation results y ⁰ _o to y ¹⁵ _o are sequentially outputted from the gate 239 at intervals of 125 ns/16. Multipliers 219 to 223 process these digital audio data x ⁰ _o to x ¹⁵ _o , as in the case described above.
Primary calculation results y ⁰ _o ~ y ¹⁵ _o and corresponding parameters A ⁰ ₀
~A ¹⁵ ₀ , A ⁰ ₁ ~A ¹⁵ ₁ , A ⁰ ₂ ~A ¹⁵ ₂ , −B ⁰ ₁ ~ −B ¹⁵ ₁ , −B ⁰ ₂
~
−B ¹⁵ Multiply by ₂ . As a result, multiplier 2
Multiplication results from 19 to 223 A ⁰ ₀ x ⁰ _o ~ A ¹⁵ ₀ x ¹⁵ _o , A ⁰ ₁ x ⁰ _o ~
A ¹⁵ ₁ x ¹⁵ _o , A ⁰ ₂ x ⁰ _o ~ ^{A 15} ₂ x ¹⁵ _o , −B ⁰ ₁ y ⁰ _o ~ −B ¹⁵ ₁ y ¹⁵ _o ,
−B ⁰ ₂
y ⁰ _o ~-B ¹⁵ ₂ y ¹⁵ _o correspond to FIFO memories 224, 225 ₁ , 227 ₁ , 2 sequentially at intervals of 125 ns/16
26 ₁ and 228 ₁ are input and stored. And each of these FIFO memories 224, 225 ₁ , 227 ₁ , 2
Every time the latest 1 multiplication result is input and stored in 26 ₁ , 228 ₁ , the corresponding FIFO memory 224 , 225 ₁ , 2
The oldest multiplication results in the corresponding time slots are output from 27 ₁ , 226 ₁ , and 228 ₁ , respectively.
FIFO memory 224, 225 ₁ , 227 ₁ , 226
1,228 ₁ , the output of the FIFO memory 224 is input to the adder 236, and the output of the FIFO memory 224 is inputted to the adder 236 _.
The outputs of 5 ₁ , 227 ₁ , 226 ₁ , 228 ₁ are respectively FIFO memories 225 ₂ , 227 ₂ , 226 ₂ , 22
8 ₂ is input and stored. At the end of the period T, as shown in FIG. 2, the same digital audio data x ⁰ _o+1 to
x ¹⁵ _o+1 is stored, FIFO memory 224, 225 ₁ ,
227 ₁ , 226 ₁ , 228 ₁ contain the multiplication results A ⁰ ₀ x ⁰ _o ~ A ¹⁵ ₀ x ¹⁵ _o , A ⁰ ₁ x ⁰ _o ~ A ¹⁵ ₁ x ¹⁵ _o , A ⁰ ₂ x in the period T.
^0o _{_}
~A ¹⁵ ₂ x ¹⁵ _o , −B ⁰ ₁ y ⁰ _o ~ −B ¹⁵ ₁ y ¹⁵ _o , −B ⁰ ₂ y ⁰ _o ~ −B ¹⁵ ₂
y ¹⁵ _o is stored in the FIFO memory 225 ₂ , 227 ₂ , 22
6 ₂ , 228 ₂ contains the multiplication results A ⁰ ₁ x ⁰ _o-1 〜A ¹⁵ ₁ x ¹⁵ _o-1 , A ⁰ ₂ x ⁰ _o-1 〜A ¹⁵ ₂ in the period T immediately before the period T.
x ¹⁵ _o-1 , −B ⁰ ₁ y ⁰ _o-1 ~ −B ¹⁵ ₁ y ¹⁵ _o-1 , −B ⁰ ₂ y ⁰ _o-1 ~ −B ^1
5 ₂ y ¹⁵ _o-1
is memorized. In addition, each FIFO memory 225 ₂ ~ 2
Every time the latest 1 multiplication result is input and stored in 28 ₂ , the oldest multiplication result in the corresponding time period is output from the FIFO memories 225 ₂ to 228 ₂ . Among the outputs of these FIFO memories 225 ₂ to 228 ₂ , each output of the FIFO memories 225 ₂ and 226 ₂ is input to the corresponding adder 229 and 231,
The outputs of the FIFO memories 227 ₂ and 228 ₂ are input and stored in the FIFO memories 227 ₃ and 228 ₃ , respectively. Therefore, at the end of the period T,
As shown in FIG. 2, the FIFO memories 227 ₃ and 228 ₃ store the multiplication results A ⁰ ₂ x ⁰ _o-2 to A ¹⁵ ₂ x ¹⁵ _o-2 , −B in the period T two cycles before the current period T. ⁰ ₂ y ⁰ _o-2 ~−B ¹⁵ ₂ y ¹⁵ _o
-2 is memorized.

In this state, the next cycle T starts, and in this cycle T, the following digital audio data x ⁰ _o+2 to x ¹⁵ _o+2 are sequentially transmitted at intervals of 125 ns/16.
When input to the FIFO memory 202, the FIFO memories 202 to 207, 224, 225 ₁
〜228 ₁ , 225 ₂ 〜228 ₂ , 227 ₃ , 228 ₃
The stored contents are output in the order in which they are stored at intervals of 125 ns/16. As is clear, when the digital audio data x ⁰ _o+2 is input to the FIFO memory 202, the FIFO memories 224, 225 ₂ , 227 ₃ , 22
The outputs of 6 ₂ and 228 ₃ are the multiplication results A ⁰ ₀ x ⁰ _o ,
A ⁰ ₁ x ⁰ _o-1 , A ⁰ ₂ x ⁰ _o-2 , −B ⁰ ₁ y ⁰ _o-1 , −B ⁰ ₂ y ⁰ _o-2 .
Adder 229 adds the outputs of FIFO memories 224 and ₂₂₅₂ . Further, the adder 230 adds the addition result of the adder 229 and the output of the FIFO memory 227 ₃ . Further, the adder 231 adds the outputs of the FIFO memories 226 ₂ and 228 ₃ .
Then, the adder 232 adds the addition results of the adders 230 and 231. The addition result of this adder 232 is A ⁰ ₀ x ⁰ _o +A ⁰ ₁ x ⁰ _o-1 +A ⁰ ₂ x ⁰ _o-2 −B ⁰ ₁ y ⁰ _o-1 −B ⁰ ₂
y ⁰ _o-2 is the gate clock signal as the primary calculation result y ⁰ _o
It is output from the gate 233 in response to T〓. below,
Similarly, when digital audio data x ¹ _o+2 is input and stored in the FIFO memory 202, the adder 232 adds the addition result A ¹ ₀ x ¹ _o + A ¹ ₁ x ¹ _o-1 + A ¹ ₂ x ¹ _{o -2} −B ¹ ₁ y ¹ _o-1 −B ¹ ₂
y ⁰ _o-2 is output, ... digital audio data x ¹⁵ _o+2 is
When input and stored in the FIFO memory 202, the adder 232 outputs the addition result A ¹⁵ ₀ x ¹⁵ _o +A ¹⁵ ₁ x ¹⁵ _o-1 +A ¹⁵ ₂ x ¹⁵ _o
-2
Output −B ¹⁵ ₁ y ¹⁵ _o-1 −B ¹⁵ ₂ y ¹⁵ _o-2 . In this way, the same digital audio data x _o of the input audio sampled in a certain period T is 2 times the corresponding period T.
After the period, the data is converted into 16 channels of digital audio data (primary calculation results) y ⁰ _o to y ¹⁵ _o and taken out.
Thereafter, in the same way, every cycle T takes a time T/16 (T=
Digital audio data x _o+1 , x _o+2 at intervals of 125 ns)
16 channels of digital audio data (1
Next operation results) y ⁰ _o+1 ~ y ¹⁵ _o+1 , y ⁰ _o+2 ~ y ¹⁵ _o+2 ... are extracted.

In other words, in this embodiment, the multiplication results required in the next cycle, the multiplication results required after two cycles, and the multiplication results required after three cycles are obtained within the same cycle (and simultaneously), and these three types of multiplication results are obtained at the same time. Multiplication results for 16 channels, 1 cycle each (time 125ns)
FIFO memory 22 during, 2 cycles, and 3 cycles
4, FIFO memory 225, 226, FIFO memory 2
27,228. And these
FIFO memory 224, FIFO memory 225, 22
6. Multiplication results in the corresponding cycle (two cycles before) output from the FIFO memories 227 and 228,
Using the multiplication results in the previous cycle and the multiplication results in the previous cycle, the addition process according to the IIR filter model is repeatedly executed for 16 channels at intervals of 125ns/16 within a constant cycle T (T = 125ns). do. In other words, in this embodiment, 16 pieces of the same digital audio data are stored in the first cycle, and in the second cycle,
Three types of multiplication results for 16 channels using digital audio data (and primary calculation results) (multiplication result required in the next cycle, multiplication result required after 2 cycles, multiplication result required after 3 cycles) ) is stored, and in the third cycle, the multiplication results required after the above two and three cycles are stored, and in the fourth cycle, the multiplication results required after the above three cycles are stored. In the fifth cycle, predetermined addition processing is performed, and so-called pipeline processing is performed in which primary calculation results (digital audio data) for 16 channels are extracted. That is, according to this embodiment, it is possible to obtain primary calculation results for 16 channels in each period according to the sampling period of the input audio, and these calculation speeds are faster than the multipliers 219 to 223 and the adders 229 to 23.
Since it is determined by pure hardware processing speed such as 2,
Significantly faster processing can be expected compared to conventional methods. Moreover, this embodiment does not require complicated microprogram control. Regarding the operation in the pipeline arithmetic circuit at the next stage (final stage), the pipeline arithmetic circuit at the previous stage (first stage) converts the digital audio data x ⁱ _o of the input audio into the primary operation result (digital audio data as) y ⁱ _o , and the parameters A ⁰ ₀ ~ A ¹⁵ ₀ , A ⁰ ₁ ~ A ¹⁵ ₁ , A ⁰ ₂ ~ ^{A 15} ₂ , −B ⁰ ₁ ~ −
B ¹⁵ ₁ , −B ⁰ ₂ ~ −B ¹⁵ ₂ as A' ⁰ ₀ ~ A' ¹⁵ ₀ , A' ⁰ ₁ ~ A' ¹⁵ ₁
,A′ ⁰ ₂ ~
The operation corresponds to the case where A′ ¹⁵ ₂ , −B′ ⁰ ₁ to −B′ ¹⁵ ₁ , −B′ ⁰ ₂ to −B′ ¹⁵ ₂ , so the explanation will be omitted.

Next, another embodiment of the present invention will be described with reference to FIGS. 4 and 5. Note that the same parts as in FIGS. 2 and 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 4 shows the configuration of the first-stage pipeline arithmetic circuit. 450 is a register, and the register 450 receives input from the gate 213 in response to the gate clock signal T (input audio).
digital audio data x ⁱ _o of time T/16, i.e.
Holds for 125ns/16. 451 is a FIFO memory (sixth FIFO memory) in which five types of parameters A ⁱ ₀ , A ⁱ ₁ , A ⁱ ₂ , -B ⁱ ₁ , -B ⁱ ₂ are stored in advance in a fixed order for 16 channels. In this embodiment, these parameters are stored in the FIFO memory 451 as A ⁰ ₀ ,
A ⁰ ₁ , A ⁰ ₂ , −B ⁰ ₁ , −B ⁰ ₂ , A ¹ ₀ , A ¹ ₁ , A ¹ ₂ , −B ¹ ₁ , −B ¹
₂ ,
...A ¹⁵ ₀ , A ¹⁵ ₁ , A ¹⁵ ₂ , −B ¹⁵ ₁ , −B ¹⁵ ₂ are stored one parameter at a time, and the time is 125 ns/(16×5)
One parameter is output at intervals of . 452 inputs the parameters output from the FIFO memory 451 to the gate clock signal T
This is a gate whose output is controlled in response to a gate clock signal T with a period of 125 ns/(16×5) synchronized with .
In this embodiment, the parameters output from the gate 452 are input again to the FIFO memory 451. However, FIFO memory 4
From 51, each parameter takes one parameter at a time.
They are repeatedly output in the order in which they are stored at intervals of 125 ns/(16×5). 453 is a gate for initializing parameters, and 454 is 1 output from gate 233.
This is a register in which the next operation result (as digital audio data) y ⁱ _o is held for a time of 125 ns/16.

A selector 455 selects either the output of the register 450 (digital audio data x ⁱ _o ) or the output of the register 454 (primary operation result y ⁱ _o ). In this embodiment, the selector 455 selects the output of the register 450 three times and the output of the register 454 twice during a certain period of 125 ns/16. That is, the selector 455 is
A timing signal T〓 ₁ with a period of 126ns/16 is synchronized with the first clock of 5 clocks of the gate clock signal T〓 generated during one period (125ns/16) of the gate clock signal T〓, and is also synchronized with the second clock. Timing signal T〓 ₂ with period 125ns/16,
...Period also synchronized with the 5th clock
125ns/16 timing signal T = ₅ timing,
The output of register 450, register 450, respectively.
output of register 450, register 454
and the output of register 454 are repeatedly selected.

456 is the output of the gate 452 and the selector 455
This is a multiplier that performs multiplication with the output of gate 4
52 and the selector 455, A ⁱ ₀ , A
It switches in the order of x ⁱ _o , A ⁱ ₁ , x ⁱ _o , A ⁱ ₂ , x ⁱ _o , -B ⁱ ₁ , y ⁱ _o , -B ⁱ ₂ , y ⁱ _o . Therefore, the multiplier 456
Multiplication of parameter A ⁱ ₀ by digital audio data x ⁱ _o , multiplication of parameter A ⁱ ₁ by digital audio data x ⁱ _o , multiplication of parameter A ⁱ ₂ by digital audio data x ⁱ _o during 125ns/16 , the parameter -B ⁱ ₁ is multiplied by the primary calculation result y ⁱ _o , and the parameter -B ⁱ ₂ is multiplied by the primary calculation result y ⁱ _o . That is, in this embodiment, the input timing to the multiplier 456 is set to 5 times the gate clock signal T, and five types of parameter multiplication are executed during a time of 125 ns/16. 5 multipliers 21
One multiplier 456 can play the roles of 9 to 223. Furthermore, according to this example, 5 types×
Since parameters for 16 channels are stored in one FIFO memory 451, five FIFO memories 203 to 20 are used as in the previous embodiment.
Unlike the configuration in which 1 type x 16 channels are stored separately in 7, only one FIFO memory control unit is required, which simplifies the configuration.

457 is an output destination switching unit that outputs the multiplication result of the multiplier 456 to one of the FIFO memories 224 to 228. The output destination switching unit 457 includes gates 458 to 462 provided corresponding to the FIFO memories 224 to 228. These gates 4
58 to 462 convert the multiplication results of the multiplier 456 into the timing signals T〓 ₁ , T〓 ₂ , T〓 ₄ , T〓 ₃ , T〓 ₅
The data are output to the corresponding FIFO memories 224 to 228 according to the data. As mentioned above, the input of the multiplier 456 is inputted at a time of _125ns /( ₁₆ ×
5), and accordingly, the multiplication result of the multiplier 456 also takes a time of 125ns/(16×5).
is switching between. That is, multiplier 456
is the multiplication result of 5 types A ⁱ ₀ x ⁱ _o , A ⁱ ₁ during time 125ns/16
x ⁱ _o , A ⁱ ₂ x ⁱ _o , −B ⁱ ₁ y ⁱ _o , −B ⁱ ₂ y ⁱ _o for time 125ns/(16×
5) is output at intervals of 5). These multiplication results A ⁱ ₀ x ⁱ _o , A ⁱ ₁ x ⁱ _o , A ⁱ ₂ x ⁱ _o , -B ⁱ ₁ y ⁱ _o , -B ⁱ ₂ y ⁱ _o are then outputted by the output switching section 457. The signals are then output to the corresponding FIFO memories 224, 225, 227, 226, and 228 at intervals of 125 ns/(16×5) during a period of 125 ns/16. The subsequent operations are the same as those in the previous embodiment, so the explanation will be omitted.

FIG. 5 shows the configuration of the next stage (final stage) pipeline arithmetic circuit, which has basically the same configuration as the previous stage (initial stage) pipeline arithmetic circuit as in the previous embodiment. 550 to 554 are the register 450, FIFO memory 451, and gate 4 in FIG. 4, respectively.
52, gate 453, register similar to register 454, FIFO memory, gate, gate, register. However, the register 550 holds not the digital audio data x ⁱ _o of the input audio, but the previous stage calculation result (digital audio data) y ⁱ _o . In addition, the FIFO memory 551 has 16 five types of parameters A' ⁱ ₀ , A' ⁱ ₁ , A' ⁱ ₂ , -B' ⁱ ₁ , -B' ⁱ _{2 .}
Parameters for each channel are stored in advance in a fixed order. Further, the register 554 holds the output of the gate 333, that is, the final calculation result z ⁱ _o in this embodiment. 556 and 557 are multipliers and output destination switching units similar to the multiplier 456 and output destination switching unit 457 in FIG. 4, and 558 to 562 are fourth
These gates are similar to gates 458 to 462 in the figure. Regarding _the operation of the pipeline _arithmetic circuit shown ⁱⁿ FIG ^. There is only a difference in parameters, but the basic operation is the same as the 4th one.
Since the operation corresponds to the operation of the pipeline arithmetic circuit shown in the figure (first stage), the explanation will be omitted.

In the above embodiment, a case has been described in which pipeline arithmetic circuits are connected in two stages and five types of parameters are prepared for 16 channels, but it is needless to say that the present invention is not limited to this.

As described in detail above, according to the cyclic secondary filter circuit for speech recognition of the present invention, high-speed processing by pipeline calculation is possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an IIR filter model, FIGS. 2 and 3 are block diagrams showing an embodiment of a pipeline calculation circuit applied to the present invention, and FIGS. 4 and 5 are pipeline calculation circuits. FIG. 7 is a block diagram showing another embodiment of the circuit. 202~207,224~228,225 ₁ ~
228 ₁ , 225 ₂ ~ 228 ₂ , 227 ₃ , 228 ₃ ,
302-307, 324-328, _{325 1-3}
28 ₁ , 325 ₂ ~ 328 ₂ , 327 ₃ , 328 ₃ , 4
51,551...FIFO memory, 219-223,
319-323,456,556...multiplier, 22
9-232...Adder, 455,555...Selector, 457,557...Output destination switching unit.

Claims (1)

[Claims] 1. Consisting of multiple stages of pipeline arithmetic circuits, this pipeline arithmetic circuit converts input audio into analog/digital data at regular intervals T to convert digital audio data or the previous stage. Digital audio data that is the n-1 (however, n≧2) order calculation result given at time T/N intervals from the pipeline arithmetic circuit of , or the primary or By performing multiplication of digital audio data, which is the result of n-th calculation, by M kinds of linear regression type parameters specific to each channel in a certain order within a certain period T for N channels, L ₁
L multiplication results required in the next cycle, and M _{multiplication} results required in the next cycle
-(L ₁ +L ₂ ) multiplication results for each channel in a fixed order at time intervals of T _/ N; , by sequentially storing the multiplication results, the multiplication results for each N channel in the corresponding cycle are stored, and L ₁ first FIFO (first-in-first・Out) memory corresponds to each of the L _two multiplication results output from the multiplication section, and the multiplication results are sequentially stored to store information for each N channel in the corresponding cycle and the previous cycle. The multiplication results are stored in _L2 second FIFO memories which are outputted in the order in which they were input at time intervals of T/N, and the M-( _L1) output from the multiplier.
+L ₂ ) multiplication results, and by sequentially storing the multiplication results, the corresponding period, 1
The multiplication results for each N channel in the previous cycle and the next cycle are stored, and the time T/N
M-(L ₁ +
L ₂ ) third FIFO memories and these L ₁ third FIFO memories.
1 FIFO memory, L ₂ second FIFO memories, and M-(L ₁ + L ₂ ) third FIFO memories, each with a corresponding cycle of the same channel, which is sequentially output for one channel at time T/N intervals in the order in which they are stored; L ₁ in the previous cycle and in the previous cycle
A predetermined addition/subtraction process is performed based on the multiplication results of L ₂ , L 2, and M-(L ₁ + L ₂ ), and the result is digital as a first-order or n-th calculation result for each channel at time T/N intervals. An audio device comprising an addition/subtraction unit that outputs audio data, and separating digital audio data obtained by analog/digital conversion of input audio into different frequency bands and extracting the digital audio data for N channels. Cyclic secondary filter circuit for recognition. 2. The cyclic secondary filter circuit for speech recognition according to claim 1, wherein the second FIFO memory is formed by cascading two FIFO memories having the same structure as the first FIFO memory. 3. The cyclic secondary filter circuit for voice recognition according to claim 2, wherein the third FIFO memory is formed by cascading three stages of FIFO memories having the same structure as the first FIFO memory. 4 The multiplier section converts the input audio into analog/digital data at fixed intervals T, or digital audio data provided from the preceding stage pipeline calculation circuit at time T/N intervals. A 4th FIFO memory is stored sequentially at time T/N intervals and outputs in the order inputted at time T/N intervals, and corresponds to the M types of linear regression type parameters described above, each of which has one type for N channels. M fifth FIFO memories which are stored in advance in a fixed order and which read and output the M types of linear regression type parameters repeatedly for each channel at time T/N intervals in the stored order; between the linear regression type parameters provided corresponding to K pieces and given at time intervals T/N from the corresponding fifth FIFO memory and the digital audio data commonly given at time intervals T/N from the fourth FIFO memory. K first multipliers that perform multiplication of
M-- which performs multiplication between linear regression type parameters given at N intervals and digital audio data commonly given at time T/N intervals from the output of the own stage.
4. The cyclic secondary filter circuit for speech recognition according to claim 1, further comprising K second multipliers. 5. The cyclic secondary filter circuit for speech recognition according to claim 4, characterized in that M=5, L ₁ =1, and L ₂ =2. 6 The multiplier section converts digital audio data obtained by analog/digital conversion of the input audio at regular intervals T, or digital audio data provided at time T/N intervals from the pipeline arithmetic circuit at the previous stage. A fourth FIFO memory is stored in sequence at time T/N intervals and outputs in the order inputted at time T/N intervals, and the above-mentioned M types of linear regression type parameters are stored in advance in a fixed order for N channels, and the above-mentioned A sixth FIFO memory that repeatedly reads and outputs linear regression type parameters in the order in which they are stored at intervals of time T/(N×M), digital audio data given from the fourth FIFO memory at intervals of time T/N, and the output of the own stage. a selector that selects one of the digital audio data given at time T/N intervals from , at time T/(M×N) intervals, and multiplication between the selection output of this selector and the output of the sixth FIFO memory. an output unit that outputs the multiplication results of the multiplier by repeatedly switching one output unit from the M output units in a fixed order at intervals of time T/(N×M); 4. A cyclic secondary filter circuit for voice recognition according to claim 1, further comprising a first switching section. 7 The selector selects and outputs the digital audio data provided from the fourth FIFO memory at time T/N intervals three times during time T/N, and outputs the digital audio data provided from the output of the own stage at time T/N.
7. The cyclic secondary filter circuit for speech recognition according to claim 6, wherein the selection is made twice during N.