JPS6359648A - Portable medium - Google Patents

Abstract

PURPOSE:To improve the accuracy of a clock function and to reduce a power consumption by constituting a clock means which counts a clock by a first clock generation means and an arithmetic means which is made to act by a second clock generation means and executes a specified arithmetic processing, etc., in the same medium. CONSTITUTION:An accurate clock generation means is additionally set for the clock function besides the clock generation means for the arithmetic function. Namely, an oscillator (the second clock generation means) 27 which is a crystal vibrator for an arithmetic clock oscillation and outputs 1MHz of oscillation frequency (high frequency) signal, a timer 32 which is used for the clock during processing actions a calandar circuit 33, the oscillator (the first clock generation means) 34 which is the crystal oscillator for a basic clock oscillation and always outputs 32.768kHz of oscillation frequency (low frequency and high accuracy) signal, etc., are provided. If an IC card is inserted in a terminal equipment, the contact part 11 of the IC card is connected to the connection part inside the terminal equipment and when the external power source voltage is supplied, a power source control circuit 23 switches to the drive of the external power source voltage from the drive of the internal battery 25.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) This invention has a built-in CPIJ, data memory, internal battery, etc., and can be used alone in the snow or inserted into a terminal. Multifunctional IC used by
Regarding portable media such as cards.

(Prior Art) Conventionally, there are card-shaped calculators, IC cards, etc., which are thin (on cards) and have calculation and storage functions. However, although some of these devices have a calculation function and a timekeeping function, all of them have one oscillator. Therefore, the above-mentioned oscillator has a high frequency for calculation purposes, and high accuracy with respect to the oscillation frequency is not required. Therefore, as a timekeeping function, it is only used to grasp the temporal relationship.
It was not possible to provide a highly accurate timekeeping function. Furthermore, since the oscillator for calculations is driven by a high-frequency clock, it consumes a large amount of power when used for a timekeeping function, and has the drawback that the battery capacity ff1 (life span) does not last for many years.

(Problems to be Solved by the Invention) As mentioned above, this invention eliminates the disadvantages of not being able to provide a highly accurate timekeeping function and not being able to reduce power consumption. It is an object of the present invention to provide a portable medium that can be provided with functions and that can reduce power consumption.

[Configuration of the Invention (Means for Solving Problems) The portable medium of the present invention is operated by an internal power source, and the portable medium of the present invention is capable of measuring time by counting the clock generated by the first clock generating means. A clock means for performing processing and an arithmetic means operated by the second clock generating means for performing predetermined arithmetic processing etc. are constructed in the same medium.

(Function) In this invention, a highly accurate clock generating means is added for the timekeeping function in addition to the clock generating means for the performance II function.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 2, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The above-mentioned offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the clock being used by the user, a time change mode that changes the time of the clock that the user is using, an address, full name,
Electronic width mode for registering and reading phone numbers, etc., or using the IC card 10 with multiple credit cards,
It has a shopping mode where it can be used as a cash card.

On the surface of the IC card 10, there is a contact section (connection means) 11 arranged at a position that matches the card specifications, a keyboard section (input means) 12 consisting of 20 keys, and a liquid crystal display arranged on the top surface of this keyboard section 12. A display section (display means) 13 formed of a display element and a magnetism generating member 14 are provided.

The contact portion 11 includes a plurality of terminals 118 to 118, for example.
11h. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11C is for a clock signal, the terminal 11d is for a reset signal, and the terminals 118 to 11h are for data input/output.

The keyboard section 12 includes mode keys (Ml, M2, M3, M4) 12a for specifying processing modes.

It is composed of a numeric keypad 12b1 and four arithmetic operation keys (function keys) 12C.

The mode key 12a selects processing for calculator mode (Ml), time display mode (M2), electronic passbook mode (M3), or shopping mode (M4) when offline, that is, when processing is performed only with the IC card 10. It is supposed to be done. Further, in the shopping mode, processing corresponding to the type of card, ie, various credit cards, cash cards, etc., is selected according to the combination of the M4 key and the numeric keypad 12b.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating member 14 is aligned with the track position of a magnetic card reader (!1 head) on the reading side (not shown).
It is buried inside the C card 10.

FIG. 3 shows an ICC card reader 1 used in a terminal device such as a personal computer that handles the TC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, a 3-volt internal battery (built-in power supply) 25, and a battery check circuit that checks whether the voltage value of this internal battery 25 is above a specified value. 24,
A clock control circuit 26, an oscillator (second clock generation means) 27 which is a crystal oscillator for arithmetic clock oscillation and outputs a signal at the oscillation frequency (high frequency) of the IMH2, a CPU for control <central processing unit> )
28. Program RO in which the control program is recorded
M29, program working memory 30. The PIN number (for example, 4 digits) and data are recorded, and the PR
A data memory 31 consisting of an OM, a timer 32 used for timing during processing operations, a calendar circuit 33, and a crystal oscillator for basic clock oscillation, which always operates at 32.768 KH.
an oscillator (first clock generation means) 34 that outputs a signal with a second oscillation frequency (low frequency and high precision), a display control circuit 35, and a display driver 3 that drives the display section 13.
6. It is composed of a keyboard interface 38 as a key input circuit of the keyboard section 12, and a magnetism generating member control circuit 40 that controls the magnetism generating member 14.

Magnetism generation member control for controlling the communication control circuit 21, CPU 28, ROM 29, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generation member 14. The circuits 40 are adapted to be connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, that is, parallel data supplied from the data bus 2o, is converted into a serial input/output signal and output to the terminal 16 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal fl116 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts up the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. This is to switch to driving by the battery 25.

The clock control circuit 26 stops an oscillation circuit 67 that outputs a signal at an oscillation frequency (high frequency) of the IMI-12, which will be described later, during standby, that is, when the key is in standby mode, in an offline mode in which the card operates using the internal battery 25. , the clock supply to the CPU 28 is also stopped, and the CPU 28 stands by in a completely stopped state. Furthermore, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 is operated for 500 to 600 m5e until stable oscillation is performed.
During the period c, the clock is outputted as a clock for the CPU 28, and the first person's key is processed.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the watch clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation occurs, and then IM)-12 clock is output.

The data memory 31 records information corresponding to a plurality of contracted credit cards (companies) and information corresponding to cash cards, and corresponds to the type of card determined by the combination of the M4 key and the numeric keypad 12b. It is read out as follows. The above information is the same as the information recorded on the conventional magnetic stripe for each card.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, world standard time when the card is issued and cannot be changed thereafter. ing.

The display unit control circuit 35 converts the display data supplied from the CPLI 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPLI 28 into a character pattern using the display unit driver 36. It is to be displayed.

The keyboard interface 38 converts keys input on the keyboard section 12 into human input signals corresponding to keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data and reading device supplied from the data memory 31 via the data bus 20 in accordance with the card type. By controlling the drive of the magnetism generating member 14 and outputting magnetic information according to the drive rate corresponding to manual reading or automatic reading, the state is the same as when a conventional magnetic stripe exists. It is something that exists.

The power supply control circuit 23 will be explained in detail using FIG. 4. That is, inverter circuit 51.54.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the external power supply voltage VCC drops, before the semiconductor switch 56 is turned on, even if the I[Bli voltage Vcc drops below the memory drive voltage, the power supply voltage ■out It is protected by an internal battery 25 so that the power does not drop.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, if the IC card 10 is not connected to the terminal 16 through the contact section 11, the semiconductor switch 56 is on, so the 1
．． The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact portion 11, the external power supply voltage CC is supplied to the gate of the semiconductor switch 58, and the clock signal CLK is supplied to the counter via the inverter circuit 51. It is supplied to the clock terminal ck of 52. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. Due to the set output Q of the FF circuit 53, a "'0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 58 is turned on.
6 is off.

Therefore, the external power supply voltage Vcc is applied to each part via the semiconductor switch 58 as the output yout of the power supply control circuit 22.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the externally applied N voltage Vcc decreases. This results in
The reset signal causes the counter 52 and the FF circuit 53 to
is reset. Then, the "1" signal is supplied to the gate of the semiconductor switch 58, the 011 signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, %fll of internal battery 25! Ii pressure is semiconductor switch 5
6 is applied to each part as the output vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 6. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The clock input terminal ck of this FF circuit 63 is supplied with the machine cycle @M1 from the CPU 28. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input end of the FF circuit 65, and the clock input %ick of this FF circuit 65 is supplied with a clock of 32.763KH2 from the calendar circuit 33. . The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

Further, the key human interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62, 63, and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes the oscillator 27 having an oscillation frequency of 1 MH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock input terminal ck of this FF circuit 76 is supplied with an OR circuit 84, which will be described later.
output is supplied.

Further, the data input terminal D1 and the reset input terminal R of the FF circuit 76 are supplied with a clock selection signal from the CPtJ28. The set output of the FF circuit 76 is F
The data input terminal of the F circuit 77 is supplied with the clock input terminal ck of the FF circuit 77, and the 32°763 KH2 clock from the calendar circuit 33 is supplied with the clock input terminal ck of the FF circuit 77. The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the clock of 32.763KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via an inverter circuit 78. . The outputs of the seven NAND circuits are supplied to one end of the NAND circuit 8o.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal ck of the FF circuit 81.
The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 63 via an inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output of No. 3 is outputted to the clock input Oi Ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied as a clock selection signal from the CPU 28. As a result, the FF circuits 76 and 77 are set. As a result, the clock clock (32,768KH2) is sent to the inverter circuit 78 and the NAND circuit. It is led to FF circuits 81 and 82 and an inverter circuit 85 via circuits 79 and 80.

Next, restarting from a stopped state will be explained.

That is, a key human interrupt signal is supplied from the CPU 28. Then, the FF circuits 62, 63, and 64 are reset, and the FF circuit 65 is set.

The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 resumes oscillation.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
1" is supplied to the data input end of 1. As a result, the output of the NAND circuit 80 causes the FF number N81
．． 83 is set and the gate of the NAND circuit 86 is opened. Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0 to 600m5ec is required.

Thereby, the CPU 28 supplies "O" as a clock selection signal to the data input end of the FF circuit 76 500 to 600 m5ec after outputting the key human interrupt signal. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the °゛1'' signal is
It is supplied to the data input end of the F circuit 74.

Also, at this time, the clock (7M) 1 generated by the oscillation circuit 67
2) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (IMH2) generated by the oscillation circuit 67 is generated by the inverter circuit 72.73, the NAND circuit 75.80,
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

Thereby, by setting the clock selection signal to ri Oit, synchronization is achieved in the FF circuit 74, and the clock for clock is switched to the clock for high-speed processing.

Next, a case will be explained in which the processing is ended and the stopped state (standby state! The output, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is open.Therefore, the clock for the watch is supplied to the inverter circuit 78, the NAND circuit 79, 80, and the inverter circuit 85.
, and is sequentially output to the CPU 28 via the NAND circuit 86.

As a result, the watch clock is outputted to the CPJJ28 again.

Then, a stop signal is supplied from the CPLJ 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and this set output is the data input 1 of the FF circuit 63.
0. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and the FF@
An "O" signal is supplied to the data input end of the FF circuit 81. As a result, the set output of the FF circuit 63 is connected to the FF circuit 81.8.
After sending two pulses in step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of crystal oscillation caused by this, the clock for the watch and the clock for the IMH2 are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 7. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from outputs ma and b by dividing the oscillation output of the frequency dividing circuit 9.
A counter 92 that outputs a signal every 10 seconds by counting the signal from the output terminal a of 1;
A counter 93 that outputs a signal every 60 seconds, that is, every minute, by counting the signals from this counter 93, a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93, and a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93. A counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signals from this counter 95, and a counter 96 that outputs a signal every 24 hours, that is, every day, by counting the signals from this counter 95. A counter 97 outputs a signal every 10 seconds by counting the signal from the output terminal b of the circuit 91, and a signal is output every 60 seconds, that is, every minute by counting the signal from this counter 97. Counter 98, which outputs a signal every 10 minutes by counting the signal from this counter 98.
9. A counter 1 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 99.
00, and a counter 101 that outputs a signal every 24 hours, that is, every day by counting the signals from this counter 100.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, while the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. An interrupt request is output to the CPU 28 by the signal from 101. Thereby, the CPU 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. Furthermore, as shown in FIG. 8, the two clocks have a one-second reference clock phase shifted from each other, so that interrupts do not occur at the same time.

The magnetism generating member control circuit 40 will be explained in detail using FIG. 9. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 11
0 consists of four FF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or a start signal is output from the output terminal 110c. A clock selection signal corresponding to the drive rate for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

The clock input terminal cp of the FF circuit 110 has the above C
A command write start signal from the PU 28 is supplied. The clock selection signal corresponding to the drive rate indicates whether the terminal type is manual reading or automatic reading.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. A signal with a frequency of 8KH2 is supplied from an oscillator (not shown) to the input terminal A of this selection circuit 111, and the input terminal B
A signal with a frequency of 4KH2 is supplied from an oscillator (not shown).

The selection circuit 111 selects the input mA signal according to the clock selection signal from the FF circuit 110 when the terminal type is a manual reading type, and outputs it from the output terminal Y.
If the type of terminal is automatic reading, the signal at input terminal B is selected and output from output terminal Y.

The start signal output from the output @110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal c of parallel/serial conversion circuit 115
The first clock is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 selects a clock for data ``0'' and a clock for data ``1'' by a selection circuit 116.
is supplied to.

Further, the magnetic data (the size is small depending on the type of card selected) supplied from the CPU 28 via the data bus 20 is supplied to the data latch circuit 113. Start signal is supplied. The data latch circuit 113 latches 7 bits of magnetic data supplied from the data bus 20 when a data write start signal is supplied from the CPU 28.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal fN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
+i 1 i+ times signal or '0' signal) and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the clock for data "1" supplied from the timing circuit 112 when the "1P signal" is supplied to the input terminal S, and the "O" signal is supplied to the input terminal S. In this case, the data "" Cj it clock supplied from the timing circuit 112 is selected and output. The output of the selection circuit 116 is J-KF
The set output and reset output of this J-KFF circuit 117 are supplied to a driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 41a according to signals from the FF circuit 117hS and others. For example, the above FF
When the circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycle ratio for data "1" and "O" is 1:2. J-K with this clock
By operating the FF circuit 117 in the inversion mode, "1", ll O1 of the format required as magnetic data is generated.
Four signals are obtained to drive the magnetism generating member 41a.

Further, the data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the empty detection FF circuit 114, and the reset input terminal of this FF circuit 114 receives the first clock from the timing circuit 112. It is supplied inverted. As a result, when the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF circuit 114 is set and the FF circuit 1
14 set outputs, ie, buffer empty signals, are supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be set, and outputs the next data to the data latch circuit 113. In this way, the CPU 28 sets data in order while sensing the output of the empty detection FF circuit 114, and after outputting all the data, turns off the command write start signal and data write start signal. There is. As a result, the timing circuit 11
2 stops generating the signal, and the operation ends.

The circuits 111 to 118 are for the first track, and the circuits for the second track also include a selection circuit 119, a timing circuit 1201, a data latch circuit 121, an empty detection FF circuit 122, and a parallel/ Serial conversion circuit 123, selection circuit 124, J-KFF circuit 12
5, and a driver 126. However, the portions where the timing circuit 120 operates in the 5 series are different.

As described above, the magnetism generating member control circuit 40 generates a magnetic field in accordance with the magnetic data of a predetermined credit card or cash card selectively read out from the data memory 31, thereby generating a magnetic field on the reading device side. A head (not shown) is provided with the same signals as when reading a conventional magnetic stripe.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the calculator mode is designated using the mode key 128, that is, the M1 key, the calculator can be used as a calculator using the numeric keypad 12b and the four arithmetic operation keys 12c.

When the time display mode is specified by pressing the mode key 128, that is, the M2 key, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97, 101 in the calendar circuit 33, and also reads the seconds, minutes, and hours from the data memory. 3
Read the year, month, day and day of the week for the display clock from 1,
Convert it to the specified format and display it in the display control circuit 35.
Output to. Thereby, the display unit control circuit 35 uses an internal character generator (not shown) to convert it into a character pattern, and displays it on the display unit 13 using the display unit driver 36.

Furthermore, when the electronic width mode is specified using the mode key 12a, that is, the M3 key, the CPU 28 uses the data memory 31
The address, name, telephone number, etc. stored in the computer are read out and displayed on the display section 13. Further, when registering the above-mentioned address, name, etc. in the electronic space, the user uses, for example, the numeric keypad 12b. That is, rAJ is "1.1", rBJ is "1.2", rCJ is "1.3", and rDJ is "2.1".
,... can be specified by entering.

When the shopping mode is specified using the mode key 12a, that is, the M4 key, the type of contracted credit card or cash card is selected using the numeric keypad 12b.
and the type of output terminal, that is, whether the reading is manual or automatic. Then, the CPU 28 reads the data memory 31
The data (72 characters) corresponding to the selected credit card or cash card are read out and output to the magnetism generating member control circuit 4o. Also, C.P.
U28 outputs a drive rate corresponding to the selection of manual type or automatic type to the magnetism generating member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

As a result, the magnetism generating member control circuit 40 causes the magnetic head (not shown) on the reading device side to read the conventional magnetic stripe by generating a magnetic field from the magnetism generating member 41a according to the magnetic data of the credit. The same signal is provided as if the

As a result, in shopping mode, it can be used as a conventional credit card.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. Accordingly, when an external power supply voltage is supplied via the contact portion 11, the power supply control circuit 23 switches from driving by the internal battery 25 to driving by the external power supply voltage, as described above. In addition, the reset control circuit 2
2 generates a reset signal and starts the CPU 28. After this activation, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. This online processing involves exchanging data and writing new data into the IC card 10 by updating data between the terminal device 16 and the IC card 1o.

As described above, a highly accurate oscillator is added for the timekeeping function in addition to the oscillator for the performance function. This makes it possible to provide a highly accurate timekeeping function, reduce power consumption, and extend the life of the battery.

In the above embodiment, an IC card is used, but the IC card is not limited to this, as long as it has a data memory and a control element, and selectively performs input/output from the outside, and the shape is not card-like. , or other shapes such as a rod shape.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a portable medium that can have a highly accurate timekeeping function and can reduce power consumption.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a diagram showing a schematic configuration of an electric circuit of an IC card, and FIG.
Figure 3 is a plan view showing the configuration of an IC card, Figure 3 is a diagram showing a terminal that handles IC cards, Figure 4 is a diagram showing an example of the configuration of a power supply control circuit, and Figure 5 shows the main parts of Figure 4. A timing chart for explaining the operation, Figure M6 is a diagram showing the configuration of the clock control ηU circuit, Figure 7 is a schematic block diagram of the calendar circuit, and Figure 8 is a diagram showing the output timing of the signal from the frequency dividing circuit. , FIG. 9 is a diagram showing an example of the structure of the magnetism generating member control circuit, and FIGS. 10 and 11 are timing charts for explaining the operation of the main parts in FIG. 9. DESCRIPTION OF SYMBOLS 10... IC card (portable medium), 11... Contact part, 12... Keyboard part, 13... Display part, 14... Magnetism generating member, 16... Terminal, 21
...Communication control circuit, 23...Power supply control circuit, 25.
・Internal battery, 26 ・Clock control circuit, 27
...Oscillator (second clock generation means), 28...
CPU (control element), 31... data memory, 33
... Calendar circuit, 34 ... Oscillator (first clock generation means), 38 ... Keyboard interface, 40 ... Magnetism generating member control circuit, 67 ... Oscillation circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) In a portable medium that is operated by an internal power source, there is a clock means that performs timekeeping processing by counting the clock generated by the first clock generation means, and a clock means that is operated by the second clock generation means and performs a predetermined time measurement. 1. A portable medium comprising a calculation means for performing calculation processing etc. in the same medium. (2) The portable medium according to claim 1, wherein the first clock generating means generates a clock having a lower frequency than the second clock generating means. (3) The portable medium according to claim 1, wherein the first and second clock generation means are oscillators.