JPS6358520A - Portable medium - Google Patents

Abstract

PURPOSE:To eliminate noise produced at the time of switching a power supply and also to prevent changeover of the power supply due to mischief as well as malfunction, of an internal circuit for improvement of reliability, by providing a contact part to which an external power supply is applied and a power supply switching means. CONSTITUTION:When an IC card 10 is not connected to a terminal equipment, the power supply voltage of an internal battery 25 is applied to each part as an output VouT via a semiconductor switch 56. While the external power supply voltage Vcc is applied to the gate of a semiconductor switch 58 together with a clock signal CLK supplied to a counter 52 when the card 10 is connected to the terminal equipment via contact part 11. When the counter 52 has the prescribed count value, an FF 53 is set with the output of the counter 52 together with switches 58 and 56 turned on and off, respectively. Thus the voltage Vcc is applied to each part as the output VouT via the switch 58. Then it is possible to eliminate the noise produced at the time of switching a power supply and to prevent changeover of the power supply due to mischief as well as malfunction of the internal circuit together with improvement of reliability.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, timepieces, etc., or as a terminal device. The present invention relates to a portable medium such as a multifunctional IC card that can be used by inserting the card.

(Prior Art) Conventionally, multifunctional IC cards have been developed that have a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, time, etc., or can be used by being inserted into a terminal. In such an IC card, depending on whether or not it is connected to a terminal, it is necessary to switch between driving by voltage from an external power source or voltage from an internal battery. This switching is done by external
It is conceivable to add one diode to each of the power source and internal battery, and connect the cathode side of each diode.

However, in the above-mentioned device, when switching the power supply, chattering caused by the contact section to the external power supply is accepted in the card, and if the contact section of the card is tampered with, the power supply is easily switched.
There is a problem that the internal circuit malfunctions. This results in
The reliability of the card was decreasing.

(Problems to be Solved by the Invention) As mentioned above, this invention eliminates the drawbacks of malfunctioning internal circuits and reduced reliability, and it is possible to accept a power supply from which chattering and noise have been removed when switching power supplies. It also prevents the power from being switched due to mischief.
Furthermore, it is an object of the present invention to provide a portable medium that can prevent malfunctions of internal circuits and improve reliability.

[Structure of the Invention] (Means for Solving the Problems) A portable medium of the present invention includes a control element and a built-in power supply for operating the control element, in which a contact portion to which power is supplied from the outside is provided. Then, after a predetermined period of time has passed since external power was supplied to this contact part,
The power source for operating the control element is comprised of switching means for switching the power source for operation of the control element from the built-in power source to an external power source.

(Function) According to the present invention, after a predetermined period of time has elapsed since external power was supplied to the contact section, the operating power of the control element is switched from the built-in power supply to the external power supply.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 3, numeral 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The above offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the clock used by the user, an electronic width mode that allows you to register and read out addresses, names, phone numbers, etc. I
The mode includes a shopping mode in which the C card 10 is used as a credit card.

On the surface of the IC card 10, a contact section 11 is arranged at a position that matches the card specifications.A keyboard section 12 consisting of 20 keys is arranged on the top surface of the keyboard section 12, and a display section is formed of a liquid crystal display element. 13, and a magnetism generating member 14 are provided.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11a.
llh. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11c is for a clock signal, the terminal 11d is for a reset signal, and the terminals lie to llh are for data input/output.

The keyboard section 12 has mode keys (Ml, M2, M3, M4) 12a for specifying processing modes.

It is composed of a numeric keypad 12b1 and four arithmetic operation keys (function keys) 12c.

The mode key 12a selects the operation for calculator mode (Ml), time display mode (M2), electronic passbook mode (M3), or shopping mode (M4) when offline, that is, when processing only with the IC card 10. It is supposed to be done.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating member 14 is inserted into the IC in accordance with the track position of a magnetic card reader (magnetic head) on the reading side (not shown).
It is embedded inside the card 10.

FIG. 4 shows an IC card reading/writing unit 1 used in a terminal such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, a 3-volt internal battery (built-in power supply) 25, and a battery check circuit that checks whether the voltage value of this internal battery 25 is above a specified value. 24,
Clock control circuit 26, oscillator 27 that outputs the oscillation frequency signal of IMH2, control CPU (central φ
processing unit) 28, a program ROM 29 in which a control program is recorded, a program working memory 30, a data memory 31 in which a password (for example, 4 digits), data, etc. are recorded, and is constituted by a FROM; A timer 32 used for time measurement, a calendar circuit 33, always, 32. ．． an oscillator 34 outputting a signal with an oscillation frequency (low frequency) of 768 KH2, a display control circuit 35, a display driver 36 for driving the display 13, a keyboard interface 38 as a key input circuit for the keyboard 12, and a magnetism generating member control circuit 40 that controls the magnetism generating member 14.

The communication control circuit 21, CPU 28, ROM 29, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generating member control for controlling the magnetism generating member 14. The circuits 40 are adapted to be connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
At the time of transmission, that is, parallel data supplied from the ``''-'' data bus 20 is converted into a serial human output signal and outputted to the terminal 16 via the contact section 11. In this case, the format content of the conversion is
It is defined as card 1o.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. This is to switch to driving by the battery 25.

The clock control circuit 26 stops an oscillation circuit 67 that outputs a signal at an oscillation frequency (high frequency) of the IMH 2, which will be described later, during standby, that is, when the key is in standby mode, in an offline mode in which the card operates with the internal battery 25.
Furthermore, the supply of clocks to the CPU 28 is also stopped, and the CPU 28 stands by in a completely stopped state. Further, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 outputs the clock for the clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation is performed. - processing is performed.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the clock as a clock for the CPU 28 for 500 to 6 oOmsec until stable oscillation occurs, and then It is designed to output the IMH2 clock.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets the standard time of escape when the card is issued and cannot be changed thereafter. are doing.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern on the display unit 13 using a display unit driver 36. It is to be displayed.

The keyboard interface 38 converts keys input on the keyboard section 12 into human input signals corresponding to keys, and outputs the signals to the CPU 2g.

When the shopping mode is specified, the magnetism generating member control circuit 40 responds to the data supplied via the data bus 20 and the drive rate corresponding to whether the reading device is manual reading or automatic reading. By controlling the drive of the magnetism generating member 14 and outputting magnetic information, the same state as when a conventional magnetic stripe exists is created.

-1- The power distribution control circuit 23 will be explained in detail using FIG. 1. That is, inverter circuits 51, 54 .
55, counter 52, D-type flip-flop circuit (FF
circuit) 53, semiconductor switch 56, 58 composed of MOSFET, diode 57, and internal battery 25
It is made up of.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the power supply voltage Vcc from the outside decreases, the power supply voltage Vout will not drop even if the power supply voltage Vcc drops below the memory drive voltage before the semiconductor switch 56 is turned on. As shown, it is protected by an internal battery 25.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. Due to the set output Q of the FF circuit 53, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned on.
turns off. Therefore, the external power supply voltage Vcc is applied to the output V of the power supply control circuit 22 via the semiconductor switch 58.
It is applied to each part as out.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external power supply voltage Vcc decreases. Thereby, the counter 52 and the FF circuit 53 are reset by the reset signal. Then, the semiconductor switch 58
A “1” signal is supplied to the gate of the semiconductor switch 56.
A 0° signal is supplied to the gate of , the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. therefore,
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

2, when going from an offline state to an online state, that is, when moving from a state where voltage from the internal battery 25 is output to a state where voltage from the terminal device 16 is output, the clock supplied from the terminal device 16 is used. The above switching is performed when a predetermined time has elapsed. This allows the terminal device 16 to output after the voltage is stabilized. In other words, chattering and noise are removed before output.

Therefore, when switching the power supply as described above, the power supply from which chattering and noise have been removed can be received into the IC card 10. Furthermore, it is possible to prevent the power source from being switched due to mischief. This can prevent malfunctions of the internal circuit and improve reliability.

The clock control circuit 26 will be explained in detail using FIG. 6. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input terminal of the FF circuit 65, and the clock input terminal ck of this FF circuit 65 is supplied with the clock of 32.763KH2 from the calendar circuit 33. . The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

In addition, the key manual interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are as follows:
It is supplied via the OR circuit 61 to the reset input terminal R of the FF circuits 62, 63, and 64, and also to the set input terminal S of the FF circuit 65.

The oscillation circuit 67 includes an oscillator 27 having an oscillation frequency of IMH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal Ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock input terminal ck of this FF circuit 76 is supplied with an OR circuit 84, which will be described later.
output is supplied.

Further, a clock selection signal from the CPU 28 is supplied to the data input terminal D5 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is FF
It is supplied to the data input end of the circuit 77, and this FF circuit 7
A clock input terminal Ck of 7 is supplied with a clock of 32.763 KH2 from the power render circuit 33. The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the clock of 32.763KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via an inverter circuit 78. . The output of the NAND circuit 79 is supplied to one end of a NAND circuit 80.

In addition, the reset output of the two-leg FF circuit 77 is the two-leg FF circuit 77.
This FF circuit 7 is supplied to the data input end of the circuit 74.
The set output of 4 is supplied to the other end of the NAND circuit 75.

The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal ck of the FF circuit 81.
The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 63 via an inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output No. 3 is outputted to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output as a clock signal to the upper t6cP U28.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. As a result, the FF circuits 76 and 77 are set. Thereby, the watch clock (32,768 KHz) is guided to the FF circuit 81.82 and the inverter circuit 85 via the inverter circuit 78 and the NAND circuit 79.80.

Next, restarting from a stopped state will be explained.

That is, a key human interrupt signal is supplied from the CPU 28. Then, the FF circuits 62, 63 and 64 are reset, and the FF circuit 65 is set.

The oscillation circuit 67 is enabled by the set output of the second FF circuit 65. As a result, the oscillation circuit 67 resumes oscillation.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
“1” is supplied to the data input end of “1”. As a result, the output of the NAND circuit 80 causes the FF circuit 8 to
1.83 sets and opens the gate of NAND circuit 86. Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0 to 600m5ec is required.

Thereby, the CPU 28 supplies "0" as a clock selection signal to the data input end of the FF circuit 76 500 to 600 m5ec after outputting the key human interrupt signal. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the "1" signal is
It is applied to the data input end of circuit 74.

Also, at this time, the clock (I MH
Z) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (IMH2) generated by the oscillation circuit 67 is transmitted to the inverter circuit 72.73, the NAND circuit 75.8o,
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

Thereby, by setting the clock selection signal to "0", synchronization is achieved in the FF circuit 74, and the clock is switched from the clock for high-speed processing to the clock for high-speed processing.

Next, a case will be described in which the processing is ended and the system is placed in a stopped state (standby state). That is, by setting the clock selection signal to "1", the FF circuits 76 and 77 are set, the set output of the FF circuit 77, that is, the °1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is opened. Therefore, the clock for the watch consists of the inverter circuit 78, the NAND circuit 79.80, and the inverter circuit 85.
, and is sequentially output to the CPU 28 via the NAND circuit 86.

As a result, the clock is outputted to the CPO 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input terminal of the FF circuit 81. As a result, the set output of the FF circuit 63 is changed to the set output of the FF circuit 81.8.
After sending two pulses in step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuits 26 are connected to the oscillator 2.
In order to cover the rising edge of crystal oscillation caused by 7, the watch clock and IMH2 clock are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 7. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the frequency dividing circuit 9.
A counter 92 that outputs a signal every 10 seconds by counting the signal from the output terminal a of 1;
A counter 93 outputs a signal every 60 seconds, that is, every minute, by counting the signals from the counter 94. Counter 94 outputs a signal every 10 minutes by counting the signals from the counter 93. , Counter 95 outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 94, and outputs a signal every 24 hours, that is, every day, by counting the signal from this counter 95. A counter 96 outputs a signal every 10 seconds by counting the signal from the output terminal of the frequency dividing circuit 91.A counter 97 outputs a signal every 10 seconds by counting the signal from the counter 97. A counter 98 that outputs a signal every 10 minutes by counting the signal from this counter 98. A counter 99 that outputs a signal every 10 minutes by counting the signal from this counter 99. It consists of a counter 100 that outputs a signal, and a counter 101 that outputs a signal every 24 hours, that is, every day by counting the signals from this counter 100.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. For the year, month, day and day of the week, an interrupt request is output to the CPU 28 based on a signal from the counter 96.101 every 24 hours. Thereby, the CPU 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. Furthermore, as shown in FIG. 8, the phases of the two clocks' base clocks of one second are shifted, so that interrupts do not occur at the same time.

- The magnetism generating member control circuit 40 will be explained in detail using FIG. 9. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 1
10 consists of four OFF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or a start signal is output from the output terminal 110C. A clock selection signal corresponding to the driving rate (mi) for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

The clock input terminal cp of the FF circuit 110 has the above C
A command write start signal from the PU 28 is supplied. The clock selection signal corresponding to the drive rate indicates whether the terminal type is manual reading or automatic reading.

The clock selection signal output from the output terminal 1'lOa of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. The input terminal A of this selection circuit 111 is supplied with a signal having a frequency of 8 KHz from an oscillator (not shown), and the input terminal B is supplied with a signal having a frequency of 4 KH2 from an oscillator (not shown).

In response to the clock selection signal from the FF circuit 110, the selection circuit 111 selects the signal at the input terminal A and outputs it from the output terminal Y when the terminal type is a manual reading type.
If the type of terminal is automatic reading, the signal at input terminal B is selected and output from output terminal Y.

The start signal output from the output end 110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal c of parallel/serial conversion circuit 115
The first clock dS is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has data “0”.
circuit 116 for selecting the clock for data “1” and the clock for data “1”
is supplied to.

Further, magnetic data supplied from the CPU 28 via the data bus 2o is supplied to a data latch circuit 113, and a data write start signal is supplied from the CPU 28 to this data latch circuit 113. The data latch circuit 113 latches 7 bits of magnetic data supplied from the data bus 20 when a data write start signal is supplied from the CPU 28.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the 1R number (“1” signal or °0" signal) and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the clock for data 1° supplied from the timing circuit 112 when a "1" signal is supplied to the input terminal S, and when a "0" signal is supplied to the input terminal S. , the data "0° clock" supplied from the timing circuit 112 is selected and output. The output of the selection circuit 116 is supplied to the J-KFF circuit 117. The set output and reset output are supplied to the driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 41a in response to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycles are at a ratio of 1:2 for data m1" and °0°. With this clock, J-KF
By operating the F circuit 117 in the inversion mode, "1°, °0° signals in the format required as magnetic data are obtained, and the magnetic field generating member 41g is driven.

Further, the data write start signal from the CPυ28 is inverted and supplied to the set input terminal of the empty detection FF circuit 114, and the reset input terminal of this FF circuit 114 receives the first clock from the timing circuit 112. It is supplied inverted. As a result, when the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF11 path 114 is set, and the set output of the FF circuit 114, that is, the buffer empty signal is supplied to the CPU 28.

As a result, the CPO 28 determines that the next data can be set, and outputs the next data to the data latch circuit 113. In this way, the CPU 2R sets the data in order while sensing the output of the empty detection FF circuit 114, and after outputting all the data, turns off the command write start signal and the data write start signal. There is. As a result, the timing circuit 11
2 stops generating the signal, and the operation ends.

The circuits 111 to 118 described above are for the first track, and the circuits for the second track also include a selection circuit 119, a timing circuit 120, a day latch circuit 121, an empty detection FF circuit 122, Parallel/serial conversion circuit 123, selection circuit 124, J-KFF circuit 12
5, and a driver 126. However, the locations where the timing circuit 120 operates in five ways are different.

As described above, the magnetism generating member control circuit 40
By generating a magnetic field in accordance with the magnetic data of a predetermined credit card supplied from Pυ28, the same signal as when reading a conventional magnetic stripe is supplied to the magnetic head (not shown) on the reader side. It has become so.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the calculator mode is designated using the mode key 12a, that is, the M1 key, the calculator can be used as a calculator using the numeric keypad 12b and the four arithmetic operation keys 12c. .

Further, when the time display mode is specified using the mode key 12g, that is, the M2 key, the CPU 28 reads out the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and displays them from the data memory 31. The year, month, day, and day of the week for the business clock are read out, converted to the specified format and format, and output to the display control circuit 35. Thereby, the display unit control circuit 35 uses an internal character generator (not shown) to convert it into a character pattern, and displays it on the display unit 13 using the display unit driver 36.

Furthermore, when the electronic width mode is specified using the mode key 12a, that is, the M3 key, the CPU 28 uses the data memory 31
The address, name, telephone number, etc. stored in the computer are read out and displayed on the display section 13. Further, when registering the above-mentioned address, name, etc. in the electronic space, the user uses, for example, the numeric keypad 12b. That is, rAJ is "1.1", rBJ is "1.2", rCJ is "1.3", and rDJ is "2.1".
,... can be specified by entering.

Further, when the shopping mode is specified using the mode key 128, that is, the M4 key, the type of contracted credit card and the type of output terminal, that is, whether reading is manual or automatic, are selected. Then, the CPU 28 retrieves data (from the data memory 31) corresponding to the selected credit.
72 characters), and the magnetism generating member control circuit 40
Output to. Further, the CPU 28 outputs a drive rate corresponding to the selection of manual type or automatic type to the magnetism generating member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

As a result, the magnetic generation member control circuit 40 applies a magnetic field to the magnetic generation member 41a according to the magnetic data of the "-" credit.
As a result, a magnetic head (not shown) on the reader side is supplied with the same signal as when reading a conventional magnetic stripe.

As a result, in shopping mode, it can be used as a conventional credit card.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. As a result, when an external power supply voltage is supplied via the contact portion 11, the mi control circuit 23 switches from being driven by the internal battery 25 to being driven by the external power supply voltage, as described above. In addition, the reset control circuit 2
2 generates a reset signal and starts the CPU 28. After this activation, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. This online processing involves exchanging data and writing new data into the IC card 10 by updating data between the terminal 16 and the IC card 10.

Note that although an IC card is used in the above embodiment, the IC card is not limited to this, as long as it has a data memory and a control element, and selectively performs input/output from the outside, and the shape is not card-like. , or other shapes such as a rod shape.

[Effects of the Invention] As detailed above, according to the present invention, when switching the power supply, it is possible to accept a power supply from which chuckling and noise have been removed, it is possible to prevent the power supply from being switched by mischief, and it is also possible to prevent internal circuits from being switched. It is possible to provide a portable medium that can prevent malfunctions and improve reliability.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a diagram showing an example of the configuration of a power supply control circuit, and FIG. 2 is a timing chart for explaining the operation of the main parts in FIG. 1. FIG. 3 is a plan view showing the configuration of the IC card, FIG. 4 is a diagram showing a terminal that handles the IC card, FIG. 5 is a diagram showing the schematic configuration of the electric circuit of the IC card 2, and FIG. 6 is a clock control diagram. 7 is a schematic block diagram of the calendar circuit, FIG. 8 is a diagram showing the output timing of signals from the frequency dividing circuit, and FIG. 9 is an example of the configuration of the magnetic generation member control circuit. 10 and 11 are timing charts for explaining the operation of the main parts in FIG. 9. DESCRIPTION OF SYMBOLS 10... IC card (portable medium), 11... Contact part, 12... Keyboard part, 13... Display part, 14... Magnetism generating member, 16... Terminal, 21
...Communication control circuit, 23...Power supply control circuit, 25.
... Internal battery (built-in power supply), 26... Clock control circuit, 27... Oscillator, 28... CPU (control element), 31... Data memory, 33... Calendar circuit, 34... - Oscillator, 38... Keyboard interface, 40... Magnetism generating member control circuit, 52.
... Counter, 56.58 ... Semiconductor switch, 67
...Oscillation circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Silk Figure 10 Silk Figure 11

Claims (3)

[Claims] (1) In a portable medium having a control element and a built-in power supply for operating the control element, a contact portion to which an external power is supplied, and a predetermined period of time after the external power is supplied to the contact portion. A portable medium comprising: a switching means for switching the operating power source of the control element from the built-in power source to an external power source after a certain period of time has elapsed. (2) The portable medium according to claim 1, which is a multifunctional medium having a keyboard, a display section, or a clock function. (3) The switching of the switching means is performed by counting clocks supplied from the outside through the contact portion and when this counted value reaches a predetermined value. portable media.