JP2597553B2 - IC card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a multifunctional IC card which incorporates, for example, a CPU, a data memory, an internal battery, etc., and can display a calculator, a time, and the like. .

(Conventional technology) Conventionally, a multi-functional device that has a built-in CPU, data memory, internal battery, etc. and uses a card such as a calculator and time display by itself or inserts into a terminal to transfer data
IC cards are being developed.

In such an IC card, the time of the clock circuit can be freely set and changed by a card holder, and is used as a substitute for a display clock (such as a wristwatch).

However, in the case of the above, if it is used to limit the expiration date of the IC card, or if it is used as part of the transaction contents at the time of the transaction, the time of the clock circuit will be changed,
There was a case where an IC card was used illegally. Conversely, if the time of the clock circuit cannot be changed by the card holder, the time of the clock circuit cannot be changed when used overseas or the like, and cannot be used as a substitute for a display clock (watch, etc.) Its use range was restricted.

(Problems to be Solved by the Invention) The present invention eliminates the above-mentioned drawbacks and performs appropriate processing using time data from a clock circuit without limiting the range of use as a display clock. For example, it is to provide an IC card that can be used as a part of transaction contents at the time of transaction or to limit an expiration date.

(Means for Solving the Problems) An IC card according to the present invention is capable of performing a transaction within a predetermined expiration date. Storage means for storing a transaction limit representing an upper limit of a transactable amount, a first means for counting reference signals and counting time data
Clock means, display means for displaying the time data counted by the first clock means when no transaction is performed, and externally input the contents of the change in the time data by the first clock means displayed on the display means. Input means for inputting a transaction amount at the time of a transaction, a second signal which counts a reference signal and counts time data different from the first clock means, and wherein the input means does not allow input of a change content. A clock means for comparing the expiration date stored in the storage means with the time data of the second clock means which cannot be changed by the input means to determine whether the expiration date of the IC card has passed; Judging means, when the first judging means judges that the expiration date has passed, stores the information indicating that the expiration date has passed in the storage means, and displays the display means when conducting a transaction. A first processing means for displaying information indicating that the expiration date has passed, and a transaction input by the input means when conducting a transaction when the first judging means judges that the expiration date has not passed. Second determination means for comparing the amount with the transaction amount limit stored in the storage means to determine whether or not the transaction can be performed; and, when the second determination means determines that the transaction can be performed, the storage means Means for storing the time data at which the transaction was performed and the transaction amount using the time data by the second clock means, updating the transaction limit, and providing the display means with information indicating that the transaction is permitted. It is composed of a second processing means for displaying.

(Function) The present invention uses the time data of the first clock means, which can change the contents of the time data from the outside by the input means, for time display, restricts the expiration date of the IC card, and displays the transaction contents at the time of the transaction. As a part, time data different from that of the first clock means is counted, and time data of the second clock means which cannot be changed by the input means is used.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 3, reference numeral 10 denotes an IC card as a portable medium, which is a multifunctional card having various functions. For example, it has an online function used by using a terminal described later, an offline function in which the IC card 10 operates alone, and a waiting state in which only a clock is counted.

The offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time of a clock used by a user, a time change mode that changes the time of a clock used by a user, an address, and a name. , An electronic book mode for registering and reading out telephone numbers and the like, or a shopping mode for using the IC card 10 as a credit card.

On the surface of the IC card 10, a contact part (connection means) 11, a keyboard part (input means) 12 composed of 20 keys, and a keyboard part 12
A display section (display means) 13 formed of a liquid crystal display element and a magnetism generating member 14 are provided.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11h
It is constituted by. The terminal 11a is for an operation power supply voltage (+5 V, Vcc), the terminal 11b is for ground, the terminal 11c is for a clock signal, the terminal 11d is for a reset signal, and the terminals 11e to 11h.
Is for data input / output.

The keyboard section 12 includes a mode key (M1, M2, M3, M4) 12a for designating a processing mode, a numeric keypad 12b, and a four-rule operation key (function key) 12c.

The mode key 12a is used when offline, that is, when processing is performed only with the IC card 10, in a calculator mode (M1), in a time display mode (M2), in an electronic passbook mode (M3), or in a terminal that supports a magnetic stripe. Select the operation for the mode (M4), select the operation for the time change mode by turning on the M2 key twice in succession, and use the combination of the M4 key and the numeric keypad 12b for the offline shopping mode without using a terminal. Is to be selected.

The display unit 13 is a dot matrix of 5 × 7 in one digit, and has a 16-digit display.

The magnetism generating member 14 is embedded in the IC card 10 in accordance with the track position of a magnetic card reader (magnetic head) on the reading side (not shown).

FIG. 4 shows the appearance of an IC card read / write unit 16 used in a terminal that handles the IC card 10, such as a personal computer. That is, by connecting to the contact portion 11 of the IC card 10 inserted from the card insertion slot 17, data in the memory of the IC card 10 is read or data is written in the memory.

The IC card read / write unit 16 is connected to a main body (not shown) of a personal computer by a cable.

The electric circuit of the IC card 10 is configured as shown in FIG. That is, the contact portion 11,
Communication control circuit 21, reset control circuit 22, power supply control circuit 2
3, for example 3 volt internal battery (built-in power supply) 25,
A battery check circuit 24 for checking whether the voltage value of the internal battery 25 is equal to or higher than a prescribed value, a clock control circuit 26, an oscillator 27 for outputting a signal having an oscillation frequency of 1 MHz, a control CPU (Central Processing Unit) ) 2
8, program ROM29 in which the control program is recorded,
A program working memory 30, a personal identification number (for example, 4 digits), data and the like are recorded and a PROM data memory 31, a timer used for timing during processing operation
32, a calendar circuit 33, a crystal oscillator for oscillating a basic clock, which constantly outputs a signal having an oscillation frequency (low frequency) of 32.768 kHz, a display unit control circuit 35, and drives the display unit 13 Display driver 36, keyboard part
Keyboard interface as 12 key input circuits
And a magnetic generating member control circuit 40 for controlling the magnetic generating member.

The communication control circuit 21, the CPU 28, the ROM 29, the program working memory 30, the data memory 31, the timer 32, the calendar circuit 33, the display unit control circuit 35, the keyboard interface 38, and the magnetic generating member control for controlling the magnetic generating member 14. The circuit 40 is adapted to be connected by the data bus 20.

The communication control circuit 21 converts a serial input / output signal supplied from the terminal 16 via the contact section 11 into parallel data at the time of reception, that is, outputs the data to the data bus 20. The parallel data supplied from 20 is converted into a serial input / output signal and output to the terminal 16 via the contact section 11. In this case, the format of the conversion is determined by the terminal 16 and the IC card 10.

The reset control circuit 22 generates a reset signal when going online, and starts the CPU.

When the power supply control circuit 23 goes online, it switches from driving by the internal battery 25 to external power supply after a predetermined time elapses, and when it goes offline, that is, when the external voltage decreases, the power supply control circuit 23 Battery 25
The drive is switched to the drive by

The clock control circuit 26 is in an off-line mode in which the card operation is performed by the internal battery 25, during standby,
In other words, during key input standby, the oscillator circuit 67 that outputs a signal of an oscillation frequency (high frequency) of 1 MHZ described later is stopped, and the CPU 2
The supply of the clock to 8 is also stopped, and the apparatus stands by in a completely stopped state. Further, the clock control circuit 26 includes:
When the oscillation circuit 67 is restarted from the stop state, the clock for the clock is set to the CPU 28 for 500 to 600 msec until stable oscillation is performed.
For the first input key.

Further, when the clock control circuit 26 is online, that is, when a reset signal is supplied, the clock clock is used for 500 to 600 msec until stable oscillation is performed.
The clock is output as a clock for the CPU 28, and then a 1 MHZ clock is output.

The data memory 31 records the validity period of the card itself. This valid period corresponds to the capacity of the internal battery 25. Further, the validity period may be set for each registered credit card and cash card, not for the validity period of the card itself.

In the data memory 31, an account number and a transaction limit of a cash card that can perform offline processing in the shopping mode are recorded.
The transaction limit is updated each time a transaction is performed. Further, a transaction number as a result of performing the above transaction is recorded in a transaction status recording area (not shown). The transaction number is a watch 102
Is encrypted data using the date, the purchase amount, and the account number corresponding to.

The calendar circuit 33 sets a display clock (first clock means) 103 whose setting can be freely changed by the card holder and, for example, a standard time of the world at the time of issuing the card. Clock for trading (second clock means) 10
And 2. The timepiece 102 is connected to the display unit 13
The time display by is prohibited.

The display control circuit 35 converts the display data supplied from the CPU 28 into a character pattern by using a character generator (not shown) constituted by an internal ROM.
This is displayed on the display unit 13 using the display unit driver 36.

The keyboard interface 38 is a keyboard unit.
Convert to the key input signal corresponding to the key input in step 12
This is output to the CPU 28.

When the shopping mode is designated, the magnetism generating member control circuit 40 responds to data supplied via the data bus 20 and a drive rate corresponding to whether the reading device is a manual reading or an automatic reading. By driving and controlling the magnetism generating member 14 to output magnetic information, it is in the same state as the existing magnetic stripe.

The power supply control circuit 23 will be described in detail with reference to FIG. That is, inverter circuits 51, 54, 55, counter 52, D-type flip-flop circuit (FF circuit) 53, MOSF
ET semiconductor switches 56 and 58, diode 57,
And an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. Above diode 57
Is for the protection of the power supply voltage Vout,
When the power supply voltage Vcc falls below the drive voltage of the memory before the semiconductor switch 56 is turned on when the power supply voltage Vcc decreases, the internal battery 25 protects the power supply voltage Vout so as not to decrease.

In such a configuration, the operation will be described with reference to the timing chart shown in FIG. That is, IC card
When the terminal 10 is not connected to the terminal 16 by the contact section 11, the semiconductor switch 56 is turned on, so that the power supply voltage of the internal battery 25 is output to the respective sections as the output Vout of the power control circuit 22 via the semiconductor switch 56. Applied.

When the IC card 10 is connected to the terminal 16 via the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58 and the clock signal CL is supplied.
K is supplied to the clock terminal ck of the counter 52 via the inverter circuit 51. Thus, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the output terminal
The FF circuit 53 is set by the output of Qn. This FF circuit 53
Signal "0" is supplied to the gate of the semiconductor switch 58, and "1"
The signal is supplied, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned off. Therefore, external power supply voltage
Vcc is the output V of the power control circuit 22 through the semiconductor switch 58.
Out is applied to each part.

When returning from the online state to the offline state,
When the external power supply voltage Vcc decreases, a reset signal is output from the reset control circuit 22. Thus, the counter 52 and the FF circuit 53 are reset by the reset signal. Then, a “1” signal is supplied to the gate of the semiconductor switch 58, a “0” signal is supplied to the gate of the semiconductor switch 56, and the semiconductor switch 58 is turned off.
56 turns on. Therefore, the power supply voltage of the internal battery 25 is output from the output Vout of the power supply control circuit 22 through the semiconductor switch 56.
Is applied to each part.

The clock control circuit 26 will be described in detail with reference to FIG. That is, the stop signal HAL from the CPU 28
T is supplied to the clock input terminal ck of the FF circuit 62. This FF
The set output of the circuit 62 is supplied to the data input terminal D of the FF circuit 63, and the clock input terminal ck of the FF circuit 63 is connected to the CPU 2
The machine cycle signal M1 from 8 is supplied. The FF circuits 62 and 63 are used for stop mode timing. the above
The set output of the FF circuit 63 is supplied to a data input terminal D of the FF circuit 64, and a clock input terminal ck of the FF circuit 64 is supplied with a clock for a clock of 32.763 KHZ from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to a data input terminal D of the FF circuit 65, and a clock input terminal ck of the FF circuit 65 is supplied with a clock of 32.763KHZ from the calendar circuit 33. The FF circuit 65 is for stopping clock oscillation. The set output of the FF circuit 65 is
The signal is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output terminal and the other end of the NAND circuit 66.

Further, the key input interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are transmitted to the reset input terminals R of the FF circuits 62, 63, 64 via the OR circuit 61.
And the set input terminal S of the FF circuit 65
Supplied to

The oscillation circuit 67 includes an oscillator 27 having an oscillation frequency of 1 MHz, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and is also supplied to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

The reset signal from the reset control circuit 22 is
The output is supplied to a set input terminal S of the FF circuit 76, and an output of an OR circuit 84 described later is supplied to a clock input terminal ck of the FF circuit 76. A clock selection signal from the CPU 28 is supplied to the data input terminal D and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is supplied to a data input terminal D of the FF circuit 77, and a clock input terminal ck of the FF circuit 77 is connected to the 32.763KHZ from the calendar circuit 33.
Clock is supplied. The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the other end of the NAND circuit 79 is supplied with a clock for a clock of 32.763 KHZ from the calendar circuit 33 via an inverter circuit 78. The output of the NAND circuit 79 is supplied to one end of the NAND circuit 80.

The reset output of the FF circuit 77 is supplied to a data input terminal D of the FF circuit 74, and the set output of the FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to a NAND circuit 80, and the output of the NAND circuit 80 is supplied to a clock input terminal ck of FF circuits 81 and 83. 63 set outputs are supplied via an inverter circuit 82.

The set output of the FF circuit 81 and the reset output of the FF circuit 83 are output to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

The set output of the FF circuit 83 is supplied to one end of a NAND circuit 86, and the output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85.
The output of the NAND circuit 86 is the clock signal CP
Output to U28.

The operation in such a configuration will be described. First, the stop state will be described. That is, “1” is supplied from the CPU 28 as a clock selection signal. Thus, the FF circuits 76 and 77 are set. Thus, the clock for clock (32.768 kHz) is guided to the FF circuits 81 and 82 and the inverter circuit 85 via the inverter circuit 78 and the NAND circuits 79 and 80.

Next, restarting from a stopped state will be described. That is, a key input interrupt signal is supplied from the CPU 28. Then, the FF circuits 62, 63, and 64 are reset, and the FF circuit 65 is set. The oscillation circuit 67 is set by the set output of the FF circuit 65.
Is enabled. As a result, the oscillation circuit 67 restarts oscillation.

Further, “1” is supplied to the data input terminal D of the FF circuit 81 due to the reset of the FF circuit 63. This allows
The FF circuits 81 and 83 are set by the output of the NAND circuit 80, and the gate of the NAND circuit 86 is opened. Therefore, the clock for the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, it is usually 500
~ 600msec is required. Thereby, the CPU 28 outputs the key input interrupt signal, and after 500 to 600 msec,
“0” is supplied to the data input terminal D of the FF circuit 76 as a clock selection signal. As a result, the FF circuits 76 and 77 are reset, and the reset output of the FF circuit 77, that is, the “1” signal is output from the FF circuit 74.
Is supplied to the data input terminal D.

At this time, the clock (1 MHz) from the oscillation circuit 67 is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the gate of the NAND circuit 75 is opened by the set output. As a result, the oscillation circuit
The clock (1MHZ) by 67 is applied to the inverter circuits 72, 73,
The signals are sequentially output to the CPU 28 via NAND circuits 75 and 80, an inverter circuit 85, and a NAND circuit 86.

By setting the clock selection signal to "0", the FF circuit 74 synchronizes and switches from the clock for clock to the clock for high-speed processing.

Next, a case where the process is terminated and the system is brought into a stopped state (standby state) will be described. That is, by setting the clock selection signal to “1”, the FF circuits 76 and 77 are set,
The set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is open. Therefore, the clock for clock is output to the CPU 28 via the inverter circuit 78, the NAND circuits 79 and 80, the inverter circuit 85, and the NAND circuit 86 in order.

As a result, the clock for the clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input terminal D of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input terminal D of the FF circuit 63.
Then, the FF is supplied by the machine cycle signal M1 from the CPU 28.
The circuit 63 is set, and a “0” signal is supplied to the data input terminal D of the FF circuit 81. As a result, the set output of the FF circuit 63 is
After two pulses are sent by the FF circuits 81 and 83, the output of the clock to the CPU 28 is stopped by closing the gate of the NAND circuit 86. As a result, the CPU 28 is stopped.

The set output of the FF circuit 63 is 2 in the FF circuits 64 and 65.
After the pulse has been sent, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

Thus, after the output of the clock to the CPU 28 is stopped, the oscillation circuit 67 is stopped.

As described above, the clock control circuit 26 effectively switches between the clock for clock and the clock for 1 MHz in order to cover the rising of the oscillation of the crystal by the oscillator 27.

The calendar circuit 33 will be described in detail with reference to FIG. In other words, by dividing the oscillation output of the 32.768 kHz oscillator 34, signals every one second are output from the output terminals a and b.
A frequency divider circuit 91 outputs a signal from the output terminal a of the frequency divider circuit 91. The counter 92 outputs a signal every 10 seconds, and a signal from the counter 92 is counted. A counter 93 that outputs a signal every second, that is, every minute, a counter 94 that outputs a signal every 10 minutes by counting the signal from this counter 93, and a counter 94 that outputs a signal every 10 minutes, for 60 minutes That is, a counter 95 that outputs a signal every hour, a counter 96 that outputs a signal every 24 hours by counting the signal from the counter 95, a signal 96 that outputs a signal every day, and a signal from the output terminal b of the frequency dividing circuit 91. The counter 97 outputs a signal every 10 seconds by counting the counter, and the counter 98 outputs a signal every 60 seconds, that is, every minute by counting the signal from the counter 97. A counter 99 that outputs a signal every 10 minutes by counting signals, a counter 100 that outputs a signal every 60 minutes, that is, every hour by counting signals from this counter 99, and a signal from this counter 100 And outputs a signal every 24 hours, that is, every day.

Here, a counter clock (second clock means) 102 for counting seconds, minutes, and hours by the counters 92 to 96 is configured.
The above-mentioned counters 97 to 101 constitute a display clock (first clock means) 103 for counting seconds, minutes and hours. The contents of the counters 97 to 101, that is, the count value, can be changed by the keyboard unit 12, and the contents of the counters 92 to 96, that is, the count value, cannot be changed by the keyboard unit 12.

In addition, the date and day of the week are counted by a counter 9 every 24 hours.
6. An interrupt request is output to the CPU 28 according to the signals from 101. As a result, the CPU 28 updates the date, month and day of the corresponding area using the data memory 31.

Also, when the above date, month and day are updated, CPU2
8 reads the validity period from the data memory 31,
, Ie, the date corresponding to the clock 102. As a result of the comparison, if the expiration date of the validity period of the card has passed, data prohibiting use of the card is recorded in the data memory 31.

If the use of this card is prohibited, the next IC card
Display that the expiration date has passed when using 10
13 is notified.

Also, as shown in FIG. 2, the two watches 102 and 103
Because the phase of the reference 1 second clock is shifted,
At the same time, no interrupt is generated.

The magnetism generating member control circuit 40 will be described in detail with reference to FIG. That is, the command data supplied from the CPU 28 via the data bus 20 is used for the command.
It is supplied to the FF circuit 110. The FF circuit 110 is composed of four FF circuits, and according to command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track from the output terminal 110a, a start signal from the output terminal 110b, or A clock selection signal corresponding to the drive rate for the second track from output terminal 110c, output terminal 110d
Outputs a start signal. The above FF circuit 11
The command write start signal from the CPU 28 is supplied to the clock input terminal cp of 0. The clock selection signal corresponding to the driving rate indicates whether the type of the terminal is manual reading or automatic reading.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal s of the selection circuit 111. An input terminal A of the selection circuit 111 is supplied with a signal having a frequency of 8 KHz from an oscillator (not shown), and an input terminal B is supplied with a signal having a frequency of 4 KHz from an oscillator not shown. The selection circuit 111 selects the signal of the input terminal A according to the clock selection signal from the FF circuit 110 and outputs the signal from the input terminal A when the terminal type is the manual reading, and outputs the signal from the output terminal Y. In the case of the automatic reading, the signal at the input terminal B is selected and output from the output terminal Y.

The start signal output from the output terminal 110b of the FF circuit 110 and the output of the selection circuit 111 are supplied to the timing circuit 112. The timing circuit 112 generates a seven-digit clock, supplies it to the clock input terminal cp of the parallel / serial conversion circuit 115, and supplies the first clock to the load input terminal L of the parallel / serial conversion circuit 115 as a load signal. The timing circuit 112 selects a clock for data “0” and a clock for data “1”.
6 to supply.

The magnetic data supplied from the CPU 28 via the data bus 20 is supplied to a data latch circuit 113. The data latch circuit 113 is supplied with a data write start signal from the CPU 28. The data latch circuit 113
When the data write start signal is supplied from the CPU 28, the 7-bit magnetic data supplied from the data bus 20 is latched.

The data latched by the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel / serial conversion circuit 115 for bits. The above parallel / serial conversion circuit
115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (“1” signal or “0” signal). And output it.

The output of the parallel / serial conversion circuit 115 is supplied to the input terminal s of the selection circuit 116. This selection circuit 116
When the “1” signal is supplied to the input terminal S, the data “1” clock supplied from the timing circuit 112 is selected and output. When the “0” signal is supplied to the input terminal S, The data “0” clock supplied from the timing circuit 112 is selected and output. The above selection circuit
The output of 116 is supplied to a J-KFF circuit 117, and the set output and reset output of the J-KFF circuit 117 are supplied to a driver 118.

The driver 118 generates a magnetic field by driving the magnetism generating member 41a according to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, a magnetic field as shown by an arrow c is generated,
When reset, a magnetic field as shown by an arrow d is generated.

The timing chart of the main part of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG. 11, the clock cycle is 1: 2 with respect to the data “1” and “0”.
The ratio is. By operating the J-KFF circuit 117 in the inversion mode with this clock, "1" and "0" signals of a format required as magnetic data are obtained, and the magnetic generating member 41a is driven.

Also, the data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the FF circuit 114 for empty detection, and the reset input terminal of the FF circuit 114 receives the first clock from the timing circuit 112. It is supplied inverted. Thereby, when the data of the data latch circuit 113 is loaded into 115, the FF circuit 11
4 is set, and the set output of the FF circuit 114, that is, the buffer empty signal is supplied to the CPU.

As a result, the CPU 28 determines that the next data set is possible, and stores the next data in the data latch circuit 113.
Output to In this way, the CPU 28 sequentially sets data while sensing the output of the empty detection FF circuit 114, outputs all data, and then issues a command write start signal,
The data write start signal is turned off. Thus, the generation of the signal by the timing circuit 112 stops, and the operation ends.

Each of the circuits 111 to 118 is a circuit for the first track, and a circuit for the second track is also a selection circuit as described above.
119, a timing circuit 120, a data latch circuit 121, an empty detection FF circuit 122, a parallel / serial conversion circuit 123, a selection circuit 124, a J-KFF circuit 125, and a driver 126. However, the point where the timing circuit 120 operates in quinary is different.

As described above, the magnetic generation member control circuit 40
By generating a magnetic field according to the predetermined credit card magnetic data supplied from U28, the same signal as when reading a conventional magnetic stripe is supplied to a magnetic head (not shown) on the reader side. It has become.

Next, the operation in such a configuration will be described. First, the offline function used by the card alone will be described. That is, when the calculator mode is designated by the mode key 12a, that is, the M1 key, the ten key 12b and the four arithmetic operation keys 1
Can be used as a calculator with 2c.

When the time display mode is designated by pressing the mode key 12a, that is, the M2 key once, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97 and 101 in the calendar circuit 33, and The year, month, day, and day of the week for the display clock are read from the data memory 31, converted into a specified format, and output to the display control circuit 35.
As a result, the display control circuit 35 converts the character pattern into a character pattern using an internal character generator (not shown), and displays the character pattern on the display 13 using the display driver 36.

When the time change mode is designated by twice pressing the mode key 12a, that is, the M2 key, the operation is performed in the same manner as in the time display mode, and the second, minute, hour, year, month, day, and day of the week are displayed on the display unit 13. To display. Then, the setting change is instructed using the numeric keypad 12b. Thereby, the CPU 28 changes the corresponding setting contents, that is, the count values of the counters 97 and 101 and the contents of the data memory 31. In this case, the contents to be changed are sequentially changed by turning on the mode key 12a.

When the electronic book mode is designated by the mode key 12a, that is, the M3 key, the CPU 28 reads the address, name, telephone number, and the like stored in the data memory 31, and
Display at 13. In addition, when registering the address, name, and the like in the electronic book, the registration is performed using, for example, the numeric keypad 12b.
That is, “A” is “1, 1”, “B” is “1, 2”,
"C" can be designated by inputting "1, 3", "D" by inputting "2, 1",....

When the shopping mode using a terminal capable of reading the magnetic stripe is designated by the mode key 12a, that is, the M4 key, the type of the contract credit card and the type of the output terminal, that is, whether the reading is manual or automatic Select Then, the CPU 28 reads data (72 characters) corresponding to the selected credit from the data memory 31.
And outputs it to the magnetism generating member control circuit 40. Also,
The CPU 28 outputs a drive rate corresponding to the selection between the manual type and the automatic type to the magnetism generating member control circuit 40. further,
CPU28 sends command data, command write start signal and data write start signal to the magnetic member control circuit
Output to 40.

As a result, the magnetic generating member control circuit 40 reads a conventional magnetic stripe by a magnetic head (not shown) on the reader side by generating a magnetic field corresponding to the magnetic data of the credit from the magnetic generating member 41a. The same signal is supplied as in the case. As a result, in the shopping mode, it can be used as a conventional credit card.

When the user selects the offline shopping mode without using the terminal by inputting the mode key 12a, that is, the M4 key and the numeric keypad 12b, the CPU 28 determines the offline processing using the cash card and determines the account number corresponding to the cash card. And the transaction limit are read from the data memory 31. Next, a date and a purchase amount are entered using the numeric keypad 12b. Then, the CPU 28 compares the purchase amount with the transaction limit and determines whether or not the transaction can be performed. As a result of this determination, if the transaction can be performed, the CPU 28 performs encryption using the account number, the date and the amount corresponding to the clock 102 as keys, and uses the encrypted data as the transaction number in the data memory 31.
Record in the transaction status recording area in. Also, the CPU 28
The transaction number and the transaction permission are displayed on the display unit 13. As a result, the clerk at the transaction (purchase) destination enters the transaction number in the purchase table indicating that the transaction has been made and hands it over to the card holder.

As a result, when confirming whether or not the purchase (shopping) has been performed, the transaction number is obtained from the account number, date, and amount, so that it is known whether the transaction has been performed.

Next, an online function used by inserting the IC card 10 into the terminal 16 will be described. That is, the IC card 10 is inserted into the insertion slot 17 of the terminal device 16. Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the IC card
Ten contact portions 11 are connected. Thus, when an external power supply voltage is supplied through the contact portion 11,
As described above, the power supply control circuit 23 switches from driving by the internal battery 25 to driving of an external power supply voltage. The reset control circuit 22 generates a reset signal,
Start 8 After this startup, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. In the online processing, data is exchanged between the terminal 16 and the IC card 10 to exchange data or to write new data in the IC card 10.

As described above, the crystal oscillator for basic clock oscillation is shared, two clock counting units are provided, and the counting value of one of the counting units can be freely changed by the keyboard unit on the IC card. The other counting section is configured so that the setting of the counting value cannot be changed from the keyboard section on the IC card. As a result, a clock whose time can be changed by the keyboard can be used for the time display,
As the time used for the validity period restriction, the encryption key, and the like, it is possible to use a clock whose time is common to each card whose time cannot be set by the keyboard unit.

[Effects of the Invention] As described above in detail, according to the present invention, an appropriate process can be performed using time data by a clock circuit without limiting the range of use as a substitute for a display clock, For example, it is possible to provide an IC card that can limit the expiration date or can be used as a part of the transaction contents at the time of the transaction.

[Brief description of the drawings]

1 is a block diagram showing a schematic configuration of a calendar circuit, FIG. 2 is a diagram showing an output timing of a signal from a frequency dividing circuit, and FIG.
FIG. 4 is a plan view showing a configuration of an IC card, FIG. 4 is a diagram showing a terminal that handles the IC card, FIG. 5 is a diagram showing a schematic configuration of an electric circuit of the IC card, and FIG. FIG. 7, FIG. 7 is a timing chart for explaining the operation of the main part in FIG. 6, FIG. 8 is a diagram showing a configuration of a clock control circuit, and FIG. 9 is a configuration example of a magnetic generation member control circuit. FIG. 10, FIG. 10 and FIG. 11 are timing charts for explaining the operation of the main part in FIG. 10 IC card (portable medium), 11 Contact part (connection means), 12 Keyboard part (input means), 13
... Display unit (display means), 14 ... Magnetic generating member, 16 ... Terminal (external device), 21 ... Communication control circuit, 23 ... Power control circuit, 25 ... Internal battery, 26 ... Clock control Circuit, 27 Oscillator, 28 CPU (control element), 31 Data memory, 33 Calendar circuit, 34 Oscillator, 38
... Keyboard interface, 40 ... Magnetic generating member control circuit, 67 ... Oscillation circuit, 92-101 ... Counter, 102 ...
... clock (second clock means), 103 ... clock (first clock means).

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-20184 (JP, A) JP-A-61-133472 (JP, A) JP-A-60-196874 (JP, A) JP-A 55-2018 57179 (JP, A) Shokai 60-164262 (JP, U)

Claims (1)

(57) [Claims] Claims: 1. An IC card capable of conducting a transaction within a predetermined expiration date, wherein a transaction limit amount representing an expiration date in which the IC card can be used for transaction and an upper limit of an amount transactable within the expiration date. Storage means for storing time data; first clock means for counting time data by counting a reference signal; display means for displaying the time data counted by the first clock means when no transaction is performed; Input means for externally inputting a change in the time data by the first clock means displayed on the display means and for inputting a transaction amount at the time of a transaction; A second clock means that counts the time data of the second and cannot input a change content by the input means; an expiration date stored in the storage means; First determining means for comparing whether the expiration date of the IC card has expired by comparing the time data of the second clock means which cannot be changed, and expiration date by the first determining means; First processing means for storing information indicating that the expiration date has passed in the storage means when the determination is made, and displaying information indicating that the expiration date has passed when the transaction is performed, When the first determination means determines that the expiration date has not expired, the transaction can be performed by comparing the transaction amount input by the input means with the transaction limit stored in the storage means when conducting the transaction. A second determining means for determining whether or not the transaction can be performed by the second determining means; the transaction is performed in the storage means using the time data by the second clock means; Time data and the above IC card characterized by comprising second processing means for displaying the information indicating that updating the transaction limit with and stores and forehead to allow the transaction on the display means.