JPS6359285B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic programmable counter with low power consumption and high operating speed for use in counters, digital synthesizers, etc.

A conventional programmable counter has a configuration shown in FIG. 1, consisting of a counter element having a counter function and a function of initializing to an arbitrary state, where 1 is an input signal terminal, and 2 is an input signal terminal.
are output signal terminals, 3-1, 3-2,..., 3-n are initial setting input terminals, 4-1, 4-2,..., 4-n
is a counter element, and 5 is a NAND gate that takes NAND logic of each output of counter elements 4-1 to 4-n. FIG. 1 shows the configuration when the operation mode of the counter element is defined as follows. Note that although the configuration changes depending on the mode of operation of each counter element, the essential operation is the same. In each counter element in the figure, when the R input is "0", an initial setting operation is performed, and when the R input is "1", a counter operation is performed. If the initial setting P input is “1”, the Q output will be “0” and the output will be “1” at the initial setting, and if the P input is “0”, the Q output will be “1” and the Q output will be “1”. becomes “0”. It is assumed that the counter operation, that is, the change in state, is performed when the input signal applied from the input terminal 1 to the T input transitions from "1" to "0".

In Figure 1, when an input pulse is applied to input terminal 1, focusing on the output, the output of counter element 4-1 closest to input terminal 1 is set as the LSB (least significant bit), and the input pulse is sequentially arranged in ascending order of digits. are added and counted. When the outputs of all the counter elements 4-1 to 4-n become "1", the output of the NAND gate 5 is inverted from "1" to "0", and this is applied to the R input of each element 4-1 to 4-n. Since each element is added to the initial setting state, the counter is initialized in accordance with the initial setting input. Usually, counter element 4-1
There is one or more inputs that initialize the output of ~4-n to "0", so in response to that, NAND gate 5
becomes "1" again, so that the R inputs of all counter elements 4-1 to 4-n become "1" again, all counter elements shift to counter operation, and start addition counting again. Therefore, in the counter circuit of FIG. 1, the number of input pulses from the end of the initial setting until the initial setting starts again can be arbitrarily specified by the initial setting input, so this counter circuit can perform any counter operation. It can be carried out.

This series of programmable counter operations can be divided into two modes of operation. One is for all counter elements 4-1 after initial settings are made.
This is a counter operation that continues until 4-n becomes "1", and the other is an initial setting operation that is performed only when all counter elements become "1". For counter operation, the input pulse is 2
Since the numbers are counted in digits, as the number of counter stages increases, each counter element 4-1 to 4-4
The period of the -n input pulse becomes twice as long. Therefore, each counter element 4-1 to 4-
This means that the counter operation speed of n may become twice as slow as the number of counter stages increases. Next, considering the initial setting operation, the initial setting operation designation signal (i.e. R input) of each counter element 4-1 to 4-n is obtained from the NAND gate 5, and is applied to all counter elements simultaneously. There is. Here, if there is even one counter element whose initial setting is completed, the initial setting signal will disappear, so the initial setting operation of all counter elements 4-1 to 4-n must be performed at the same speed. . That is, while the counting operation speed may be slowed down by a factor of two as the counter stages progress, the instantaneous initialization operation must be performed for all counter elements within the same time period.

Normally, it is impossible to arbitrarily make the initial setting operation faster than the counter operation speed for each counter element, and since the speeds are about the same, all counter elements operate with the same speed performance and the same power consumption. I have to let it happen. In other words, the conventional method had a drawback of high power consumption loss. In addition, in the initial setting operation, the first stage counter element 4-1 is set to "1" by the transition of the input pulse from "1" to "0" while the outputs of all counter elements from the second stage onwards are "1". The initial setting time is T ₁ , the counting operation time of the first stage is T ₂ , the delay time of the NAND gate 5 is T ₃ , and the R input is input to each counter element. If the time it takes for the state to reverse is T ₄ , then T ₁ = T ₂ + 2T ₃ + T ₄ . From this, it can be seen that the minimum period of the input pulse is determined by the initial setting time _T1 . That is,
The minimum period of the input pulse is T ₁ . Therefore, the speed performance of the NAND gate 5 is a factor that determines the minimum period of the input pulse, and as the number of counter elements increases, the fan-out of the NAND gate 5 increases, and the speed performance of the NAND gate 5 deteriorates. In the end, this had the disadvantage of lowering the maximum count frequency. The present invention aims to eliminate these drawbacks, and provides a configuration in which the initial setting operating speed of the counter element of interest can be freely made to correspond to the counter operating speed according to the period of the input pulse applied to the element of interest. This makes it possible to reduce the power consumption of the counter element compared to the previous stage according to the period of the input pulse of that stage. Further, according to the present invention, it is possible to separate the initial setting operation designation signal of each counter element, suppressing a decrease in the maximum counting frequency due to an increase in the number of fan-outs accompanying an increase in the number of counter elements, and making it possible to It is possible to increase the speed of the counter.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

First, the ideal operation of the programmable counter at initial setting will be described. Generally, in the above-mentioned type of programmable counter, there are two types of initial setting operations for each counter element: a case in which the state changes before and after the initial setting operation, and a case in which the state does not change. 2A to 2J illustrate these two types of operation modes using signal waveforms of the circuit of FIG. 1. When the state changes, there is an initial setting input of "0" as shown in Figures 2A to 2E, and the output of the counter element of interest changes as shown in Figure 2A, as shown in Figure 2B. The input pulse 3 changes to "1", the R input becomes "0", starts the initial setting operation, and becomes "0" again.
Changes to The first stage counter element becomes 1 again by the next input pulse 1. The initial setting of the counter element in the next stage only needs to be performed before the transition from "1" to "0" occurs in the counter element stage of interest, so it should be completed by time t _d shown in Figure 2B. Bye. Therefore, the time width allowed for the initial setting of the next-stage counter element is the width T _B shown in FIG. 2B, which is twice the time width T _A allowed for the previous stage, that is, the counter element of interest.

In addition, if the state does not change, there is a "1" initial setting input shown in FIG. 2 F to J. In this case, the state does not change during the initial setting operation, so this initial setting operation is unnecessary. It is only necessary to have a counting function as shown in FIG. 2G. However, the transition from "1" to "0" due to the initial setting in the previous stage must not be counted. For example, the signal in FIG. 2 for a 1→0 change between the dashed lines in FIG. 2H, as shown in FIG. 2I, is not counted. If you do this,
Since the counter element with P = "1" has a period of essentially 1/2, the initial setting operation of the next stage counter element starts one cycle before the input pulse to the counter element of the stage of interest. Therefore, the time width allowed for initial setting becomes the time width T _C shown in FIG. 2G. In this case, the time width T _C is also twice the time width T _A allowed in the previous stage. Therefore, when the state does not change, if the counter element of interest performs a 1/2 frequency division operation that prohibits the counting of operations according to the initial setting in the previous stage, the initial setting operation time can be changed according to the input pulse period. Even if you change it, it will still work fine.

Furthermore, to summarize the above content, if the state changes depending on the initial setting, that is, if P = 0,
In principle, the initial setting time of the subsequent stage, that is, the relevant counter element, is allowed to be twice as long as that of the preceding stage counter element, similar to the counting operation time.
Therefore, if the initial setting signal, that is, the R signal, is maintained until the initial setting of the relevant counter element is completed, and the initial setting operation speed is configured to automatically follow the counting operation speed, the subsequent stage, that is, the relevant counter element. Normal operation can be obtained at a lower speed than the previous stage. Further, if the state does not change due to the initial setting, that is, if P=1, the state does not change and only the counting operation is always performed. Therefore, by configuring the counter element to perform constant counting operation, normal operation can be obtained by setting the counter element at a lower speed than the previous stage. However, regardless of whether the relevant counter element is P=0 or P=1, if the state of the preceding stage counter element changes due to the initial settings, if the relevant counter element counts the change in state, normal operation will not occur. Therefore, during the initial setting operation, the counter element sends a count prohibition signal indicating that the initial setting operation is in progress to the next stage counter element, and the next stage counter element receives the count prohibit signal. It is necessary to configure the system so that counting operations are prohibited during the operation.

Next, the configuration of the counter element circuit of the programmable counter of the present invention is shown in FIG. 3A, and the equivalent circuit when the initial setting input is "0" is shown in FIG. 3B.
FIG. 3C shows an equivalent circuit when the initial setting input is "1". In FIG. 3A, reference numeral 11
1 is an input signal terminal, 12 is an output signal terminal, 13 is an initial setting input terminal, 14 is a counter element similar to the counter element 4 shown in FIG.
5, 16 and 17 are NAND gates; 18 is a reset flip-flop; 19 is an output terminal of NAND gate 16 for forming an initial setting designation signal;
20 is a set input terminal of the reset flip-flop 18; 21 is a count inhibit signal input terminal for the initial setting operation of the previous stage consisting of the previous stage R input signal;
2 is a count inhibit signal output terminal for sending the R input signal in the counter element circuit to the count inhibit signal input terminal 21 of the next stage.

The timing waveforms of each part when the P input to the initial setting input terminal 13 is "0" are shown in FIG. 3-1.
In this case, since P=“0”, the output of the NAND gate 17 is always “1”, and the NAND gate 15 is a simple inverter.
If the initial setting operation of the counter element circuit 6 is set sufficiently later than the initial setting operation of the counter element circuit in the preceding stage, a simple inverter can be obtained, so that the equivalent circuit shown in FIG. 3B is obtained. Therefore, when a set signal is input to the set input terminal 20 of the reset flip-flop 18, the R input of the counter element 14 becomes "0", and this counter element circuit enters the initial setting operation state, and the output of the counter element 14 becomes "0". is set to "0" in response to P="0" input, and the change to "0" is completed. Therefore, only after the initial setting of the counter element 14 is completely completed, the output of the gate 16 becomes "0", the reset flip-flop 18 is reset, and the counter operation is started.
At this time, since the operation of each counter element 14 becomes slower as it goes to the later stages,
The reset of 8 becomes slower as the stage progresses. Therefore, the initial setting operating speed automatically follows the counting operating speed.

P input to initial setting input terminal 13 is P="1"
Fig. 3-2 shows the timing waveforms of each part when . When the counter element circuit in the previous stage is operating in the counting mode, the A input of the terminal 21 is "1", so in the counter element circuit 14 in the stage of interest, P="1" and NAND
Since the output of the gate 17 becomes "0", the R input of the counter element 14 becomes "1" and operates in counting mode. Also, the output of the output terminal 19 is also
As shown in Figure 2 G, it becomes “1” and appears to be 1/2.
Operates as a frequency divider. That is, the operation of each counter element 14 becomes slower toward the later stage.
When the previous stage counter element circuit is in the initial setting special operation state, the A input becomes “0”,
The output of NAND gate 17 becomes “1”,
Since the output of the NAND gate 16 is "1", the reset flip-flop 18 is in the set state, and since the output is "1", the R input of the counter element circuit 14 is "0", and the initial setting mode is set. becomes. Therefore, since the counting mode is not entered while the A input is "0", counting of changes in state at the initial setting of the previous stage is prevented. Therefore, P
The equivalent circuit for the circuit of FIG. 3A in the case of ="1" is as shown in FIG. 3C.

Therefore, when the state does not change due to the initial setting, that is, when P=1, the constant counting operation is performed, ignoring the change in the state due to the previous initial setting operation.

Next, FIG. 4 shows an embodiment of the programmable counter of the present invention, which is constructed by cascading n counter element circuits shown in FIG. 3A and is capable of counting from 1 to 2 ⁿ . Here, the same parts as in FIG. 3A are given the same reference numerals, and subscripts 1 to n are given depending on the position of each stage of the counter element circuit. The input signal terminal 11-1 of the first stage counter element circuit is used as the input signal terminal of the programmable counter, and the NAND gate output terminals 19-1 to 19
-n is connected to the input terminal of the NAND gate 31, and the output of this NAND gate 31 is guided to the output signal terminal 32. Here, in the reset flip-flops 18-1 to 18-n, when S="0", Q="1", and when R="0", Q="0" is operated. shall be taken as a thing.

This operation will be explained below, but if the operations of the first and second stages are shown, the operations of the subsequent stages can be considered in the same way, so the operation when all the initial setting inputs up to the nth stage to the third stage are "1" think of. In this case, there are four combinations of initial setting inputs for the first stage and second stage, and the operating waveforms for all of them are shown in Figures 5A to 5A.
K, Figures 6A-K, Figures 7A-K and Figure 8A
- Shown in K. In Fig. 5 A to K, P ₁ = “0”, P ₂ =
“0”, FIG. 6 A to K are P ₁ = “1”, P ₂ = “0”, FIG. 7 A to K are P ₁ = “0”, P ₂ = “1”, and
Figures A to K show the cases where P ₁ = "1" and P ₂ = "1", respectively. In each of Figures 5 to 8, A is 1
1-1 IN input, B is 18-1 Q output, C is 13-1 P ₁ input, D is 17-1 output, E is 14-1 R input (A' output), F is 14-1 Q
Output, G is the output of 19-1 (R input of 18-1), H is the output of 14-1, I is the output of 14-2, J is the output of 19-2 (R input of 18-2) ,
K is the OUT output of 31 (S of 18-1, 18-2)
input). Here, P ₁ and P ₂ indicate initial setting inputs for the first stage and second stage.

In the cases shown in Figure 5 A to K, each element initially operates as a counter, and ₁ (first stage output) = "0",
Q ₂ (2nd stage output, in the same way, corresponding numbers will be added as subscripts up to n stages) = “0”, ₃ ~
Initial setting is n=“1”. Terminal 11-1
Since each element is sequentially inverted as the input transitions from "1" to "0", three input pulses result in ₁ = ₂ =...n = "1", which is passed through the NAND gate 31 to the first stage and second stage. Row set reset flip-flops 18-1 and 18-2
is set, and the first and second stage counter element circuits enter the initial setting operating state. The transition to the third stage is always a counter operation due to the initial setting input "1". When the initial setting operations in each of the first and second stages are completed, the reset flip-flop is reset and the counter operates.
Therefore, a count of "3" is performed. The arrows in the figure indicate the time range within which initial settings are allowed. Furthermore, the fifth
The reason why the first rising pulse in Figure H is located approximately midway between the falling edge of the first pulse and the rising edge of the second pulse in Figure 5A is due to the response delay due to the counting operation time _T2 of the first stage counter element ( This is due to delays.

The OUT output of NAND gate 31 in Figure 5 K is 1
→When the value is 0, the preset operation starts. In FIG. 4, all the flip-flops 1
8-n is set. Each flip-flop 18
- When the Q of -n changes from 0 to 1 and from 1 to 0 (corresponding to the timing in Figure 5B), each NAND gate 15-
The output of n changes from 1 to 0 and is input to the R terminal of each counter element 14-n. At this time, P=
The initial setting operation starts with a counter element of 0, and the initial setting mode is entered. The operation of the counter element 14-n in FIG. 4 becomes slower as the counter element in the later stage is set, and in the first counter element 14-1, the initial value is set within T _A of H in FIG. -2～
In n, the later the stage, the longer the time goes from 1 to 0.
The initial value is set. Next, the output of each NAND gate 16-n changes from 1 to 0 at a later stage, and outputs an initial setting mode end signal. This termination signal is input to the R terminal of each flip-flop 18-n, and further input to each NAND gate 15-n. As a result, the input to the R terminal of each counter element 14-n changes from 0 to
1, and the initial setting mode automatically shifts to the counting mode. Counter element 14-2
The R input of is shown in FIG. 5L. Figure 5 I, 14-2
The change from 1 to 0 in the output of , that is, the initial value is T _B
Figure 5 L after the initial value is set.
R input, that is, automatic transition to count mode is performed. In this way, the initial value setting and transition to the counter mode of the next stage counter element is slower than that of the first stage counter element. Furthermore, since the output of each counter element becomes the T input of the counter element in the next stage, the setting of the initial value and the transition to the count mode in the third and subsequent stages are slower than in the counter element in the previous stage.
Then, at t ₄ in FIG. 5H, the counter element 14
-1 starts counting, and each counter element starts counting after transitioning to counting mode.

In the case of FIGS. 6A to 6K, since the first stage always performs a counter operation with the initial setting input "1", a signal obtained by counting down the input signal by half is input to the second stage. Therefore, the operation is the same as that of the first stage when P ₁ = "0" and P ₂ = "0". In the figure, the time width allowed for the initial setting is indicated by an arrow, and the cases in FIGS. 5A to 5K are the same for both the first stage and the second stage. Here, the count number is "2". In the case of FIGS. 7A to 7K, the operations are clear from the previous explanation, so the explanation thereof will be omitted. The count number is "1". 2
The stages are always in counter operation, so
₂ state continues the counter operation as shown in the figure without any effect on the initialization input.

In the cases shown in FIGS. 8A to 8K, all the counter elements operate as a counting operation, that is, as a binary counter, although this is actually meaningless. Since all outputs are "1", the output OUT always remains "0". As described above, in the programmable counter of the present invention, when the state changes due to the initial settings, the initial setting operation speed of the counter element automatically follows the counting operation speed, or when the state does not change due to the initial settings. performs a constant counting operation, and in any of these cases, by operating so as not to count the change in state due to the initial setting of the previous stage, the time width for initial setting is set according to the number of stages of the counter element. It can be approximately doubled.

FIG. 9 shows an embodiment of the programmable counter of the present invention in a case where the main focus is on high speed. Setting input terminal, 4
4-1 to 44-n are counter elements, 45
~53 is a NAND gate. Here, terminal 43
A P ₁ input of -1 is supplied via NAND gate 47 to NAND gates 45 and 48 . The Q output of the first stage counter element 44-1 is also supplied to the NAND gate 48, and the NAND output is supplied to the NAND gate 5.
Add to 1. The respective outputs of the second to nth counter elements 44-2 to 44-n are added to the NAND gate 49, and the NAND output is applied to the NAND gate 50.
Add to NAND gate 51 via. The output of the NAND gate 51 is taken out from the output signal terminal 42.
Furthermore, the output of the NAND gate 51 is transferred to the NAND gate 4.
6 to the other input terminal of the NAND gate 45 mentioned above. The NAND output of this NAND gate 45 is connected to the R of the first stage counter element 44-1.
Use as input. Furthermore, Nand gates 50 and 53
The outputs of NAND gates 51 and 52 are applied to NAND gate 53. The output of the NAND gate 52 is used as the R input of each counter element 44-2 to 44-n.

An operation timing diagram of this embodiment is shown in FIG. 9-1. This figure A shows the case where the initial setting input _P1 of the first stage is "0", and this figure B shows the case where it is "1". The case of A in this figure will be explained. For convenience of explanation, 2nd and 3rd row
The initial setting inputs of the counter element circuits in the second stage are "0" and "1", respectively. As the counting operation progresses, the output of the inverter 50 changes from "0" to "1" when all of the second and subsequent stages become "1".
Furthermore, when an input pulse enters the terminal 51 and all the counter element circuits including the first stage become "1", the output of the NAND gate 47 is always 1.
The output of the NAND gate 51 changes from "1" to "0", the output of the NAND gate 45 becomes "0", and the first stage counter element circuit enters the initial setting operation mode. At the same time, the output of the reset flip-flop constituted by NAND gates 52 and 53 changes from "1" to "0", and the counter element circuits in the second and subsequent stages also enter the initial setting operation mode.

The output of the first stage that has entered the initial setting operation is initialized to "0", and in response to this, the output of the NAND gate 51 becomes "1" again, and the first stage counter element shifts to the counting operation mode. This series of initial setting operations at the first stage is designed to be completed within the TA time shown in FIG. 9-1, that is, within the period of the input pulse.

The second and subsequent stages only need to be completed within the time Tc in the figure, so the output of the NAND gate 51 is “1”.
Therefore, even if the initial setting operation signal of the first stage disappears, the initial setting signals of the second and subsequent stages are transmitted to NAND gates 52 and 5.
The reset flip-flop is maintained by a reset flip-flop consisting of 3. When the initial setting of the second stage counter element circuit is completed, the output of the NAND gate 50 becomes "0", and the output of the reset flip-flop becomes "1", and the second stage and subsequent stage counter element initial setting mode is started. After that, go to counting mode. Therefore, it is possible to lower the speed of the second and subsequent stages.

In the case of Figure 9-1B, the P input of the first stage is 1, so the output of the inverter 47 is always "0", NAND
Since the outputs of gates 48 and 45 are always "1", the first stage always performs only a counting operation. As shown in the timing diagram, the second and subsequent stages all become "1" one clock before, and the output of the reset flip-flop,
That is, the initial setting mode designation signal becomes "0" one clock before, the initial setting operation is started, and the initial setting operation is completed within the time Tc as shown in the figure.

Therefore, similarly to FIG. 9-1A, it is possible to reduce the speed of the second and subsequent stages.

Here, by taking advantage of the fact that the initial setting operation speed of the counter element of interest can be delayed compared to the previous stage, the initial setting operation designation signal of the first stage has a minimum delay without being affected by the parasitic capacitance of the fan-in and wiring. Let them join. In this example, 2
The structure after the first stage is the same as that of the conventional one, and this is because the increase in the number of elements when forming the counter element is suppressed as much as possible.

In Figure 10, the fan-out effect is noticeable, and
An example will be shown in which a programmable counter of the present invention is constructed using an I ² L (Integrated Injection Logic) gate, which has the characteristic that an increase in the number of elements does not significantly increase the chip area as an IC (Integrated Circuit). Here, the multi-input I ² L gate has the circuit configuration shown in FIG. 11A, and its logic symbol is expressed as shown in FIG. 11B.

In FIG. 10, 51 is an input terminal, 52 is an output terminal, and 53-1 to 53-n are ₁ to 53-n, respectively.
Initial setting input terminals to which input is supplied, 54-1~
54-n is a counter element, 55-60 are NAND gates, and 61-77 are the above-mentioned ^I2L gates. Here, ₁ to inputs are respectively applied to the ^I2L gates 63, 67, 71, etc., _P1 to Pn signals are taken out, and each counter element 54-1 to 54-
It is supplied to each P input terminal of n, and also to I ² L gates 62, 66, 70, etc. corresponding to NAND gates 17-1 to 17-n shown in FIG. The I ² L gates 61, 64, etc. and the NAND gate 58 correspond to the NAND gates 51-1 to 15-n shown in the fourth figure,
The NAND gate 56, I ² L gates 68, 72, etc. correspond to the NAND gates 16-1 to 16-n shown in the fourth figure. Further, NAND gate 57 and I ² L gate 65 correspond to flip-flop 18-2 in FIG. 4, and NAND gate 59 and I ² L gate 69 correspond to flip-flop 18-2 in FIG. It corresponds to flip-flop 18-n.
The I ² L gate 73 supplies the first collector output of the I ² L gate 73 corresponding to the NAND gate 31 shown in the fourth figure to the I ² L gate 61 via the NAND gate 55, and also supplies the second collector output to the output terminal 52, the third collector output is sent to each counter element 54-2 to 54-n via multi-stage connected I ² L gates 74 to 77, etc., and further to a NAND gate 60, etc.
It is added to the R input of the corresponding counter element from the I ² L gates 65, 69, etc. This configuration uses an I ² L gate, so the gate configuration is slightly different, but it is logically equivalent to the embodiment shown in Figure 4, so the operation timing diagrams are the same as those in Figures 5 to 8. Omitted. Normally, in an I ² L gate, the fanout number is determined by the number of collectors and is not large, about 3 to 5, so I ² L gates are connected in multiple stages to obtain a large fanout. Furthermore, speed dependence on the number of collectors is extremely significant, and as the number of collectors is increased, speed performance deteriorates. Therefore, if an attempt is made to increase the fan-out, the speed will deteriorate significantly. Therefore, in the programmable counter of the present invention shown in FIG.
The configuration is such that the R inputs are sequentially supplied to the counter elements that are closest to each other in the process of increasing the fan-out of the initial setting designated signal, starting with the one with the least delay among the appropriately extracted signals, thereby maximizing the reduction of deterioration due to fan-out. There is.

As explained above, the present invention has a configuration that allows the time width for initial setting to be approximately twice that of the previous stage, so normally, the counting operation speed and the initial setting operation speed are the same depending on the power consumption. Therefore, in the examples shown in FIGS. 5A to 8K to FIGS. 8A to 8K, if there is no increase in speed or power due to the added functions, the power consumption can be reduced to half that of the previous stage. Therefore, if the power of the first stage is set to 1. From the second stage onward, 1/2, 1/
4, 1/8, . . . 1/2 ⁿ , so any number of stages can be operated with less power than the power of two conventional counter elements. Even in an actual case, for example, if we consider a configuration consisting of 10 stages of elements, in the conventional counter, if the power consumption of one element is 1, then the power consumption is 10, whereas in the programmable counter of the present invention, the power consumption is 10 times. Even if the power of the element is doubled due to the function, the total is 2 + 1 + 1/2 + 1/4 + 1/8 + 1/16 + 1/32 + 1/6
The value is 4+1/128+1/256, which is smaller than 4.
Thus, the present invention has the advantage that significantly lower power consumption is achieved without degrading speed performance. In addition, in the example shown in Figure 9, the initial setting designation signal is separated, so that even if the number of counter elements increases, the effects of an increase in fan-out and an increase in wiring capacity are eliminated, and the maximum count frequency is reduced. Therefore, when there are a large number of counter elements, there is an advantage over the conventional method that the speed can be increased without increasing power consumption or increasing the number of elements. In addition,
The present invention also has the advantage that it can be configured freely while balancing the increase in the number of elements and the degree of improvement in power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional programmable counter, and FIGS. 2A to 2J are diagrams showing the circuit diagram of FIG. FIG. 3A is a logic circuit diagram of the counter element circuit in the programmable counter of the present invention, and FIGS. 3B and C are signal waveform diagrams showing signal waveforms when the initial setting input P is "0" and "1". Each equivalent circuit diagram, Figures 3-1 A to J is a signal waveform diagram of the circuit in Figure 3 A when its initial setting input P is "0", and Figures 3-2 A to J are its initial setting inputs. A signal waveform diagram of the circuit of FIG. 3A when P is "1", FIG. 4 is a logic circuit diagram showing one embodiment of the programmable counter of the present invention, FIGS. 5A-L, and FIGS. 6A-
K, FIGS. 7 A to K and FIGS. 8 A to K show four combinations of the input pulse, first stage counter element, second stage counter element, and output operation waveforms of the programmable counter of the present invention, respectively, with initial setting inputs. FIG. 9 is a logic circuit diagram showing an embodiment of the present invention when the main focus is on high speed, and FIGS. 9-1 A and B.
9 is a signal waveform diagram showing the operation timing of the circuit in FIG. 9, FIG. 10 is a logic circuit diagram showing an embodiment of the present invention using an I ² L gate that focuses on high speed, and FIG.
Figure A is the circuit diagram of the I ² L gate and Figure 11B is the I ² L gate circuit diagram.
FIG. 3 is a diagram showing logic symbols of gates. 1...Input signal terminal, 2...Output signal terminal, 3
-1~3-n...Initial setting input terminal, 4-1~4
-n... Counter element, 5... NAND gate, 11, 11-1, 41, 51... Input signal terminal, 12, 32, 42, 52... Output signal terminal,
13,13-1~13-n,43-1~43-
n, 53-1 to 53-n...Initial setting input terminal,
14, 14-1 to 14-n, 44-1 to 44-
n, 54-1 to 54-n... Counter element, 15, 16, 17, 15-1 to 15-n, 1
6-1 to 16-n, 17-1 to 17-n, 31,
45-53, 55-60...Nand Gate, 1
8, 18-1 to 18-n... Set reset flip-flop, 19, 19-1 to 19-n... Output terminal, 20... Set input terminal, 21... Counting inhibit signal input terminal, 22... ...Counting prohibition signal output terminal, 61-77... ^I2L gate.

Claims (1)

[Claims] 1 Connect multiple counter elements in cascade,
When the output of all counter elements reaches the final value, the initial setting control signal for dividing or counting operation is sent to the plurality of counter elements, and the initial setting operation and counting operation are mutually automatic. In a monolithic programmable counter configured to enable arbitrary frequency division or counting operations, at least one of the counter elements changes to the initial value of the counter element at the time when an initial setting control signal is sent. The counter element has a configuration that determines whether initial setting is necessary based on the input and the output of the counter element, and if initial setting is not necessary, the counting operation is continued. If necessary, it generates a signal to perform the initial setting operation, performs the initial setting operation, and sends a signal to the next stage counter element to perform the initial setting operation, so that the next stage counter element The configuration is such that output changes of the previous stage counter element involved in the initial setting operation of the previous stage are not counted, and the operating speed of the next stage counter element during the counting operation and the initial setting operation is higher than that of the counter element. However, it is a programmable counter that is characterized by low speed.