JPH03262210A - Variable frequency division system - Google Patents

Abstract

PURPOSE:To set a frequency division ratio of a small circuit scale optionally by using a delay signal outputted from a binary element to frequency-divide an oscillation oscillating frequency. CONSTITUTION:A pre-stage Q output terminal is connected to a D input terminal of a next stage, a clock pulse is inputted only to a 2nd stage D flip-flop 2 via an inverter 6, and inputted directly to each clock terminal of other D flip- flops 1,3-5. The output of the other D flip-flops 1,3-5 is inputted to a selector 7, the output terminal of the selector 7 is connected to the D terminal of a 1st stage flip-flop 1 via an inverter 8 to form a loop. The each Q output of 1st stage and 2nd stage D flip-flops 1, 2 is outputted via an exclusive OR circuit 9 to obtain a frequency division output. Since a 1st clock pulse after release of reset is outputted even when any frequency is selected, no spike is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a variable frequency division method that allows a frequency division ratio to be arbitrarily set with a small-scale circuit configuration.

[Conventional technology]

Conventionally, as a frequency dividing circuit, for example, as shown in FIG.
A device constructed using a D-flip-flop in a toggle state is known. That is, in FIG. 5, 101.
Reference numerals 102 and 103 designate cascade-connected D flip-flops, each of which has a Q output terminal and a D input terminal connected directly, and a negative output terminal of the previous stage and a clock terminal of the next stage. The configuration is such that the output of each Q output terminal is taken out as the output of the frequency dividing circuit via the selector 104.

The D-flip-flop in the frequency divider circuit configured in this manner inverts its output state every time a clock pulse CLK is applied, and operates as a binary counter. Therefore, by connecting a plurality of these in series, an asynchronous binary coded binary counter (ripple counter) is formed, and by selectively outputting each output J signal with the selector 104, a 2n frequency divided output signal is generated. is obtained.

Furthermore, as a conventional frequency dividing circuit, one using a combination of a counter and a decoder as shown in FIG. 6 is known. That is, in FIG. 6, 201 is a counter, and each output terminal is connected to a decoder 202-1, 202-2, respectively.
．． ...202-4 are connected, and the output terminals of each decoder are connected to the J and input terminals of flip-flops 203 and 204, respectively, and the Q outputs of JK flip-flops 203 and 204 are connected. is configured to be selectively taken out as a frequency-divided output via the selector 205.

In the frequency divider circuit configured in this way, the decoder 2
02-1. . . . By setting 202-4, the duty ratio of the frequency-divided output can be changed freely.

[Problems to be Solved by the Invention] However, in the frequency dividing circuit constructed by cascading D-flip-flops shown in FIG. 5, the duty ratio cannot be changed and the frequency can only be divided by 21. On the other hand, the frequency divider circuit shown in Fig. 6 has the following drawbacks:
When constructing a variable frequency divider circuit, there is a drawback that the circuit scale increases.

For example, when performing multi-playback in which the TV screen is divided into several sub-screens, TV in TV format, or zoom playback in which a part of the screen is enlarged, there is a need to vary the size of the sub-screens or zoom. There is. In such a case, if you try to use the frequency dividing circuit shown in FIG. 5, the variation will be too large and it will be difficult to use.
If the frequency dividing circuit shown in the figure is used, the scale of the circuit will become too large and the cost will increase.

In addition, in both frequency divider circuits, there is a difference in delay between the signals selected by the selector due to variations in the selector, D-flip-flop, or J-flip-flop. If the difference is significant and signals are required at exactly the same timing, it is necessary to insert a flip-flop after the selector to match the timing. However, even if a flip-flop is inserted after the selector in this way, there is a problem in that these frequency dividing circuits cannot output the frequency-divided signal and the original oscillation signal at exactly the same timing. Furthermore, both frequency divider circuits have the problem that spikes may occur when the selector selects and outputs the divided signal.

The present invention was made in order to solve the above-mentioned problems in conventional frequency divider circuits.The present invention is a variable frequency divider that can output the original oscillation signal and the divided output at the same timing with a smaller circuit scale. The purpose is to provide a method.

[Means and operations for solving the problem] In order to solve the above problems, the present invention uses a shift register configured by combining binary elements, forms a loop in the shift register, and stores each binary value. The original oscillation frequency is divided using the delayed signal output from the element.

By obtaining a frequency-divided signal in this way, a frequency-divided signal that is arbitrarily variable from the original oscillation frequency to its N-divided frequency can be obtained with a relatively small circuit scale, and the phase and duty ratio can be arbitrarily set. becomes possible. Furthermore, even if multistage is used, since it is a shift register operation, high-speed operation is possible, and the delay time of the output signal can be taken out at a constant rate regardless of the frequency division ratio. Furthermore, since no spikes occur, the frequency-divided output signal can be used as it is as a clock.

[Example] Next, an example will be described. FIG. 1 is a block diagram showing a first embodiment of the variable frequency division method according to the present invention. In this embodiment, the pulse width of the "H" level is fixed, and the frequency can be divided from the original oscillation signal by thinning out the pulses of the number of stages of D-flip-flops. In the figure, 1 to 5 are D flip-flops connected in series to form a shift register, and the Q output terminal of the previous stage is connected to the D flip-flop of the next stage.
The other D-flip-flops 1, 3.4.5 are
is input directly to the clock pin. The Q outputs of the D-flip-flops 1 to 5 in each stage are input to a selector 7, and the output terminal of the selector 7 is connected to the D input terminal of the D-flip-flop 1 in the first stage via an inverter 8 to form a loop. is forming. Then, each Q output of the first and second stage D flip-flops 1 and 2 is connected to an exclusive OR circuit 9.
The configuration is such that the frequency-divided output is obtained.

Next, the operation of the variable frequency division system configured as described above will be explained with reference to the timing chart shown in FIG. First, selector 7 (1
) is set. The reset signal R3T becomes “H” level, and the clock pulse C
When LK is applied, the Q output of the first stage D-flip-flop 1 becomes "H" because the output "L" level of the selector 7 is inverted by the inverter 8 and input to the D input terminal.
” level. As a result, the input (1) of the selector 7 becomes the “Ho” level, and therefore its output also becomes the “H” level, which is inverted by the inverter 8 and the D input of the first stage D-flip-flop 1 becomes the “Ho” level. It is input back to the terminal. At this time, the output of the exclusive OR circuit 9 is °“
It becomes H” level.

Next, when the clock pulse CLK falls, the Q output of the second stage D-flip-flop 2 becomes "H".

level, and the output of the exclusive OR circuit 9 is “L”.
Return to Rubel. After that, when the clock pulse CLK rises, the Q output of the first stage D-flip-flop 1 becomes “
The output of the exclusive OR circuit 9 becomes the “H” level again, and the selector 7 and inverter 8
to set the D input terminal of the first stage D-flip-flop 1 to "H".

Change to level. In this way, the output of the original oscillation signal itself appears at the output terminal OUT.

Similarly, when the selector 7 is set to (2) to (4) and the output of the selector 7 is changed, the human clock pulses are thinned out one by one and appear at the output terminal OUT. FIG. 2 shows the operation when the selector 7 is selected and set to (4) in addition to the case where the selector 7 is selected and set to (1).

According to this embodiment, no matter which frequency is selected by changing the setting of the selector 7, the first clock pulse after reset release is output, so the phase relationship is the same, which is different from the conventional clock pulse shown in FIGS. 5 and 6. It has the characteristic that it rises faster after reset release than the output signal from the frequency divider circuit, and also does not generate spikes.

FIG. 3 is a block diagram showing a second embodiment of the present invention, in which the same or equivalent members as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals. This embodiment is a variable frequency division method that can output frequency division by 3 and frequency division by 4 with a duty ratio close to 50%. To explain the structural parts that are different from the embodiment shown in FIG. is similarly connected to the D of the first stage D-flip-flop 1 via the inverter 8.
It is designed to be input to the input terminal to form a loop.

Further, the clock pulse CLK is applied to the first, second, . It is directly input to each clock terminal of the D-flip-flops 1, 2, and 4.5 in the fourth and fifth stages, and is input via the inverter 6 to the clock terminal of the D-flip-flop 3 in the third stage. It has become so. Then, the Q outputs of the first and third stage D-flip-flops are input to the exclusive OR circuit 9-1, which outputs a divided clock output with a first duty ratio to the output terminal 0UTI, The Q outputs of the first and fourth stage D-flip-flops are input to the exclusive OR circuit 9-2, and a divided clock output with a second duty ratio is output to the output terminal 0UT2. It is configured.

The operation of the variable frequency division method configured in this way is performed in the same way as the frequency division method of the first embodiment, and when the selector 7 is selected and set to (1), the reset signal R3T reaches the ``H'' level. , when the clock pulse CLK is applied, the Q outputs of the D-flimp flops 1 to 4 in the first to fourth stages appear as shown in the timing chart of FIG. From the terminals 0UTI and 0UT2, divided-by-3 outputs with duty ratios of 1/2 and 2/3, respectively, are obtained as shown.

Furthermore, when the selector 7 is selected and set to (2), the duty ratio is 1.5/1, respectively, as shown in FIG.
4.1/2 divided into 4 outputs are output from each output terminal 0UTI, 0U.
Obtained from T2.

In addition, as a modification of this variable frequency division method, the frequency division output signal can be taken out using an AND circuit or an OR circuit, and the initial value 9 frequency division ratio, duty ratio, etc. can be controlled using the set and reset of D-flip-flops. It is also possible to do so.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, it is possible to provide a variable frequency division method in which the frequency division ratio can be arbitrarily set with a relatively small circuit scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the variable frequency division method according to the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a block diagram showing a second embodiment of the variable frequency division method according to the present invention. FIG. 4 is a block configuration diagram showing an example, FIG. 4 is a timing chart for explaining its operation, and FIGS. 5 and 6 are block configuration diagrams showing a conventional frequency dividing circuit. In the figure, 1 to 5 are D-flip-flops, 6.8 is an inverter, 7 is a selector, and 9 is an exclusive OR circuit.

Claims (1)

[Claims] A shift register configured by combining one-value and two-value elements is used to form a loop in the shift register, and the original oscillation frequency is divided using the delay signal output from each binary element. A variable frequency division method that is characterized by frequency rotation. 2. The variable frequency division method according to claim 1, wherein the frequency division signal is extracted from the delay signal output from each binary element of the shift register using an exclusive OR circuit. 3. The frequency division ratio, initial value, and duty ratio can be set and varied as desired by changing the number of stages of the shift register, initial value setting using preset data, and arrangement position of the exclusive OR circuit. 3. The variable frequency division method according to claim 2.