JPS6358861A - Mos field effect transistor pair - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to one MOS field effect transistor (MO
The present invention relates to a MOS field effect transistor suitable for integrated circuit devices, in which a transistor (SFET) is formed vertically above another transistor of the same type, each sharing a common gate.

[Background of the invention]

In recent years, various three-dimensional integrated circuit devices have been proposed in order to meet the increasing demand for highly integrated circuits. Another MO8 on top of the bulk silicon MO8FET
Attempts to form stacked FET devices include recrystallization steps of polycrystalline silicon layers formed on bulk silicon MO8FETs. Generally, this recrystallization step involves a heat treatment conducted at a temperature in excess of about 950° C. for one hour or more. Such a process is suitable for bulk MOSFET! , which can cause over-diffusion of the P0 region and impair the potential performance of VLSI circuit devices formed in this manner. Additionally, prior art stacked MOSFET structures have considerable undesirable parasitic capacitance due to overlapping gates with respect to source and drain regions; The structure and manufacturing method reduce parasitic cavities caused by overlapping source/drain regions and gates.
It is requested.

[Summary of the invention]

The present invention provides a pair of MOSFETs with a common gate arranged in an integrated circuit device and a method of manufacturing the MOSFET pair. First and second heavily doped regions having either conductivity type are formed and disposed in the semiconductor body of the device and extend inwardly from the planar surface of the body. The first and second regions are spaced apart to define a first channel having a length therebetween. This first. On the planar surface over the second region and the first channel is a silicon oxide layer extending over the second region and the first channel. Heavily doped third and fourth regions of one conductivity type are provided in the silicon layer and extend to the silicon oxide layer. The third and fourth regions are spaced apart to define a second channel therebetween. The second channel has a length substantially equal to or greater than the length of the first channel and is substantially opposite the first channel. A gate is provided between the first and second channels and substantially aligned therewith. the gate is insulated from the semiconductor body and the silicon layer;
It has a length substantially equal to the length of the first channel.

[Detailed explanation]

In the following description, and in FIGS. 1-10, an example is shown using materials and regions of P and N conductivity types. However, what is shown here is only an example and does not limit the idea of the invention. It will be appreciated that devices consisting of opposite P-type and N-type configurations are considered equivalent in all respects to the devices described herein. 1-4, a portion of an integrated circuit device 1o is shown including a semiconductor body 12 of a first conductivity type material, in this example a lightly doped P-type material. and has a flat surface 14.

A relatively thin layer 16 of insulating material, such as silicon oxide, is provided over this planar surface 14, as shown in FIG. A goo (20) of any suitable material, such as metal, metal silicide, or doped silicon, is disposed over this insulating layer 16 and has a length labeled II L L+ in FIG. There is. Another layer 22 of insulating material, such as silicon oxide, is formed over the entire exposed surface of gate 20. The first and second heavily doped regions 26 and 28 provided in the body 121 are the source and drain regions, respectively, of the lower MO8F''ET.

A first channel 30 having a length labeled IIL'' in FIG. 1 is delimited by these first and second regions. In this example, the material is of a highly doped second conductivity type, that is, N+ type.The first and second regions are formed so that the length L of the channel 3o is substantially equal to the length L of the gate 2o. Isolation oxide 32 is formed in a conventional manner to electrically isolate the various components of the integrated circuit. is being used.

The particular materials and processing techniques utilized to obtain the apparatus 1o shown in FIG. You just have to use things wisely. The device 10 shown in FIG. 1 represents the starting material with which the features of the invention are to be combined.

As shown in FIG. 2, an opening 40 is formed in the oxide layer 16 over a portion of the first region 26 to expose the surface 14.

Next, an epitaxial layer 42 of single crystal silicon is grown from this exposed silicon. Such epitaxial layers are described, for example, in Corboy (J.
Lateral epitaxial overgrowth (ELO) fabrication techniques disclosed in U.S. Pat. It can be manufactured using. The ELO process essentially involves repeated two-phase deposition/etch cycles to grow single crystal silicon from the surface of the single crystal exposed within the opening of the coating mask. In this example, layer 42 overlies oxide layer 16 to form the first and second regions 2 of the bottom MO8FET.
6. Grow over 28 active areas and at least slightly overlap with these areas. 7v42 is about 5
Grow to a thickness of 0.00 nanometers. Although excellent quality crystals can be obtained using this process, there is a high density of defects at the interface between two overgrown layers of single crystal silicon. Therefore, care must be taken when locating adjacent openings 40 so that the two portions of overgrowth layer 42 do not meet in the vicinity of gate 20. Layer 42 is then etched in the conventional manner to define its perimeter 43 as shown in FIG.

A photoresist tJ is formed on the epitaxial layer 42, and then a photoresist layer 50 is formed as shown in FIG.
．． Suitable openings 48 are defined in this photoresist layer such that openings 52 remain directly above openings 40 and gates 20, respectively. Device 10 is then subjected to a low energy boron implant to form third and fourth regions 54,56, as shown in FIG. The implant energy level should be selected to prevent boron ions from penetrating into the gate 20 and the first and second regions 26,28. A fifth region 58 having the same conductivity type and doping level as the first region 26 remains in the epitaxial layer 142 directly above the opening 40 as seen in FIGS. 2, 3 and 4. Please note that

This fifth region 58 was formed during the growth of epitaxial layer 42 and automatically assumes the same conductivity type and doping level as its seed or region 26. By covering the fifth region 58 with a layer of photoresist 50 during the ion implantation into the third region 54, the resulting PN junction 60 is formed substantially perpendicular to the surface 14. As a result, the third and fifth
By forming a metal conductor in ohmic contact with both regions 54 and 58, electrical shorting of the PN junction is possible following the above steps. The first and third areas 26.54
This results in submerged electrical contact. Opening 48 is formed such that photoresist layer 52 defines a second channel 80 having a length shown as L2 in FIG.

This length L2 should be substantially equal to or slightly larger than the length L□ of the first channel 30. Further, the second channel 80 is connected to the gate 20 so that the first and second channels 30.80 and the gate are approximately aligned as shown in FIG.
It should be centered at the top.

Silico/Oxide or BPSG (borophosphosilicate glass) (7
) layer 70 is formed over the epitaxial layer 42 and surrounding isolation oxide 32, and the contact dose lower 2 is formed by methods well known in the art. Next, the metal contact part 74.7
6 are formed in ohmic contact with the third and fourth regions, respectively, in a conventional manner. (See Figure 4). Note that in this example, metal contact 74 is positioned to short PN junction 60; contact 74 can optionally be positioned to leave this junction open if this junction is desired. , or if desired, photoresist layer 5
0 can also be omitted so that the PN junction is formed approximately parallel to the surface 14.

Electrical connections to the gate 20 and the first and second regions 26,28 are made by extending these regions and the gate laterally so that contact openings can be provided outside the periphery 43 of the layer 42. You can make it. Techniques for making such electrical connections are well known in the art and will not be specifically described.

A second embodiment 100 of the device IO is shown in FIGS. 5 and 6. Structural details shown with like reference numerals as structural details of device 10 are similar and will not be described further. In this embodiment, the first third region 26.54 is not connected by the fifth region 58. The process of making device 100 is similar to the process of making device 10 except for the following points. As shown in FIG. 5, when defining the perimeter 43 of the layer 42, the portion of the layer 42 immediately above the opening 40 is removed to the surface 14. Next, as in the case of device 10,
forming a photoresist layer on the epitaxial layer 42;
A suitable opening 48 is made in this and a photoresist layer 50.5 is formed.
2 remain directly above the opening 40 and the gate 20, respectively.

However, in this case the layer 5o is slightly larger than the opening 4o and overlaps its entire periphery. The 3.4th region 54.56 is then formed by ion implantation as described above for device IO. After removal of layers 50, 52, silicon oxide or BPSGO layer 70 is deposited on epitaxial layer 4.
2 and surrounding isolation oxide 32. Note that layer 70 fills opening 40, thereby insulating third region 54 from first region 26. Metal contacts 74,76 are formed in the manner described above.

A third embodiment 110 of the apparatus 10 is shown in FIGS.
10. As shown in FIG. Detailed structural parts with reference numerals similar to those of the device 10 (- are similar and will not be described again. Layer 11 of polycrystalline silicon.
2 is formed over the device 110, as shown in FIG. 7, to first form a heavily doped glass layer 114, which can be of any conductivity type, but is P type in this example. spin·
A planarization layer 116 of any suitable material, such as on-glass, is formed over the doped glass layer 114. The major surface of planarization layer 116 is substantially flat. Additionally, the material chosen for planarization layer 116 must have an etch rate that approximates that of doped glass layer 114. layer of polycrystalline silicon 11
The etching rate of layer 112 should be as low as possible.Next, as shown in FIG.
Apply etching. Doped glass layer 114 is etched slightly over-etched, leaving doped glass layer 126 in the lower regions surrounding mesa surface 124.

Additionally, layer 112 is etched in a conventional manner to remove unwanted material and define its periphery 130 as shown in FIG. Similar to the structure of device 10, this layer 112 is on top of oxide layer 16, covering gate 2o and at least lower M
It extends so as to slightly overlap the operating portions of the first and second regions 26 and 28 of the O8FET.

A layer 132 of BP SG or similar reflow glass is formed over the device 110 in a manner well known in the art. The apparatus is then heated for approximately 850° to fluidize layer 132 in the conventional manner. This operation causes impurities to be diffused from the doped glass layer 126 into the layer 112 into third and fourth regions 140, 142 of the same conductivity type as that of the lightly doped layer 114.
is formed. As shown in FIG. 10, the third and fourth areas 1
40.142 are automatically self-aligned to gate 20 and spaced apart to form a second channel 144 of length designated L2. As in device 10, this length L2 in device 110 is equal to the first channel 30.
By this process, the second channel 144 has a length L (approximately equal to or slightly less than the gate 2).
Centered above 0, first and second channels 30.1
44 and the gate are substantially aligned 9H as shown in FIG. Contact openings are formed in layer 132 and metal contacts 74 . are formed in the manner described above with respect to device 10 .
form 76.

Upper MO8FE formed in polycrystalline silicon layer 112
Although T is not made of high quality monocrystalline silicon, it is suitable for many applications such as memory cells in static random access memory devices or CMOS circuits that do not require high gain in P-channel MO8FETs. Useful.

However, if desired, the performance of the device 110 can be improved by recrystallizing the polycrystalline silicon layer 112.

This can be done by any known short time treatment such as a laser recrystallization treatment or a laser heat treatment, provided that the temperature and time of the treatment are such that the highly doped first and second Regions 26 and 28 are the semiconductor body 12
We must avoid over-diffusion into the interior.

Any suitable process known in the art may be utilized to complete the integrated circuit device. This process includes metallization and passivation steps to interconnect the various parts of the integrated circuit.

An important advantage of this invention is that it has a three-dimensional structure (thus, as a pair of MOS F'ETs, one of the MOS
By stacking one FET on top of the other MOSFET,
Conventional single MOS on one integrated circuit chip
What is obtained is that it occupies only the same space as FET. This structure has a gate and a pair of channels that are mutually aligned and of approximately the same length for the two MOSFETs, so that the parasitic capacitance due to source/drain and gate overlap is substantially eliminated. has been reduced to

[Brief explanation of the drawing]

1-4 are cross-sectional views of a portion of an integrated circuit device illustrating the structure and various stages of fabrication of a pair of MOSFETs utilizing the techniques of the present invention; FIGS. Figure 3,
A diagram showing the structure of a second embodiment of the invention similar to FIG. 4,
FIGS. 7-10 are diagrams showing a third example structure of the present invention similar to FIGS. 1-4. 10... Integrated circuit device, 12... Semiconductor body, 14
...Surface, 16...Silicon oxide layer, 20...
gate, 26.28...heavily doped first and second regions, 30...first channel, 42...silicon layer, 54.56...heavily doped first and second regions; 3
and the fourth area, 80...second channel.

Claims (1)

[Claims] (1) in a body of semiconductor material of a first conductivity type having a planar surface and spaced apart extending inwardly from the planar surface to form a first channel of a length therebetween; highly doped first and second regions of either conductivity type disposed on the planar surface above the first and second regions and the channel; a layer of silicon oxide; a silicon layer disposed on the silicon oxide layer above the first and second regions and the channel; and a silicon layer extending into the silicon layer to the silicon oxide layer. any electrical conductivity provided and separated from each other to form a second channel having a length at least equal to the length of the first channel and substantially opposite the first channel; highly doped third and fourth regions having a mold and insulated from the body and the silicon layer and disposed between and substantially aligned with the first and second channels; and a gate having substantially the same length as the first channel. Field effect transistor pair.