JPS6356941A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6356941A JPS6356941A JP61200101A JP20010186A JPS6356941A JP S6356941 A JPS6356941 A JP S6356941A JP 61200101 A JP61200101 A JP 61200101A JP 20010186 A JP20010186 A JP 20010186A JP S6356941 A JPS6356941 A JP S6356941A
- Authority
- JP
- Japan
- Prior art keywords
- barrier metal
- bump
- etching
- gold
- stopper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 83
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 230000004888 barrier function Effects 0.000 claims abstract description 77
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000007747 plating Methods 0.000 abstract description 21
- 239000010931 gold Substances 0.000 abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052737 gold Inorganic materials 0.000 abstract description 12
- 239000000126 substance Substances 0.000 abstract description 8
- 238000009713 electroplating Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【発明の詳細な説明】
〔１既 要〕
バンプ形成後、その外側に位置するバリヤメタルをエツ
チングにより除去する段階で、す１゛ドエツチが起こっ
てハンプ下側のハリＡ・メタルがエツチングされること
を防止するために、バンプ形成前にまたはバンプ形成と
同時に、エツチングのストッパとなる物質をバリヤメタ
ルの所定部分に埋め込むように配置した。[Detailed Description of the Invention] [1] After the bump is formed, at the stage where the barrier metal located on the outside thereof is removed by etching, etching occurs and the firmness A/metal on the lower side of the hump is etched. In order to prevent this, a substance serving as an etching stopper is embedded in a predetermined portion of the barrier metal before or simultaneously with the formation of the bump.
本発明は、半導体装置の！！！造方決方法するものであ
り、さらに詳しく述べるならば、半導体装置の端子電極
として使用されるバンプ（ｂｕｍｐ）の形成に特徴があ
る半導体装置の製造方法に関するものである。The present invention is a semiconductor device! ! ! The present invention relates to a method for manufacturing a semiconductor device, and more specifically, it relates to a method for manufacturing a semiconductor device characterized by the formation of bumps used as terminal electrodes of the semiconductor device.
通常、半導体装置の端子電極はＡｕワイヤの端子電極に
より構成されるが、大きな突起状金属を半導体装置の電
極部に付着させ、該突起状金属にワイヤを接続する電極
構造も採用されている。この電極構造は半導体装置の高
さを低くできるなどの利点がある。突起状金属（ハンプ
と言われる）を形成する方法の従来技術を第２図の（ａ
ｌおよび（ｂｌにより説明する。Generally, terminal electrodes of semiconductor devices are constructed of Au wire terminal electrodes, but an electrode structure has also been adopted in which a large protruding metal is attached to the electrode portion of the semiconductor device and the wire is connected to the protruding metal. This electrode structure has the advantage that the height of the semiconductor device can be reduced. The conventional technique for forming a metal protrusion (referred to as a hump) is shown in Figure 2 (a).
l and (bl).
第２図（ａｌおよび（ｂ）において、１は基板、２はＡ
Ｎ配線、３はＳｉＯ□などの絶縁膜、４はバリヤメタル
、５はレジスト、６はバンプである。第２図（ａｌは、
通常の工程でＡｅ配′ｆｒｆＡ２の一部を開孔する電極
窓を絶縁膜３に形成した後、バンプ６のめっき時に下地
のＡ１配線２を保護するバリヤメタル４を被着し、レジ
スト５゛によりバンプ６形成部を開孔した後めっきによ
りバンプ６を形成した状態を示す。第２図（ｂ）はバン
プ６のめっき後、バンプ６をマスクとして下地のバリヤ
メタル４をエツチングにより選択的に残し、表出部は除
去した状態を示す。従来法はこの様にバンプ形成後バリ
ヤメタルが除去されていた。すなわち、バンプ形成前に
バリヤメタルを除去することはできなかった。In Fig. 2 (al and (b)), 1 is the substrate, 2 is A
3 is an insulating film such as SiO□, 4 is a barrier metal, 5 is a resist, and 6 is a bump. Figure 2 (al is
After forming an electrode window in the insulating film 3 in which a part of the Ae wiring (frfA2) is opened in a normal process, a barrier metal 4 is deposited to protect the underlying A1 wiring 2 during plating of the bump 6, and a resist 5 is applied. A state in which bumps 6 are formed by plating after opening the bump 6 forming part is shown. FIG. 2(b) shows a state in which after plating the bumps 6, the underlying barrier metal 4 is selectively left by etching using the bumps 6 as a mask, and the exposed portions are removed. In the conventional method, the barrier metal was removed after the bumps were formed. That is, it was not possible to remove the barrier metal before forming the bumps.
第２図（ａｌ （ｂｌに示されるように、バンプ６形成
後バリヤメタル４がエツチングされると、バンプ６がき
のこ状の形をしており、またバンプの幅が１０−１００
μｍとかなり大きいために、バンプ６の張り出し部仔下
方ではメッキ液の到達と循環が悪くなり、またバンプ６
とバリヤメタル４とにより電池が構成されることは避け
られないため午、バンプ６の下のバリヤメタル４がエツ
チングされる。As shown in FIG. 2 (al (bl), when the barrier metal 4 is etched after the bump 6 is formed, the bump 6 has a mushroom-like shape, and the width of the bump is 10-100 mm.
Since the size is quite large (μm), it is difficult for the plating solution to reach and circulate below the protruding portion of the bump 6.
Since it is inevitable that a battery is formed by the bumps 6 and the barrier metal 4, the barrier metal 4 below the bumps 6 is etched.
本発明者は上記問題点を解決するための方法として、バ
ンプの下のバリヤメタルをエツチングからマスクするス
トッパを設ける手段を具体的に検討した。As a method for solving the above-mentioned problems, the present inventors specifically studied means for providing a stopper that masks the barrier metal under the bump from etching.
本発明者は、下記■〜＠を充足するようにバンプを形成
すると、ストッパ物質がバリヤメタルをエツチングから
保護し、問題点が解決されることを見出した。The inventors of the present invention have found that when the bumps are formed so as to satisfy the following conditions 1 to 2, the stopper material protects the barrier metal from etching and the problem is solved.
■ バリヤメタルの少なくとも一部を除去して溝を形成
する。■ Remove at least a portion of the barrier metal to form a groove.
◎ 前記溝形成位置をバンプ形成予定領域の外縁の少な
（ともほぼ全周とする。◎ The groove formation position is set at the outer edge of the area where the bump is to be formed (almost the entire circumference).
０ 前記溝にストッパとなる物質を埋込む。0. Fill the groove with a substance that will serve as a stopper.
■ 前記溝形成位置より外側でバリヤメタルを除去する
際に内側のバリヤメタルをエツチングから保護する。(2) Protecting the inner barrier metal from etching when removing the barrier metal outside the groove forming position.
以下、これらの必要条件を説明する。These requirements will be explained below.
Ｏによりストッパとなる物質を配置する場所を形成する
ため、バンプ形成予定領域の境界を定め、その領域では
バリヤメタル本来の機能を果すとともに、その領域外で
は■によりバリヤメタルを除去できるようにするため、
バリヤメタルの少なくとも一部を除去して溝を形成する
（■）こととした。バリヤメタルはバンプ形成の際バン
プ材の下地への侵入を阻止できまた下地配線との密着性
がよいものであれば特に制限はなく、いかなる材質、層
構造のものでも使用することができる。現在は、Ｎｉ
１０００人（上層）／Ｃｕ２μｍ（中間層）／Ｔｉ１０
００人（下層）の三層構造が多用されている。バリヤメ
タルの除去幅（すなわち溝幅）は、ストッパ物質の耐エ
ツチング性、バンプの大きさ、などによって、定められ
る。バリヤメタルの除去幅はストッパ物質の幅を定め、
この幅が大なほどストッパ機能も高められるので、バリ
ヤメタルの錬去幅は大きければ大きいほど良い。しかし
バリヤメタルの除去幅が大きくなると、ストッパ物質を
めっきで形成する場合はめっき作業が困難になる。In order to form a place to place a substance that will serve as a stopper using O, the boundary of the area where the bump is to be formed is defined, and in that area, the barrier metal performs its original function, and outside of that area, the barrier metal can be removed using ■.
At least a portion of the barrier metal was removed to form a groove (■). The barrier metal is not particularly limited as long as it can prevent the bump material from penetrating into the underlying layer during bump formation and has good adhesion to the underlying wiring, and any material and layered structure can be used. Currently, Ni
1000 people (upper layer)/Cu2μm (middle layer)/Ti10
A three-tier structure of 00 people (lower layer) is often used. The removal width of the barrier metal (ie, groove width) is determined by the etching resistance of the stopper material, the size of the bump, etc. The removal width of the barrier metal determines the width of the stopper material;
The larger the width, the better the stopper function, so the larger the barrier metal removal width, the better. However, if the removal width of the barrier metal becomes large, the plating operation becomes difficult when the stopper material is formed by plating.
上記Ｎｉ ／Ｃｕ ／Ｔｉバリャメクル、バンプのＡＮ
配線からの高さ一８０μｍ、バンプ径−２００μｍの場
合はバリヤメタルの除去幅は５μｍ程度が好ましい。Above Ni/Cu/Ti variamecle, bump AN
When the height from the wiring is -80 .mu.m and the bump diameter is -200 .mu.m, the removal width of the barrier metal is preferably about 5 .mu.m.
前記◎については、バンプ形成予定領域のほぼ全周また
は完全に全周でストッパ機能を実現しなければならない
ため、上述のように規定した。Regarding ◎, the stopper function must be realized almost or completely around the entire circumference of the area where the bump is to be formed, and is therefore defined as described above.
前記Ｏについては、ストッパとなる物質が、バンプ形成
予定領域と、バリヤメタル除去領域との境界に、■のバ
リヤメタル除去時より前に、存在していることが必要で
あるので、上述のように規定した。ストッパとなる物質
はバリヤメタルに対してエツチングの選択性があるもの
であれば、如何なる物質でもよい。例えばＮｉのエッチ
ャントとしてＨＮＯ：ｌ系溶液、Ｃｕのエッチャントと
してｕｏｚ？８？＆、Ｔｉのエッチャントとして希フフ
酸系溶液を用いる場合、Ａ・」、ハンダはこれらの工ソ
チャントに対して不溶性である。Regarding O, it is necessary that a substance to serve as a stopper be present at the boundary between the bump formation area and the barrier metal removal area before the barrier metal is removed in (2), so it is specified as above. did. The stopper material may be any material as long as it has etching selectivity with respect to the barrier metal. For example, HNO:l-based solution is used as an etchant for Ni, and Uoz? as an etchant for Cu. 8? When a dilute hydrofluoric acid solution is used as an etchant for Ti, solder is insoluble in these etchants.
前記■については、バリヤメタル除去は通常の工程であ
るが、ストッパ物質の効果を発現させるための必須の工
程でもあり、また、開花位置より外側でエツチングを行
なうとストッパ物質がエツチングが内側に進行するのを
防止するから、上述のように規定した。Regarding (2) above, barrier metal removal is a normal process, but it is also an essential process for the stopper substance to exhibit its effect, and if etching is performed outside the flowering position, the stopper substance will be etched inward. In order to prevent this, the above provisions were made.
以下、本発明の詳細な説明する。The present invention will be explained in detail below.
第１図ｔａ＋、 （ｂｌ、第３図および第４図は本発明
の基本的バンプ形成方法を図解している。なお図中の符
号１，２，３，４．５は第２図のものと同−層等を示し
ている。第１図（ａｌ、 （ｂｌに示されているように
、レジスト５によって溝状のバリヤメタル除去部■を形
成する。バリヤメタル除去部■の内側の領域はバンプ形
成予定領域■である。よってバリヤメタル除去部■はバ
ンプ形成予定領域すの全周を取り囲むように形成されて
いる。またバンプ形成予定領域■のバリヤメタル４ｂは
バリヤメタル除去部■より外側のバリヤメタル４ａとは
非導通状態になっている。Figure 1 ta+, (bl, Figure 3 and Figure 4 illustrate the basic bump forming method of the present invention. Reference numerals 1, 2, 3, 4.5 in the figures refer to those in Figure 2. As shown in FIGS. 1A and 1B, a groove-shaped barrier metal removed portion (2) is formed using the resist 5. The area inside the barrier metal removed portion (2) is a bump. Therefore, the barrier metal removed portion (2) is formed so as to surround the entire circumference of the bump formation area (2).The barrier metal 4b in the bump formation area (2) is separated from the barrier metal 4a outside the barrier metal removed portion (2). is in a non-conducting state.
第１ （ａｌ、 ｔｂ１図に示されるようにバリヤメタ
ル４を除去した後に、バリヤメタル４ａを陰極とする電
気めっきを行なって、ストッパとなる物質として、例え
ば金１０、をバリヤメタル除去部０に埋め込む。この電
気めっきの初期には、バリヤメタル４ａから金１０のデ
ポジットが開始し、その後金１０は上方向および横方向
に成長し、そしてバリヤメタル４ｂに達する。この時点
で、バリヤメタル４ｂも４ａと導通され、そしてバリヤ
メタル除去部■の断面全体でめっきが進行する。続いて
、レジスト１１によりバンプ形成領域以外をマスクし、
そしてめっきによりバンプ６を形成すると、バンプ６は
金１０とバリヤメタル４ｂ上から成長し、図示のような
きのこ状形状となる。Ｒ１’Ｊｃにレジスト１１を除去
し、エツチングによりバリヤメタル４ａを除去する。こ
のエツチング中に、第５図に図示されるように、バンプ
６が多少サイドエツチングされても、金１０が表出され
た時点より金１０がエツチングのスト、７バとなる。After removing the barrier metal 4 as shown in Figure 1 (al, tb1), electroplating is performed using the barrier metal 4a as a cathode to embed, for example, gold 10 as a stopper material in the barrier metal removed portion 0. At the beginning of electroplating, the deposit of gold 10 starts from the barrier metal 4a, and then the gold 10 grows upwardly and laterally and reaches the barrier metal 4b. At this point, the barrier metal 4b is also in conduction with 4a, and Plating progresses over the entire cross section of the barrier metal removed portion (3).Next, the area other than the bump formation area is masked with resist 11,
When the bumps 6 are formed by plating, the bumps 6 grow from the gold 10 and the barrier metal 4b, forming a mushroom-like shape as shown in the figure. The resist 11 is removed from R1'Jc, and the barrier metal 4a is removed by etching. During this etching, as shown in FIG. 5, even if the bumps 6 are side-etched to some extent, the gold 10 becomes the etching spot 7 from the time the gold 10 is exposed.
第６図（ａｌ、 （ｂ）、第７図および第８図は、バリ
ヤメタルの一部の層をエツチングの際に残して置きそし
てストッパめっきの際の電気的パスとして使用する実施
例である。図中４′はＴｉ層、４″はＰｄまたはＮｉ／
Ｃｕ層を示し、４′と４１によりバリヤメタル４が構成
されている。レジスト５によりバリヤメタル除去部■を
形成する際に、ＰｄまたはＮ ｉ ／ Ｃｕ層４″のみ
を除去しＴｉ層４′を残す。このように一部の層のバリ
ヤメタルを残ずとバリヤメタル４の工・ノチングが簡単
になる。また、電気めっきの代りに無電解めっきも可能
になる。続いて、Ａｕまたはハンダを用いてめっきによ
りストッパ１０を形成しく第７図）、次にレジスト１１
によりマスクされない場所でバンプ６はめっきで形成す
る。最後に、レジスト１１を剥離し、そして表出された
バリヤメタル４をエツチングにより除去する。なお、第
７図に示されるめっき工程を省略し、第８図に示される
レジスト１１をマスクするバンプ６のめっきを行なって
も、Ｔｉ層４′により電気的パスが形成されているため
、バリヤメタル除去部■にバンプの金属が埋め込まれそ
してストッパとしての機能を備える。6(a), 7(b), 7 and 8 are examples in which a portion of the barrier metal layer is left during etching and is used as an electrical path during stopper plating. In the figure, 4' is a Ti layer, and 4'' is a Pd or Ni layer.
A Cu layer is shown, and 4' and 41 constitute a barrier metal 4. When forming the barrier metal removed portion (2) using the resist 5, only the Pd or Ni/Cu layer 4'' is removed, leaving the Ti layer 4'. - Notching becomes easy.Also, electroless plating can be used instead of electroplating.Subsequently, the stopper 10 is formed by plating using Au or solder (Fig. 7), and then the resist 11 is formed by plating with Au or solder.
The bumps 6 are formed by plating in areas that are not masked by. Finally, the resist 11 is peeled off and the exposed barrier metal 4 is removed by etching. Note that even if the plating step shown in FIG. 7 is omitted and the bump 6 is plated to mask the resist 11 shown in FIG. 8, the electrical path is formed by the Ti layer 4', so the barrier metal The metal of the bump is embedded in the removed portion (2) and functions as a stopper.
第９図（ａｌ、 （ｂ）、第１０図および第１１図はバ
ンプめっきを２回行なう実施例である。第９図（ａ）。9(a), FIG. 9(b), FIG. 10, and FIG. 11 are examples in which bump plating is performed twice. FIG. 9(a).
（ｂ）に示す如く、バリヤメタル除去部■を形成後レジ
スト５を剥離し、次に第１０図に示す如く、バンプ材１
２のめっきを行なう。レジスト１３によりバンプ材１２
をバンプ形成予定領域にのみ残す。As shown in FIG. 10, after forming the barrier metal removal portion (2), the resist 5 is peeled off, and then the bump material 1 is removed as shown in FIG.
Perform step 2 plating. Bump material 12 by resist 13
is left only in the area where the bump is to be formed.
なお、バンプ材１２の代りにＡｕなどストッパとしての
機能を有する材料をバンプ形成予定領域に残してもよい
。バンプ材１２の厚さは極く薄く、後工程のバンプめっ
き際の電気的パスとなる程度のものであってよい。続い
て、第１１図に示すように、レジスト１３を剥に１シ、
バンプ形成予定領域外のバリヤメタル４ｂをマスクする
レジスト（図示せず）を形成し、このレジストをマスク
としてバンプ６のめっきを行なう。この場合、バンプ材
１２による電気的パスが形成されており、バンプ材１２
の面積全体が陰極となるから、電気量が多くなりそして
バンプ６が厚くなる。Note that instead of the bump material 12, a material such as Au having a function as a stopper may be left in the area where the bump is to be formed. The thickness of the bump material 12 may be extremely thin and may be just enough to serve as an electrical path during bump plating in a subsequent process. Subsequently, as shown in FIG. 11, the resist 13 is removed and
A resist (not shown) is formed to mask the barrier metal 4b outside the area where the bumps are to be formed, and the bumps 6 are plated using this resist as a mask. In this case, an electrical path is formed by the bump material 12, and the bump material 12
Since the entire area becomes a cathode, the amount of electricity increases and the bump 6 becomes thick.
第１２図（ａ）、 （ｂ）、第１３図および第１４図は
バリヤメタル除去部■をバンプ形成予定領域のほぼ全周
に形成する実施例である。第１２図（ｂｌに示されるよ
うに、０部を除外してバリヤメタル４をし。FIGS. 12(a) and 12(b), FIGS. 13 and 14 show examples in which the barrier metal removed portion (2) is formed almost all around the area where the bump is to be formed. As shown in FIG. 12 (bl), the barrier metal 4 is formed by excluding part 0.
レジスト５をマスクとしてエツチングにより除去する。It is removed by etching using the resist 5 as a mask.
このようにバリヤメタル４の一部を残すことによりバリ
ヤメタル４のエツチングが容易になる。以下の工程は第
３図、第４図、第７図、第９図、第１Ｏ図に示されるも
のを行なう。By leaving a portion of the barrier metal 4 in this manner, etching of the barrier metal 4 becomes easier. The following steps are shown in FIGS. 3, 4, 7, 9, and 1O.
第１３図および第１４図は１回のめっき工程で形成され
るバンプそのものの一部をストッパとして使用する実施
例である。第１図（ａｌ、 （ｂｌ、第６図（ａ）、
Ｆｂｌまたは第１２図（ａ）、 （ｂｌのようにバリヤ
メタル４を除去した後に、レジスト１１をバリヤメタル
除去部■より僅かに外側からバンプ形成予定領域を表出
するようにパターンニングし、そしてバンプ６をめっき
により形成すると、バリヤメタル４ａの外縁はバンプの
脚部「で囲まれ、第１４図で行なわれるバリヤメタル４
ａのエツチングの際にバンプの脚部「が多少は溶解され
ることはあっても溶解がバリヤメタル４ｂに及ぶのを防
止する。FIGS. 13 and 14 show an embodiment in which a part of the bump itself formed in one plating process is used as a stopper. Figure 1 (al, (bl), Figure 6 (a),
After removing the barrier metal 4 as shown in Fbl or FIG. When the barrier metal 4a is formed by plating, the outer edge of the barrier metal 4a is surrounded by the legs of the bump, and the barrier metal 4a is formed by plating as shown in FIG.
Even though the leg portions of the bumps may be slightly melted during etching of step a, this prevents the melting from reaching the barrier metal 4b.
本発明によれば、バンプ下側のバリヤメタルのサイドエ
ッチが防止されるため、バンプとＡｅ配線との電気的接
続が良好になり、そして半導体装置の信頼性が高められ
る。According to the present invention, since side etching of the barrier metal under the bump is prevented, the electrical connection between the bump and the Ae wiring is improved, and the reliability of the semiconductor device is improved.
第１図（ａ）、 （ｂ）は、バリヤメタルに形成する溝
を示した図、
第２図（ａｌ、 （ｂｌは従来のバンプ形成法の説明図
、第３図、第４図は本発明の一実施例によりストッパ物
質を埋め込む工程の説明図、
第５図は形成されたバンプを示す図面、第６図（ａｌ、
（ｈｌ、第７図ｉよび第８図は、本発明の一実施例に
よりバリヤメタルの一部を除去して溝を形成する方法の
説明図、
第９図（ａ）、 （ｂｌ、第１０図および第１１図は、
本発明の一実施例によりめっきを２回行う方法の説明図
、
第１２図（ａｌ、 （ｂｌはバリヤメタル除去部の溝を
バンプ形成予定領域のほぼ全長に形成する本発明の一実
施例の説明図、
第１３図および第１４図はバンプ自体をストッパ物質と
する本発明の一実施例の説明図である。
１・・・基板、 ２・・・Ａ７！配線、３・
・・絶縁膜、 ４・・・バリヤメタル、４ａ・・
・バンプ形成領域外のバリヤメタル、４ｂ・・・バンプ
形成領域内のバリヤメタル、５・・・レジスト、
６・・・バンプ、１０・・・ストッパ、１１・・・レ
ジスト、１２・・・バンプ材。
第８目
第９図（Ｑ） 第９図（ｂ）
第１０図
第１１図Figures 1 (a) and (b) are diagrams showing grooves formed in the barrier metal, Figures 2 (al and bl are explanatory diagrams of the conventional bump forming method, and Figures 3 and 4 are diagrams showing the present invention). An explanatory diagram of the step of embedding a stopper material according to one embodiment; FIG. 5 is a diagram showing the formed bump; FIG. 6 (al,
(hl, Fig. 7i and Fig. 8 are explanatory diagrams of a method of forming a groove by removing a part of the barrier metal according to an embodiment of the present invention, Fig. 9(a), (bl, Fig. 10) and FIG.
An explanatory diagram of a method of performing plating twice according to an embodiment of the present invention. 13 and 14 are explanatory diagrams of an embodiment of the present invention in which the bump itself is used as a stopper material. 1...Substrate, 2...A7! wiring, 3.
...Insulating film, 4...Barrier metal, 4a...
・Barrier metal outside the bump formation area, 4b...Barrier metal inside the bump formation area, 5...Resist,
6... Bump, 10... Stopper, 11... Resist, 12... Bump material. 8th Figure 9 (Q) Figure 9 (b) Figure 10 Figure 11
Claims (1)
体装置の製造方法において、 バンプ形成予定領域の外縁の少なくともほぼ全周でバリ
ヤメタルの少なくとも一部を除去した溝を形成し、前記
溝にストッパ物質を埋め込み、そして前記バンプ形成予
定領域より外側のバリヤメタルをエッチングにより除去
する際に、前記ストッパ物質によって内側のバリヤメタ
ルをエッチングから保護することを特徴とする半導体装
置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device including a step of forming a bump on a barrier metal, comprising: forming a groove from which at least a portion of the barrier metal is removed at least substantially all around the outer edge of a region where the bump is to be formed; A method for manufacturing a semiconductor device, characterized in that when a stopper material is embedded in the trench and the barrier metal outside the bump formation area is removed by etching, the stopper material protects the inner barrier metal from etching.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61200101A JPS6356941A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor device |
| US07/086,805 US4742023A (en) | 1986-08-28 | 1987-08-19 | Method for producing a semiconductor device |
| DE8787307459T DE3777047D1 (en) | 1986-08-28 | 1987-08-24 | METHOD FOR PRODUCING A CONNECTING ELECTRODE OF A SEMICONDUCTOR ARRANGEMENT. |
| EP87307459A EP0261799B1 (en) | 1986-08-28 | 1987-08-24 | Method for producing a terminal electrode of a semi-conductor device |
| KR1019870009416A KR900006511B1 (en) | 1986-08-28 | 1987-08-27 | Method for producting a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61200101A JPS6356941A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356941A true JPS6356941A (en) | 1988-03-11 |
Family
ID=16418859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61200101A Pending JPS6356941A (en) | 1986-08-28 | 1986-08-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356941A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5952746A (en) * | 1982-09-20 | 1984-03-27 | Horiba Ltd | Response film for chloride ion selective electrode and its production |
| JPS6436054A (en) * | 1987-07-31 | 1989-02-07 | Oki Electric Ind Co Ltd | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51151069A (en) * | 1975-06-20 | 1976-12-25 | Matsushita Electric Ind Co Ltd | Electrode forming method of a semiconductor element |
| JPS5674945A (en) * | 1979-11-22 | 1981-06-20 | Toshiba Corp | Electrode forming method of semiconductor element |
-
1986
- 1986-08-28 JP JP61200101A patent/JPS6356941A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51151069A (en) * | 1975-06-20 | 1976-12-25 | Matsushita Electric Ind Co Ltd | Electrode forming method of a semiconductor element |
| JPS5674945A (en) * | 1979-11-22 | 1981-06-20 | Toshiba Corp | Electrode forming method of semiconductor element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5952746A (en) * | 1982-09-20 | 1984-03-27 | Horiba Ltd | Response film for chloride ion selective electrode and its production |
| JPH0240184B2 (en) * | 1982-09-20 | 1990-09-10 | Horiba Ltd | |
| JPS6436054A (en) * | 1987-07-31 | 1989-02-07 | Oki Electric Ind Co Ltd | Semiconductor device |
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