JPS6354226B2 - - Google Patents
Info
- Publication number
- JPS6354226B2 JPS6354226B2 JP56117642A JP11764281A JPS6354226B2 JP S6354226 B2 JPS6354226 B2 JP S6354226B2 JP 56117642 A JP56117642 A JP 56117642A JP 11764281 A JP11764281 A JP 11764281A JP S6354226 B2 JPS6354226 B2 JP S6354226B2
- Authority
- JP
- Japan
- Prior art keywords
- eprom
- manufacturing
- polycrystalline silicon
- gate
- probing test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
この発明はEPROM（Erasable＆
Programmable Read Only Memory）の製造方
法にかかり、特に電気特性の向上をはかるための
製造方法の改良に関する。[Detailed Description of the Invention] This invention is an EPROM (Erasable &
The present invention relates to a manufacturing method for a programmable read only memory (Programmable Read Only Memory), and in particular to improvements in the manufacturing method to improve electrical characteristics.
半導体メモリで書換えを可能にするため、フロ
ーテイングゲートの上にさらにゲートを設けた２
層ゲートMOSによるEPROMがある。これは第
１図に示すように、酸化シリコン層１によつてシ
リコン基板２とも、また相互にも電気絶縁して形
成されたスタツクの多結晶シリコンゲートの下側
の多結晶シリコン層３が電子を捕獲するいわゆる
フローテイングゲートであり、上側の多結晶シリ
コン層４はフローテイングゲートに電子を注入す
るところの書込み用電極として用いられている。
そして、メモリセルとして第２図に示すようにア
ドレス線５とデータ線６とに接続されて回路を形
成する。また、消去するには紫外線を照射するこ
とによつて注入されている電子を放出させ消去を
達成する。このようなEPROMの製造において、
ウエハプロセスが完了したのち探針を用いて電気
的特性を測定するいわゆる、プロービングテスト
を施して書込み特性、入出力リーク等の評価を施
しこのEPROMの歩留りと品質がきまる。 In order to enable rewriting with semiconductor memory, an additional gate is provided on top of the floating gate.
There is an EPROM with layer gate MOS. As shown in FIG. 1, this is due to the fact that the polycrystalline silicon layer 3 under the polycrystalline silicon gate of the stack, which is electrically insulated from the silicon substrate 2 and each other by the silicon oxide layer 1, is This is a so-called floating gate that captures electrons, and the upper polycrystalline silicon layer 4 is used as a write electrode that injects electrons into the floating gate.
Then, as shown in FIG. 2, the memory cell is connected to an address line 5 and a data line 6 to form a circuit. Furthermore, erasing is accomplished by emitting injected electrons by irradiating ultraviolet rays. In manufacturing such EPROM,
After the wafer process is completed, a so-called probing test is performed to measure electrical characteristics using a probe to evaluate write characteristics, input/output leaks, etc. to determine the yield and quality of this EPROM.
上に述べたようにして形成されたEPROMで、
ウエハプロセスを終了したのちのフローテイング
ゲートのSiO2とＰ型の基板２との間に形成され
る表面準位密度は通常２×1010cm-2以下でほとん
ど無視できる程に小さいが、工程中に形成される
歪や、電極形成時に加えられるダメージが完全に
除かれないことが多く、このため品質を低下し歩
留りを悪化するなどの欠点があつた。 With an EPROM formed as described above,
The surface state density formed between the SiO 2 of the floating gate and the P-type substrate 2 after the wafer process is normally 2×10 10 cm -2 or less, which is so small that it can be ignored. In many cases, the strain formed therein and the damage caused during electrode formation are not completely removed, resulting in lower quality and lower yield.
この発明は上記従来の欠点を改良するためにな
されたもので、EPROMの改良された製造方法を
提供する。 This invention was made to improve the above-mentioned conventional drawbacks, and provides an improved method for manufacturing EPROM.
この発明にかかるEPROMの製造方法は、多結
晶シリコン層で構成された２層構造のゲートを有
するものの製造において、プロービングテストに
先行して紫外線照射を施すことを特徴とする。 The method for manufacturing an EPROM according to the present invention is characterized in that ultraviolet irradiation is performed prior to a probing test in manufacturing an EPROM having a gate with a two-layer structure made of polycrystalline silicon layers.
以下に本発明を１実施例につき詳細に説明す
る。Ｐ型のシリコン基板にウエハプロセスを施し
てEPROMを形成し、プロービングテストを施す
に先行して、紫外線照射を施す。この紫外線照射
は例えば40ワツトの紫外線ランプに５cmの距離で
対向させて照射を施すと、第３図に示すように表
面準位密度と相関のあるスレシヨルド電圧VTHが
次第に上昇する傾向にあり、約10時間で飽和す
る。すなわち、表面準位密度が最小になることを
示している。 The present invention will be explained in detail below with reference to one embodiment. A wafer process is performed on a P-type silicon substrate to form an EPROM, and prior to a probing test, ultraviolet rays are irradiated. When this ultraviolet irradiation is performed using, for example, a 40 watt ultraviolet lamp placed at a distance of 5 cm, the threshold voltage V TH , which correlates with the surface state density, tends to gradually rise, as shown in Figure 3. It saturates in about 10 hours. In other words, this shows that the surface state density is minimized.
上述の如く形成されたEPROMではプロービン
グテストを実施した際の書込み特性がきわめて良
好になり、このテストにおける歩留りが約５％向
上をみるという顕著な効果が認められた。また、
この発明は実施が簡単である利点もある。 The EPROM formed as described above had extremely good write characteristics when subjected to a probing test, and a remarkable effect was observed in which the yield in this test was improved by about 5%. Also,
The invention also has the advantage of being simple to implement.
第１図はEPROMの１部の断面図、第２図は
EPROMの一部の回路図、第３図は１実施例の紫
外線照射時間とスルシヨルド値との相関を示す線
図である。
１…酸化シリコン層、３…下側の多結晶シリコ
ン層、４…上側の多結晶シリコン層、５…アドレ
ス線、６…データ線。
Figure 1 is a cross-sectional view of a part of EPROM, Figure 2 is
FIG. 3, which is a circuit diagram of a part of the EPROM, is a diagram showing the correlation between the ultraviolet irradiation time and the Sursjord value in one embodiment. DESCRIPTION OF SYMBOLS 1...Silicon oxide layer, 3...Lower polycrystalline silicon layer, 4...Upper polycrystalline silicon layer, 5...Address line, 6...Data line.
Claims (1)
ートを有するEPROMの製造において、プロービ
ングテストに先立つて紫外線照射を施すことを特
徴とするEPROMの製造方法。1. A method for manufacturing an EPROM, which comprises applying ultraviolet irradiation prior to a probing test in manufacturing an EPROM having a gate with a two-layer structure composed of polycrystalline silicon layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117642A JPS5821368A (en) | 1981-07-29 | 1981-07-29 | Manufacture of erasable and programmable read only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56117642A JPS5821368A (en) | 1981-07-29 | 1981-07-29 | Manufacture of erasable and programmable read only memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5821368A JPS5821368A (en) | 1983-02-08 |
| JPS6354226B2 true JPS6354226B2 (en) | 1988-10-27 |
Family
ID=14716740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56117642A Granted JPS5821368A (en) | 1981-07-29 | 1981-07-29 | Manufacture of erasable and programmable read only memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821368A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161872A (en) * | 1983-03-07 | 1984-09-12 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS59184569A (en) * | 1983-04-05 | 1984-10-19 | Oki Electric Ind Co Ltd | Manufacture of non volatile memory device |
| JPH01172213U (en) * | 1988-05-26 | 1989-12-06 | ||
| DE69126228T2 (en) * | 1990-03-24 | 1997-10-09 | Canon Kk | Optical heat treatment method for semiconductor layer and manufacturing method of semiconductor device with such a semiconductor layer |
-
1981
- 1981-07-29 JP JP56117642A patent/JPS5821368A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5821368A (en) | 1983-02-08 |
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