JPS59161872A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59161872A JPS59161872A JP58035866A JP3586683A JPS59161872A JP S59161872 A JPS59161872 A JP S59161872A JP 58035866 A JP58035866 A JP 58035866A JP 3586683 A JP3586683 A JP 3586683A JP S59161872 A JPS59161872 A JP S59161872A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- ultraviolet rays
- cell transistor
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000012360 testing method Methods 0.000 claims abstract description 7
- 230000001678 irradiating effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000006870 function Effects 0.000 abstract description 4
- XUFQPHANEAPEMJ-UHFFFAOYSA-N famotidine Chemical compound NC(N)=NC1=NC(CSCCC(N)=NS(N)(=O)=O)=CS1 XUFQPHANEAPEMJ-UHFFFAOYSA-N 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000234282 Allium Species 0.000 description 1
- 235000002732 Allium cepa var. cepa Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は高集積回路でかつ集積回路の安定した特性を
得ることができる半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device that is highly integrated and can obtain stable characteristics of the integrated circuit.
（従来技術）
第１図は、半導体装置、詳しくはＦＡＭＯ８型ＥＰＲＯ
Ｍのメモリセルトランジスタ部を示すもので、図中の１
はシリコン基板、２はフィールド酸化膜、３はダート酸
化膜、４は層間酸化膜である。(Prior art) Figure 1 shows a semiconductor device, specifically a FAMO8 type EPRO.
1 in the figure shows the memory cell transistor section of M.
2 is a silicon substrate, 2 is a field oxide film, 3 is a dirt oxide film, and 4 is an interlayer oxide film.
また、５，６はそれぞれフローティングゲートおよびコ
ントロールｆ−）の電極であυ、多結晶シリコン膜で形
成されている。７はソース部拡散層、８はドレイン部拡
散層、９は中間絶縁膜、１０はＡｔ配線である。Further, numerals 5 and 6 are floating gate and control f-) electrodes, respectively, which are formed of polycrystalline silicon films. 7 is a source diffusion layer, 8 is a drain diffusion layer, 9 is an intermediate insulating film, and 10 is an At wiring.
従来の半導体装置の製造方法、特に上述のＥＰＲＯＭの
製造方法には、次のような欠点があった。Conventional semiconductor device manufacturing methods, particularly the above-mentioned EPROM manufacturing method, have the following drawbacks.
ＥＰＲＯＭ（７）＃造工程終了後、集積回路動作機能試
験を行なうが、ＥＰＲＱＭがフローティングゲト構造を
有しているため、製造工程中のノイズ、熱ストレスまた
はイオン照射などのダメージによシミ荷、主として電子
が７０−テインググート５に蓄積され、メモリセルトラ
ンジスタ特性が変動し、規格外れの特性を示し回路動作
試験の結果不良モードとして判定された。EPROM (7)# After the manufacturing process is completed, integrated circuit operation and functional testing is performed, but since EPRQM has a floating gate structure, it may be stained or damaged due to damage such as noise, thermal stress, or ion irradiation during the manufacturing process. Mainly electrons were accumulated in the 70-teinggut 5, and the memory cell transistor characteristics fluctuated, exhibiting characteristics that were out of specification, and as a result of the circuit operation test, it was determined to be in a failure mode.
また、上述のメモリセルトランジスタ特性不安定性のた
めにＥＰＲＯＭの製造工程に各種の特性管理基準を設足
して厳格に管理しても、あらかじめ、電子がフローティ
ングＰ−）に蓄積されることが生じ、特性不安定性を解
消するのが困難であった。Further, due to the instability of the memory cell transistor characteristics mentioned above, even if various characteristics control standards are established in the EPROM manufacturing process and strictly controlled, electrons may be accumulated in the floating P-) in advance. It was difficult to eliminate characteristic instability.
（発明の目的）
この発明は、これらの欠点を解決するためになされたも
ので、メモリセルトランジスタの特性の安定化を期する
ことができる半導体装置の製造方法を提供することを目
的とする。(Object of the Invention) The present invention was made in order to solve these drawbacks, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can stabilize the characteristics of a memory cell transistor.
（発明の構成）
この発明の半導体装置の製造方法は、ＦＡＭＯ８型ＥＰ
ＲＯＭの製造工程終了後集積回路の特性チェックおよび
回路動作機能試験を行なう前に所定波長の紫外線を数十
分照射するよ５にしたものである。(Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device of the present invention.
After completing the ROM manufacturing process and before checking the characteristics of the integrated circuit and testing the circuit operation and function, ultraviolet rays of a predetermined wavelength are irradiated for several minutes.
（実施例〕
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings.
第２図はその一実施例を説明するための図であｐ、図中
の１１はウェハ基板、１２はウェハ支持台、１３は紫外
線ランプを簡略化したものである。FIG. 2 is a diagram for explaining one embodiment of the present invention. In the figure, 11 is a wafer substrate, 12 is a wafer support stand, and 13 is a simplified ultraviolet lamp.
まず、公知の技術により第１図に示すような断面構造を
したメモリセルトランジスタ部を有するＦＡＭＯ８型Ｅ
ＰＲＯＭを形成させた後、第２図に示すようにウェハ基
板１１の表面を上にして、クエ波長の紫外線を紫外線ラ
ンｆ１３Ｖｃよ）、ウェハ基板全面に数１０分照射する
。First, a FAMO8 type E having a memory cell transistor section having a cross-sectional structure as shown in FIG.
After the PROM is formed, as shown in FIG. 2, with the surface of the wafer substrate 11 facing upward, the entire surface of the wafer substrate is irradiated with ultraviolet rays of the Que wavelength for several tens of minutes.
次に、通常測定方法にょシ、ウェハ基板】１の各トラン
ジスタ特性を測定し、その後集積回路動作機能試験を行
なう。Next, using the usual measurement method, the characteristics of each transistor on the wafer substrate (1) are measured, and then an integrated circuit operational function test is performed.
第３図はｒ−）長３μｍレベルのＦＡＭｏｓ型ＥＰＲＯ
Ｍを例にとｐ、紫外線照射前後のメモリセルトランジス
タのｖＴをプロットしたものであるが、紫外線照射前の
ｖＴは１．５４Ｖ〜３．４０ Ｖ迄ばらつきがみられる
が、このウェハに対して水銀ランプ（波長２５３７にの
紫外線）を３０分照射すると、ＶＴは１．４８Ｖ〜１．
６７Ｖとなシばらつきが少なくなった。Figure 3 shows an r-) FAMos type EPRO with a length of 3 μm.
Taking M as an example, the vT of the memory cell transistor before and after UV irradiation is plotted.VT before UV irradiation varies from 1.54V to 3.40V, but for this wafer When irradiated with a mercury lamp (ultraviolet light with a wavelength of 2537) for 30 minutes, VT is 1.48V to 1.
67V, and the variation was reduced.
その後さらに３０分（トータルでは６０分）紫外線照射
してＶＴ （スレッシュホールド電圧）の変動はみられ
ず紫外線照射３０分でメモリセルトランジスタのＶＴが
安定することがわかった。Thereafter, no change in VT (threshold voltage) was observed after UV irradiation for another 30 minutes (60 minutes in total), and it was found that the VT of the memory cell transistor stabilized after 30 minutes of UV irradiation.
なお、紫外線照射として、４．３ ｅＶ以上（４，３ｅ
ＶｉＮ型多結晶Ｓｔダートの場合の価電子帯からの電子
が励起されるエネルギ）の強い紫外ａを数十分間照射す
ると、より効果的である。In addition, as ultraviolet irradiation, 4.3 eV or more (4.3e
Irradiation with strong ultraviolet a (energy that excites electrons from the valence band in the case of ViN type polycrystalline St dirt) for several tens of minutes is more effective.
紫外線照射前ノ’Ｖ’ｒ７Ｊｉ １．５４ Ｖ 〜３．
４０−Ｖ トＩｄらつきがみられたことの理由としては
前述したように、メモリセルトランジスタが７＋：＋−
ティングゲート構造を有しでいるため、製造工程中のノ
イズ、熱ストレスなどのダメージによシミ荷、主とじで
電子が７０〜テイングゲートに蓄積され、その結果メモ
リセルトランジスタのＶＴが変動し、電子蓄積量にばら
つきがおるため、ＶＴがばらつく結果となったからでる
る。Before UV irradiation 'V'r7Ji 1.54 V ~3.
As mentioned above, the reason why the 40-V voltage Id fluctuation was observed is that the memory cell transistor is 7+:+-
Because it has a gate gate structure, electrons are accumulated in the gate gate due to damage such as noise and thermal stress during the manufacturing process, and main stitching, resulting in fluctuations in the VT of the memory cell transistor. This is because the amount of accumulated electrons varies, resulting in variations in VT.
紫外葱照射を行なうと、７０−テインググートに存在す
る電子が紫外線により励起されて高エネルギをもった状
態になシ、フローティングゲートより放出される。その
結果メモリセルトランジスタのｖＴが低下し、ばらつき
が少なくなる。When the onion is irradiated with ultraviolet rays, the electrons present in the 70-teinggut are excited by the ultraviolet rays and are emitted from the floating gate in a high-energy state. As a result, the vT of the memory cell transistor is lowered and variations are reduced.
以上説明したよ５１／（：、第１の実施例でｉ−１集積
゛ 回路動作機能試験１行な９前にウェハ基板表面に２
５３７Ａの波長の紫外ｌｉＭヲ照射することにより、製
造工程中の各種要因によるメモリセルトランジスタの特
性変動を防ぐ利点がある。As explained above, 51/(:, in the first embodiment, the i-1 integrated
The irradiation with ultraviolet LiM having a wavelength of 537A has the advantage of preventing variations in the characteristics of the memory cell transistor due to various factors during the manufacturing process.
加えて、紫外線照射後メモリセルトランジスタのｖＴの
ばらつきが少ないため、特性管理が容易になるという利
点がある。In addition, since there is little variation in vT of memory cell transistors after UV irradiation, there is an advantage that characteristic management becomes easier.
（発明の効果）
以上のように、この発明の半導体装置の製造方法によれ
ば、ＦＡＭＯ８型ＫＰＲＯＭの製造工程終了後集積回路
の特性チェックおよび回路動作機能試験を行なう前に所
定の波長の紫外線を数１０分照射するようにしたので、
製造工程中のノイズ、熱ストレス、イオン照射などのダ
メージにより発生する特性のばらつきを低減させること
ができる。(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, ultraviolet rays of a predetermined wavelength are applied before performing the characteristics check of the integrated circuit and the circuit operation function test after the manufacturing process of the FAMO8 type KPROM is completed. I irradiated it for several 10 minutes, so
It is possible to reduce variations in characteristics caused by damage such as noise, thermal stress, and ion irradiation during the manufacturing process.
これにともないメモリセルトランジスタの特性の安定化
に役立つ利点があり、ＦＡＭＯ８型ＥＰＲＯＭの製造に
利用することができる。This has the advantage of helping to stabilize the characteristics of memory cell transistors, and can be used for manufacturing FAMO8 type EPROMs.
第１図はＦＡＭＯ８型ＥＰＲＯＭのメモリセルトランジ
スタ部の断面図、第２図はこの発明の半導体装置の製造
方法の一実施例に適用される紫外線照射方法の簡略説明
図、第３図は紫外線照射前後のメモリセルトランジスタ
のＶＴ７’ロット図である。
１・・・シリコン基板、２・・・フィールド酸化膜、３
・・・ダート酸化膜、４・・・層間酸化膜、５・・・フ
ローティン？”？ｙ”−）、６・・・コントロールｌ’
−ト、７・・・ソース部拡散層、８・・・ドレイン部拡
散層、９・・・中間絶縁膜、１０・・・Ａｔ配線、１１
・・・ウェハ基板、１２・・・ウェハ支持台、１３・・
・紫外線ランプ。
特許出願人 沖電気工業株式会社
１ 図
嬉 ２ 図
ｆヲ〒ぢ「１２FIG. 1 is a cross-sectional view of the memory cell transistor part of a FAMO8 type EPROM, FIG. 2 is a simplified explanatory diagram of an ultraviolet irradiation method applied to an embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 3 is an ultraviolet irradiation method. FIG. 7 is a VT7' lot diagram of front and rear memory cell transistors. 1... Silicon substrate, 2... Field oxide film, 3
... Dirt oxide film, 4... Interlayer oxide film, 5... Floating? "?y"-), 6...Control l'
7... Source part diffusion layer, 8... Drain part diffusion layer, 9... Intermediate insulating film, 10... At wiring, 11
...Wafer substrate, 12...Wafer support stand, 13...
・Ultraviolet lamp. Patent applicant: Oki Electric Industry Co., Ltd.
Claims (1)
特性チェックおよび回路動作機能試験を行なう前に強い
紫外線を充分照射することを特徴とする半導体装置の製
造方法。A method for manufacturing a semiconductor device, which comprises sufficiently irradiating strong ultraviolet rays after the manufacturing process of a FAMO8 type EPROM is completed and before performing a characteristic check of the integrated circuit and a circuit operation function test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035866A JPS59161872A (en) | 1983-03-07 | 1983-03-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035866A JPS59161872A (en) | 1983-03-07 | 1983-03-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161872A true JPS59161872A (en) | 1984-09-12 |
Family
ID=12453906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58035866A Pending JPS59161872A (en) | 1983-03-07 | 1983-03-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161872A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821368A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Manufacture of erasable and programmable read only memory |
-
1983
- 1983-03-07 JP JP58035866A patent/JPS59161872A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821368A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Manufacture of erasable and programmable read only memory |
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