JPS6353913A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress dislocations and make high quality GaAs system compound grow by a method wherein high concentration impurity doping and a temperature cycle growth method are jointly employed in a growth process such as molecular beam epitaxial growth. CONSTITUTION:A GaAs layer 2a is made to grow on an Si substrate 1 while being doped with an impurity 5 composed of Te with a concentration of 1X10<18>-1X10<20>cm<-3>, preferably 10<19>cm<-2>. Then the growth is discontinued and the temperature of the substrate 1 is lowered to near a room temperature. Accompanying the temperature, mutual reaction between dislocations 4 and the Te impurity is created and the breaking effect of the dislocations is induced. Then, the temperature is made to rise and a GaAs layer 2b is made to grow while being doped with the impurity 5. Then the temperature is allowed to drop to a room temperature. With this process, the dislocations 4 are further suppressed. If the cycle like this is repeated a plurality of times, the dislocation density decreases with an increase in the growth layer thickness. Then a GaAs layer 2A is made to grow on the growth layers as the active layer of a device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for suppressing the generation of dislocations that occur during the growth of a GaAs-based compound semiconductor layer or an InP-based compound semiconductor layer. Regarding.

BACKGROUND ART Recently, heteroepitaxial GaAs growth technology on silicon (Si) substrates has been attracting attention. If the semiconductor material of this form is technically established, gallium arsenide (
This not only makes it possible to reduce the price of GaAs)M devices, such as optical devices and high-speed devices, but also makes it possible to fabricate a composite device in which GnAsI< devices and 81 devices are integrated on the same device.

The above GaA's layer was grown using the 82 Metal Vapor Phase Civil Law (
MOCVD) and molecular beam epitaxial growth (MBE)
However, there is a difference of about 4% in the lattice constants of GaAs and Si, and the linear expansion coefficients are also different, so dislocations occur within the GaAs layer, resulting in high-quality GaAs.
The growth of s is extremely difficult.

Dislocation density depends on growth conditions, but with conventional growth methods,
It is on the order of 310"c-12.

Problems to be Solved by the Invention In order to apply the above-mentioned heteroepitaxial GaAs/Si wafer to various semiconductor devices (optical semiconductor devices and high-speed transistors!?), it is essential to reduce the dislocation density. As a method of lowering dislocation, even if 1
Delmanium (Ge) or GaAs/GaAs f as an intermediate layer between rGaAs/1 and Si substrate.
Although a method of inserting an fi lattice or the like may be mentioned, at present, a growth technique for high-quality heteroepitaxial GaAs has not been established. The current situation is similar to the growth technology of high-quality heteroepitaxial InP.

An object of the present invention is to provide a method for manufacturing a semiconductor device that enables the growth of a high-quality GaAs-based compound semiconductor layer or InP-based compound semiconductor layer with low dislocation density on a J% seed substrate.

Means for Solving the Problems The present invention provides GaAs on a substrate different from GaAs by metal organic vapor phase epitaxy or molecular beam epitaxial growth.
A method for manufacturing a semiconductor device in which an s-based semiconductor is grown, which includes at least one step of crystal growth, cooling of the substrate → heating of the substrate → crystal growth, and during the crystal growth before cooling of the substrate, a substance different from Zn is grown. An impurity whose binding energy with Ga or As is Ga
A semiconductor vcI?, characterized in that such an impurity having a binding energy greater than that of -As is added to a concentration of I x 10'' - I x 1020 am-co.
! This is the 91 construction method.

In the present invention, InP is grown on a substrate different from InP by metal organic vapor phase epitaxy or molecular beam evidaxial growth.
A method of manufacturing a semiconductor device for growing a semiconductor based on crystal growth includes at least one step of cooling down the substrate → heating up the substrate → crystal growth, and during the crystal growth before cooling down the substrate, In or P and Impurities whose bond energy is larger than that of I n −P are separated from 1×1018 to 1×1020 cm to I
This is a method for manufacturing a semiconductor device, characterized in that the addition is carried out so that the concentration is 10''c■-co.

According to the present invention, a GaAs-based compound semiconductor or an InP-based compound semiconductor is grown on a different substrate by metal organic vapor phase epitaxy or molecular beam epitaxial growth, and during this growth process, a high concentration A combination of impurity addition and temperature cycle growth methods is used.

This makes it possible to suppress dislocations and produce high-grade Ga.
An As-based compound semiconductor layer or an InP-based compound semiconductor layer can be grown.

EXAMPLE Generally, there is an interaction between dislocations and impurities in GaAs. The magnitude of this interaction slightly depends on the charge and mass of the impurity. Although electrically neutral, there are impurities (such as In) that strongly interact with dislocations.
Impurities that have a large bonding force with G& ions or As ions are considered to have a large interaction with dislocations. For example, the bond strength between various impurities in GaAs and Ga or As is shown in Pt5l&.

(Leaving space below) Table 1 It is well known that the dislocation density is reduced by adding innoum (In) to the pulling of single crystal GaAs, but in heteroepitaxial growth, simply adding impurities will not be sufficient as described below. The dislocation braking effect due to impurities does not occur effectively. A step to raise the temperature of the substrate is essential.

The braking effect will be explained below. Figure 1 (1
), a GaAs layer 2 is grown on a Si substrate 1 by metal organic vapor phase epitaxy or molecular beam epitaxy. Due to the difference in lattice constant between GaAs and Si, dislocations 4 generated from the interface 3 between GaAsN2 and 5iJJiFj,1 grow simultaneously with the growth of the GaAs layer 2.
It reaches the surface of N2. However, when the temperature of a heteroepitaxial wafer in such a state is lowered from the growth temperature of, for example, 700°C to, for example, 300'C, internal stress is generated in the GaAs layer 2 due to the difference in the #i expansion coefficients of GaAs and Si. , dislocation 4 moves.

Therefore, if the impurity 5 is added to the GaAs layer 2 in advance, the dislocation 4 and the impurity 5 interact, and as shown in Fig. 1 (2).
As shown, the potential energy of the dislocation 4 becomes low. Dislocations in this state are further stimulated by G.
Even if the temperature is raised to aA s#, the dislocation does not return to its original state. This is known as the dislocation braking or pinning effect. The cause of the braking effect is based on the interaction between dislocations (or dislocation loops) 4 and impurities 5. The magnitude of this interaction depends on the impurity concentration, as shown in Figure 2, and is generally about 1019a.
It is logically calculated that a maximum occurs at high concentrations on the order of m-'. In the fjS2 diagram, the horizontal axis shows the impurity concentration, and the vertical axis shows the interaction between dislocations and impurities (dislocation #i
(per t1cm).

As shown in Table 1, a binding energy king effect between Zn and As is expected, but in reality, the braking effect of zinc (Zo) is extremely small. This paradox can be explained as follows. When Zn is present at the Ga site, the Zn-As interaction is 84°4Kcal, 'j+
It is ol. However, since the diffusion constant of Zn is very large, Zn is located between Ga and As (i.e., interstitial).
Easy to get into. Since the interaction between the interstitial Z n and Ga or As is weak, a dislocation braking effect due to Zn cannot be expected in reality.

As is clear from Table 1, boron (B) of group ■, 1,000 elements (N), phosphorus (P), and antimony (s b) of group ■
The bonding force between sulfur (S), selenium (S e), and tellurium (Te) of group II and As or Ga is stronger than the bonding force of Ga-As (47.7Kca)/Shima of), so it provides strong braking. You can expect good results.

An embodiment of the present invention will be described using FIG. 3.

First, as shown in FIG. 3(1), a GaAs layer 2a is grown on a Si substrate 1 by adding an impurity 5 made of Te to a concentration of about IQ 19 cm-3. In order to add Te by organometallic vapor phase epitaxy, it is preferable to use a growing metal consisting of diethyl tellurium (or trimethyl tellurium).

Next, the growth is stopped and the temperature of the Si substrate 1 is lowered to near the lowest temperature. As the temperature decreases, an interaction occurs between the dislocation 4 and the Te impurity vlJ5, as shown in FIG. 3(2), and a braking effect of the dislocation occurs. Next, as shown in the Pt layer 53 (3), the temperature is raised again to the growth temperature, and the GaAs layer 2b is grown while adding Te impurity 5 in the same manner as described above. Next, the temperature is lowered to room temperature in the same manner as described above. This allows t
As shown in Figure 53 (4), dislocations 4 are further suppressed. Thereafter, when the same cycle as above is repeated multiple times, the dislocation density decreases as the thickness of the grown layer increases. And Figure 3 (5)
As shown in , a GaAs layer 2A as a device active layer is grown thereon.

The above explanation has focused on the growth of heteroepitaxial GaAs, but Ga, A 1xA s (0<x<
The same principle that holds true when growing a ternary compound semiconductor layer such as 1) also holds true for heteroepitaxial rnP. Impurities in InP and
Interactions with In or P are shown in Table 2.

(The following is a blank space) PtS2 Table ゛Effects As described above, according to the present invention, it is possible to grow a high-quality GaAs-based compound semiconductor layer or InP-based compound semiconductor layer with low dislocation density on a heterogeneous substrate. .

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the braking effect of dislocations caused by temperature fall, Fig. 2 is a graph showing the relationship between the interaction between dislocations and impurities, and the impurity concentration, and Fig. 1llS3 is a cross-sectional view of one embodiment of the present invention. It is. 1... Substrate, 2.2a, 2b, 2A-GaAs layer,
3... Interface between substrate and GaAs layer, 4... Dislocation, 5
...Impurity agent Patent attorney Number of strokes Keibe 1st figure 3 3rd figure

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device in which a GaAs-based semiconductor is grown on a substrate different from GaAs by metal-organic vapor phase epitaxy or molecular beam epitaxial growth, the steps are: crystal growth → lowering the temperature of the substrate → increasing the temperature of the substrate → crystal growth During the crystal growth before the temperature of the substrate is lowered, an impurity different from Zn whose bonding energy with Ga or As is Ga-
Such an impurity with a binding energy greater than that of As,
1. A method for manufacturing a semiconductor device, characterized in that the additive is added to a concentration of 1×10^1^8 to 1×10^2^0 cm^-^3. (2) In a method for manufacturing a semiconductor device in which an InP-based semiconductor is grown on a substrate different from InP by metal organic vapor phase epitaxy or molecular beam epitaxial growth, the following steps occur: crystal growth → lowering the temperature of the substrate → increasing the temperature of the substrate → crystal growth step, and during crystal growth before the temperature of the substrate is lowered, impurities whose bond energy with In or P is larger than that of In-P are added at 1×10^1^8 to 1×10^2. ^0cm^-^3
1. A method for manufacturing a semiconductor device, characterized in that the additive is added to a concentration of .