JPH08335695A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a compound semiconductor device and a method for the manufacture thereof which prevents degradation in resistance in the surface of a IV compound semiconductor substrate, and endures high-speed or high-frequency practical use. CONSTITUTION: A compound semiconductor thin film 2 is formed on a IV compound semiconductor substrate 1 containing at least in its surface impurities that form a deep energy level both in the IV semiconductor substrate 1 and in the compound semiconductor thin film 2. Then an active element is formed in the compound semiconductor thin film 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly to a compound semiconductor device provided on a group IV semiconductor substrate, particularly a group III-V compound semiconductor device, and its use. The present invention relates to a heteroepitaxial growth method for forming a compound semiconductor thin film.

[0002]

2. Description of the Related Art In recent years, III-V compound semiconductors having a high electron mobility such as GaAs have been used for high-speed semiconductor devices or high-frequency semiconductor devices. These III-V compound semiconductors are used. Substrates are expensive and fragile.

In order to improve such a defect, a group III-V compound semiconductor thin film is heteroepitaxially grown on a group IV semiconductor substrate such as silicon which is inexpensive and has high mechanical strength, and this is grown in a group III-V group. A technique used in place of the compound semiconductor substrate has been developed (Japanese Patent Laid-Open No. 61-262).
16 and Japanese Patent Laid-Open No. 61-70715).

When the III-V group compound semiconductor thin film is heteroepitaxially grown on the silicon substrate as described above, since the lattice constants of silicon and the III-V group compound semiconductor such as GaAs are different, the thin film is grown on the silicon substrate. II
Since the crystallinity of the I-V group compound semiconductor thin film is inferior to that of the III-V group compound semiconductor bulk crystal formed by the pulling method or the like, II
It was necessary to anneal the IV compound semiconductor thin film at a temperature of about 900 ° C. to improve the crystallinity (Japanese Patent Laid-Open No. 1-20).
612).

This conventional heteroepitaxial growth process will be described with reference to FIG. See FIG. 5. After growing the first undoped AlGaAs layer 4 on the silicon substrate 8 at 300 to 450 ° C., 500 to 65
Grow the second undoped AlGaAs layer 5 at 0 ° C.,
Then, the undoped GaAs layer 6 is grown at 600 to 750 ° C.

Then, annealing is performed at 900 ° C. to improve the crystallinity of the undoped GaAs layer 6, and then the HEMT (high electron mobility transistor) and MESFET (Schottky barrier gate field effect transistor) are formed on the undoped GaAs layer 6. ) Or a high speed semiconductor device such as an HBT (hetero bipolar transistor) or a high frequency semiconductor device.

[0007]

However, when annealed at 900 ° C., the constituent elements of the group IV semiconductor substrate and II
Since the constituent elements of the I-V group compound semiconductor thin film act as impurities for determining the conductivity type of each other, each constituent element, particularly,
There has been a problem that the group V element of the III-V group compound semiconductor thin film is solid-phase diffused into the silicon substrate and the surface of the silicon substrate becomes n-type.

Due to the solid phase diffusion of the group V element, the sheet resistance at the interface of the silicon substrate / group III-V compound semiconductor thin film becomes several hundreds Ω / □ or less, and a compound semiconductor device is formed on this group III-V compound semiconductor thin film. In such a case, a leak current also flows in the IV group semiconductor substrate to deteriorate the device characteristics, and when a high frequency semiconductor device used at several GHz or more is provided, it operates due to parasitic capacitance due to the resistance lowering layer. There was a problem of slow speed.

Therefore, it is an object of the present invention to provide a high-speed or high-frequency compound semiconductor device which can prevent the resistance of the surface of the group IV semiconductor substrate from being lowered and can withstand practical use.

[0010]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. See FIG. 1. (1) The present invention provides a compound semiconductor device in which a group IV semiconductor substrate 1 and a compound semiconductor thin film 2 both have at least a surface on which impurities forming deep energy levels are included on the group IV semiconductor substrate 1. , Compound semiconductor thin film 2
Is provided.

(2) In the compound semiconductor device according to the present invention, a III-V group compound semiconductor layer in which the V-group constituent element is nitrogen is provided on the IV group semiconductor substrate 1, and the III-V group compound semiconductor layer is provided. It is characterized in that the compound semiconductor layer 2 is provided thereon.

(3) Further, in the present invention according to the above (2), the group IV semiconductor substrate 1 contains at least a surface of an impurity that forms a deep energy level in both the group IV semiconductor substrate and the compound semiconductor thin film. It is characterized by being

(4) Further, in the present invention according to the above (3), the III-V compound semiconductor layer in which the V group constituent element is nitrogen is GaN, InN, AlN, or a mixed crystal thereof. It is characterized by being.

(5) Further, according to the present invention, in the above (1) or (3), the impurities forming a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 are transition metals. Is characterized by.

(6) Further, in the present invention according to the above (5), the transition metal is Fe, Co, Cr, Ti or A.
u is one of the features.

(7) Further, according to the present invention, in the above (1) to (6), the group IV semiconductor substrate 1 is made of Si, Ge,
Alternatively, it is characterized by being one of SiGe.

(8) Further, according to the present invention, in the above (1) to (7), the compound semiconductor thin film 2 is made of GaAs or Al.
It is characterized by being either GaAs or InGaAs.

(9) In the method of manufacturing a compound semiconductor device according to the present invention, at least the surface of the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 contains impurities forming a deep energy level. It is characterized in that the compound semiconductor thin film 2 is heteroepitaxially grown on the semiconductor substrate 1.

(10) Further, according to the present invention, in the above (9), the group IV semiconductor substrate 1 is ion-implanted with an impurity that forms a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2. It is characterized by introducing.

(11) Further, in the present invention according to the above (9), impurities forming a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 are vapor-phase diffused into the group IV semiconductor substrate 1. It is characterized by being introduced by.

(12) Further, according to the present invention, in the above (9), an impurity that forms a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 is deposited on the group IV semiconductor substrate 1. , And is introduced by solid-phase diffusion by annealing.

(13) Further, in the present invention according to the above item (9), the compound semiconductor thin film 2 comprises at least the first AlG.
It is composed of an aAs layer, a second AlGaAs layer, and a GaAs layer. First, the first AlGa layer at 300 to 450 ° C.
An As layer is grown, then a second AlGaAs layer is grown at 500-650 ° C, then 600-750 ° C.
Is characterized by growing a GaAs layer.

[0023]

By using the group IV semiconductor substrate 1 containing at least the surface of the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 with impurities forming a deep energy level, the annealing process for improving the crystallinity is performed. The constituent element of the compound semiconductor thin film 2 is a group IV semiconductor substrate 1.
Even if the solid-phase diffusion is performed, the electrons or holes resulting from the solid-phase-diffused constituent elements are trapped in a deep energy level and do not become free carriers. Therefore, near the interface between the group IV semiconductor substrate 1 and the compound semiconductor thin film 2. It is possible to prevent lowering of resistance.

The group III-V compound semiconductor layer in which the group V constituent element is nitrogen is thermally stable, and N in the group IV semiconductor substrate does not generate carriers at room temperature, and does not contain other atoms. Since it also functions as a diffusion prevention layer of the group III-V compound semiconductor layer having a group V constituent element of nitrogen on the group IV semiconductor substrate 1, the group III-V group semiconductor is used in an annealing process for improving crystallinity. It is possible to prevent the constituent elements of the compound semiconductor layer or the compound semiconductor thin film 2 from solid-phase diffusing into the group IV semiconductor substrate 1, and thus to prevent the resistance near the surface of the group IV semiconductor substrate 1 from being lowered.

When a III-V group compound semiconductor layer whose group V constituent element is nitrogen is provided on the group IV semiconductor substrate 1, the group IV semiconductor substrate and the compound semiconductor thin film are formed on at least the surface of the group IV semiconductor substrate 1. By including impurities that form deep energy levels in both
It is possible to reliably prevent lowering of resistance near the surface of the V-group semiconductor substrate 1.

Further, by using either GaN, InN, AlN or a mixed crystal thereof as the III-V group compound semiconductor layer in which the group V constituent element is nitrogen, it has relatively good crystallinity. A diffusion prevention layer can be formed.

Further, by using a transition metal as an impurity that forms a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2, a deep energy level is formed in the group IV semiconductor substrate 1 such as silicon. can do.

Further, as transition metals, Fe, Co, C
By using either r, Ti, or Au, a deep energy level can be reliably formed in the group IV semiconductor substrate 1 such as silicon.

As the group IV semiconductor substrate 1, Si,
By using either Ge or SiGe, it is possible to provide a substrate that is inexpensive and has high mechanical strength.

As the compound semiconductor thin film 2, GaA is used.
A high-speed semiconductor device that can be put to practical use by using either s, AlGaAs, or InGaAs.
Alternatively, a high frequency semiconductor device can be manufactured.

Further, the compound semiconductor thin film 2 is heteroepitaxially grown on the group IV semiconductor substrate 1 containing at least the surface of the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 with impurities forming deep energy levels. Thus, it is possible to prevent the resistance near the interface between the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 from being lowered due to the annealing process for improving the crystallinity.

Impurities that form deep energy levels are introduced into the group IV semiconductor substrate 1 by ion implantation to introduce impurities that form deep energy levels in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2. The concentration and depth of can be controlled with high precision.

Further, by introducing into the group IV semiconductor substrate 1 an impurity that forms a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 by vapor phase diffusion, the impurity introduction step is simplified. be able to.

Further, an impurity introducing step is performed by depositing an impurity that forms a deep energy level in both the group IV semiconductor substrate 1 and the compound semiconductor thin film 2 on the group IV semiconductor substrate 1 and performing solid phase diffusion by annealing. Can be simplified.

The compound semiconductor thin film 2 is provided with at least a first AlGaAs layer, a second AlGaAs layer, and
It is composed of a GaAs layer, and firstly at 300-450 ° C
AlGaAs layer is grown, and then 500-650
Grow a second AlGaAs layer at 600C, then 600
By growing the GaAs layer at ˜750 ° C., it is possible to manufacture a compound semiconductor device including a compound semiconductor thin film having crystallinity that can be put to practical use and a group IV semiconductor substrate that maintains high resistance.

[0036]

EXAMPLE A heteroepitaxial growth process of a compound semiconductor device according to a first example of the present invention will be described with reference to FIG. See FIG. 2. First, Fe is contained in the range of 10 ¹⁹ to 10 ²⁰ cm ⁻³ , and [01
1) A Fe-doped silicon substrate 3 having a (100) plane inclined by about 2 ° in the main direction is placed on a carbon susceptor in a reaction tube of a MOVPE apparatus (organic metal vapor phase epitaxy apparatus).

Next, the reaction tube is filled with H ₂ gas of 10000 to 1000.
15,000 sccm, typically 12000 sccm was introduced, and the pressure inside the reaction tube was 50 to 100 Torr, typically 76 Torr, and F was generated by high frequency induction.
The e-doped silicon substrate 3 is heated to 950 to 1100 ° C., typically 1000 ° C. for 10 to 30 minutes, typically
By heat treatment for 20 minutes, the oxide film formed on the surface of the Fe-doped silicon substrate 3 is removed. In addition, in the following steps, the H ₂ flow rate and the pressure in the reaction tube were not changed.

Next, the substrate temperature is set to 300 to 400 ° C., typically 350 ° C., and TMAl (trimethylaluminum) is set to 2 to 3 sccm, typically 2.5 scc.
m, TEGa (triethylgallium) 2-4scc
m, typically ₃ sccm, and AsH ₃ 120-
Introduce 160 sccm, typically 140 sccm,
First undoped AlGaAs layer 4 serving as a buffer layer
(Al ratio is 0.1 to 0.5, typically 0.2)
Deposit 0-20 nm, typically 15 nm. In addition,
When the growth temperature is 400 ° C. or higher, it is difficult to two-dimensionally grow the undoped AlGaAs layer 4 on the Fe-doped silicon substrate 3.

Then, the substrate temperature is raised to 500 to 600 ° C., typically 550 ° C., in order to enhance the crystallinity,
TMAl (trimethylaluminum) 0.2-0.3
sccm, typically 0.25sccm is, TEGa (triethyl gallium) and 0.5～1.5Sccm, typically 1.0 sccm, and the AsH ₃ 50~70sc
cm, typically 60 sccm, and the second undoped AlGaAs layer 5 (Al ratio is 0.1 to 0.5, typically 0.2) serving as a buffer layer is also introduced to 200 to 7
00 nm, typically 500 nm.

Then, the substrate temperature is set to 650 to 750 ° C., typically 700 ° C., and TMGa (trimethylgallium) is set to 2.0 to 3.0 sccm, typically 2.5 sc.
cm and AsH ₃ are introduced at ₃₀ to 40 sccm, typically 35 sccm to deposit the undoped GaAs layer 6 at 0.5 to 1.5 μm, typically 1.0 μm.

Next, the substrate temperature is set to 800 to 1000 ° C., typically 900 ° C. for 10 to 30 minutes, typically 20 while the H ₂ flow rate and the pressure in the reaction tube are not changed.
After annealing for a minute to improve the crystallinity of the undoped GaAs layer 6, the HEMT and ME are applied to the undoped GaAs layer 6.
An SFET or HBT (not shown) is formed.

In this case, since the sheet resistance of the Fe-doped silicon substrate 3 is 10 kΩ / □ or more, the parasitic capacitance due to the low resistance layer does not pose a problem, so that it is used as a substrate for a high frequency semiconductor device operating at several GHz. However, there is no problem.

This state will be described with reference to FIG. See FIG. 3. This FIG. 3 shows the Fe concentration of the Fe-doped silicon substrate 3,
Undoped AlGa is formed on the Fe-doped silicon substrate 3.
It shows the correlation with the sheet resistance of the Fe-doped silicon substrate 3 when the As layers 4 and 5 and the undoped GaAs layer 6 are grown, and when the Fe concentration exceeds 5 × 10 ¹⁸ cm ⁻³ , the sheet It can be seen that the resistance is 10 kΩ / □ or more.

When measuring the sheet resistance, an In electrode was attached to the surface of the heteroepitaxial growth layer, and van
It is measured by the der Paw method, and the data with an arrow at the right end of the figure shows the measurement limit of the device, and shows that the actual sheet resistance is 40 kΩ / □ or more.

In the first embodiment, the Fe-doped silicon substrate 3 in which Fe is doped at the ingot stage is used as the substrate, but the present invention is not limited to such a substrate, and an undoped silicon substrate is formed by another method. May be doped with Fe.

For example, Fe ions may be implanted into the surface of the silicon substrate and then the substrate may be annealed at 1200 ° C. to provide a Fe-doped region on the surface of the silicon substrate. In this case, in the annealing step after the heteroepitaxial growth step. Since the diffusion distance of the group III element and the group V element is about the depth of ion implantation (several hundred to several thousand Å), the group III element and the group V element which have been solid phase diffused in the annealing step after the heteroepitaxial growth step are The resulting electrons and holes can be effectively captured, and free carriers are not generated.

Further, for example, a silicon substrate may be heat-treated at 900 to 1200 ° C. in a ferrocene atmosphere which is a Fe compound to vapor-diffuse Fe onto the surface of the silicon substrate. In this case, a large amount of Fe may be diffused at one time. Since the silicon substrate can be processed, the entire manufacturing process is simplified.

Further, after depositing Fe on the surface of the silicon substrate by a vapor deposition method or the like, the silicon substrate is set to 900-12.
Fe may be heat-treated at 00 ° C. to solid-phase diffuse Fe on the surface of the silicon substrate. In this case as well, a large amount of silicon substrates can be treated at one time, so that the entire manufacturing process is simplified.

Further, although Fe is used as the impurity forming the deep energy level in the first embodiment, it is not limited to Fe and Au, Cr, C may be used.
Alternatively, another transition metal element such as o or Ti may be used.

Next, with reference to FIG. 4, a heteroepitaxial growth process of the compound semiconductor device of the second embodiment of the present invention will be described with reference to FIG. See FIG. 4. First, similarly to the first embodiment, Fe is added to 10 ¹⁹ to 10 ²⁰ c.
A carbon susceptor in a reaction tube of a MOVPE apparatus (organic metal vapor phase epitaxy apparatus) including an Fe-doped silicon substrate ³ containing m ⁻³ and having a (100) plane that is inclined by about 2 ° in the [011] direction as a main surface. Place it on top of the reaction tube and add H ₂ gas to the reaction tube at 10
000-15000sccm, typically 12000s
ccm is introduced and the pressure in the reaction tube is 50 to 100 Tor.
The Fe-doped silicon substrate 3 is set to 950 to 1100 by high frequency induction under the condition of r, typically 76 Torr.
The oxide film formed on the surface of the Fe-doped silicon substrate 3 is removed by heating at 0 ° C., typically 1000 ° C., and performing heat treatment for 10 to 30 minutes, typically 20 minutes.

Next, the substrate temperature is set to 350 to 450 ° C., typically 400 ° C., and TMGa (trimethylgallium) is set to 2 to 3 sccm, typically 2.5 sccm, N 2.
_2-3 sccm H ₃ , typically 2.5 sccm, and H ₂ 130-160 sccm, typically 150
Introducing sccm, the pressure inside the reaction tube is 50-100 Tor
The GaN layer 7 is deposited to a thickness of 5 to 90 nm, typically 15 nm, at a temperature of r, typically 76 Torr. (For the GaN growth method, see T. Lei, et.
al. , Appl. Phys. Lett. , Vol. 5
9, no. 8, p. See 944. )

Next, the substrate temperature is raised to 500 to 600 ° C., typically 550 ° C., with the same H ₂ flow rate and reaction tube internal pressure as in the first embodiment, and TMAl (trimethylaluminum) is added to 0.2 to 10. 0.3 sccm, typically 0.25 sccm, TEGa (triethylgallium) 0.5-1.5 sccm, typically 1.0 sccm,
And 50 to 70 sccm of AsH ₃ , typically 60
sccm is introduced, and the undoped AlGaAs layer 5 (Al
The ratio is 0.1-0.5, typically 0.2) to 200-
Deposition is 700 nm, typically 500 nm.

Then, the substrate temperature is set to 650 to 750 ° C., typically 700 ° C., and TMGa (trimethylgallium) is set to 2.0 to 3.0 sccm, typically 2.5 sc.
cm and AsH ₃ are introduced at ₃₀ to 40 sccm, typically 35 sccm to deposit the undoped GaAs layer 6 at 0.5 to 1.5 μm, typically 1.0 μm.

Then, the substrate temperature is set to 800 to 1000 ° C., typically 900 ° C. for 10 to 30 minutes, typically 20 while the H ₂ flow rate and the pressure in the reaction tube are not changed.
After annealing for a minute to improve the crystallinity of the undoped GaAs layer 6, the HEMT and ME are applied to the undoped GaAs layer 6.
An SFET or HBT (not shown) is formed.

In this case, Fe without the GaN layer 7 provided
The sheet resistance of the doped silicon substrate 3 was about 10 kΩ / □, but the sheet resistance when the GaN layer 7 was provided was
When examined by Hall measurement, it is 30 kΩ / □ or more, and the high resistance of the substrate can be maintained.

Since GaN is a semiconductor having a strong binding energy, the Fe-doped silicon substrate 3 is kept at 700 ° C.
Even if the GaN is decomposed, it hardly decomposes and diffuses into the Fe-doped silicon substrate 3, and even if the temperature becomes higher and N diffuses into the Fe-doped silicon substrate 3, N does not change at room temperature. Since no carriers are generated, the resistance of the surface of the Fe-doped silicon substrate 3 is not lowered.

Although the GaN layer 7 is used as the III-V group compound semiconductor layer in which N is the group V element in the second embodiment, it is not limited to the GaN layer 7.
It may be an InN layer, an AlN layer, or a mixed crystal of an InN layer, an AlN layer, and a GaN layer.

Also in the case of the second embodiment, the Fe-doped silicon substrate 3 may be formed by ion implantation, vapor phase diffusion, or solid phase diffusion as in the first embodiment. Alternatively, other transition metal elements such as Au, Cr, Co, or Ti may be used instead of Fe.

However, in the case of the second embodiment, the substrate is not necessarily the Fe-doped silicon substrate 3, and although the resistance is somewhat lowered, an undoped silicon substrate may be used.

Further, in the first and second embodiments, the undoped AlGaAs layers 4 and 5 serving as the buffer layers are formed.
Via the undoped GaAs layer 6 as an active element forming layer
However, the active element forming layer may be AlGaAs,
Alternatively, it may be InGaAs.

In general, the active element forming layer is made of AlA.
s, InAs, GaP, AlP, InP, GaSb, A
It may be a III-V group compound semiconductor made of a mixed crystal containing 1Sb, InSb, or GaAs, and may be a II-VI group compound semiconductor.

Further, although the silicon substrate is used as the group IV semiconductor substrate, it is not limited to the silicon substrate, and another group IV semiconductor substrate such as a Ge substrate or a SiGe substrate may be used. .

In the first and second embodiments, the low pressure MOVPE method is used as the crystal growth method, but the present invention is not limited to such a low pressure MOVPE method, and the MBE method (molecular beam epitaxial growth method) is used. ), MOM
The BE method (organic metal molecular beam epitaxial growth method) or the GSMBE method (gas source molecular beam epitaxial growth method) may be used.

Further, the numerical conditions described in the above first and second embodiments are not necessarily essential, and may be appropriately changed according to the structure or characteristics of the compound semiconductor device to be obtained. .

[0065]

According to the present invention, a group IV semiconductor substrate doped with an impurity forming a deep energy level is used as a substrate for growing a compound semiconductor thin film.
III-V containing N such as GaN as a group V element on a group semiconductor substrate
Since the group compound semiconductor layer is provided, even if the compound semiconductor layer is heteroepitaxially grown on it and then annealed to improve the crystallinity, the surface of the group IV semiconductor substrate does not decrease in resistance, and the high frequency semiconductor device It is possible to provide an inexpensive growth substrate for use.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of effects of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional heteroepitaxial growth process.

[Explanation of symbols]

 1 Group IV Semiconductor Substrate 2 Compound Semiconductor Thin Film 3 Fe-Doped Silicon Substrate 4 Undoped AlGaAs Layer 5 Undoped AlGaAs Layer 6 Undoped GaAs Layer 7 GaN Layer 8 Silicon Substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/205 (72) Inventor Shinji Miyagaki 1015 Uedotachu, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Osamu Ueda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (13)

[Claims] 1. A compound semiconductor device in which a compound semiconductor thin film is provided on a group IV semiconductor substrate, wherein a deep energy level is provided on at least the surface of the group IV semiconductor substrate in both the group IV semiconductor substrate and the compound semiconductor thin film. A compound semiconductor device comprising impurities to be formed. 2. A compound semiconductor device having a compound semiconductor thin film formed on a group IV semiconductor substrate, wherein the group V constituent element is nitrogen between the group IV semiconductor substrate and the compound semiconductor thin film. A compound semiconductor device comprising: 3. The group IV semiconductor substrate according to claim 2, wherein at least the surface of the group IV semiconductor substrate contains impurities forming a deep energy level in both the group IV semiconductor substrate and the compound semiconductor thin film. Compound semiconductor device. 4. The III-V compound semiconductor layer, wherein the V-group constituent element is nitrogen, is GaN, InN, AlN, or
4. The compound semiconductor device according to claim 3, wherein the compound semiconductor is any one of these mixed crystals. 5. The compound semiconductor device according to claim 1, wherein the impurities forming a deep energy level in both the group IV semiconductor substrate and the compound semiconductor thin film are transition metals. 6. The transition metal is Fe, Co, Cr, T.
6. The compound semiconductor device according to claim 5, wherein the compound semiconductor device is either i or Au. 7. The group IV semiconductor substrate is made of Si, Ge,
Alternatively, the compound semiconductor device according to any one of claims 1 to 6, which is any one of SiGe. 8. The compound semiconductor thin film comprises GaAs, A
8. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is one of InGaAs and InGaAs. 9. A method of manufacturing a compound semiconductor device in which a compound semiconductor thin film is heteroepitaxially grown on a group IV semiconductor substrate, wherein at least the surface of the group IV semiconductor substrate is deep in both the group IV semiconductor substrate and the compound semiconductor thin film. A method for manufacturing a compound semiconductor device, comprising an impurity forming an energy level. 10. The compound semiconductor according to claim 9, wherein impurities forming deep energy levels in both the group IV semiconductor substrate and the compound semiconductor thin film are introduced into the group IV semiconductor substrate by ion implantation. Device manufacturing method. 11. The compound according to claim 9, wherein impurities forming deep energy levels in both the group IV semiconductor substrate and the compound semiconductor thin film are introduced into the group IV semiconductor substrate by vapor phase diffusion. Manufacturing method of semiconductor device. 12. The IV film on the IV semiconductor substrate
10. The method for manufacturing a compound semiconductor device according to claim 9, wherein impurities forming a deep energy level are deposited on both the group semiconductor substrate and the compound semiconductor thin film, and the impurities are introduced by solid phase diffusion by annealing. 13. The compound semiconductor thin film comprises at least a first AlGaAs layer, a second AlGaAs layer, and
The first AlGaAs layer is composed of a GaAs layer, and is grown at 300 to 450 ° C., and then 500 to 65.
Grow a second AlGaAs layer at 0 ° C., then 60
The method of manufacturing a compound semiconductor device according to claim 9, wherein the GaAs layer is grown at 0 to 750 ° C.