JPS6353792B2 - - Google Patents
Info
- Publication number
- JPS6353792B2 JPS6353792B2 JP56064789A JP6478981A JPS6353792B2 JP S6353792 B2 JPS6353792 B2 JP S6353792B2 JP 56064789 A JP56064789 A JP 56064789A JP 6478981 A JP6478981 A JP 6478981A JP S6353792 B2 JPS6353792 B2 JP S6353792B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse width
- voltage
- switching regulator
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000008859 change Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000003111 delayed effect Effects 0.000 claims description 4
- 230000004907 flux Effects 0.000 description 21
- 238000004804 winding Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 13
- 230000005415 magnetization Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 5
- 238000009499 grossing Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 238000003079 width control Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
- H02M3/3376—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current
Description
【発明の詳細な説明】
本発明は１対のスイツチングトランジスタを交
互に導通させてパルス幅制御を行うスイツチング
レギユレータに関し、負荷が急激に重くなつた場
合の該トランジスタの破損の防止を目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching regulator that performs pulse width control by alternately conducting a pair of switching transistors, and is designed to prevent damage to the transistors when the load suddenly increases. purpose.
この種のスイツチングレギユレータとしては、
代表的なものとして第１図の回路図に示すような
ハーフブリツジ形のものがある。このスイツチン
グレギユレータはスイツチングトランジスタであ
る１対のトランジスタＱ１，Ｑ２を交互に「オ
ン」して、商用電源１からフイルタ２、整流平滑
回路３を径て得た直流電圧を主トランスＴ１の１
次巻線Ｌ１１に加え、交互に反対方向の電流を流
し、主トランスＴ１の２次巻線Ｌ１２，Ｌ１３に
Ｌ１１との巻線比で定まる交流電圧を誘起させ
る。そしてダイオードＤ１，Ｄ２により整流し
て、チヨークコイルCL、電解コンデンサＣ１に
より平滑して、直流の出力電圧Vputを出力端子
７，７′に得る。誤差増幅器Ａ２２は検出した出
力電圧を基準電源Ｅ１の電圧と比較して第２図ｂ
のような誤差信号を発生し、パルス幅変調器４の
比較器Ｃは誤差信号を発振器OSが発生する第２
図ａの鋸歯状波信号と比較する。そして鋸歯状波
信号が誤差信号を越える期間だけフリツプフロツ
プ回路Ｆの発生する信号に同期したノア回路
NORの働きにより、ドライブトランスＴ２の１
次側に接続されているドライブトランジスタＱ
３，Ｑ４が交互に「オン」する。２次側の１対の
トランジスタＱ１，Ｑ２が１次側のトランジスタ
と同じように「オン」することによりパルス幅制
御が行なわれて出力電圧Vputは所定の値に維持さ
れる。 As this type of switching regulator,
A typical example is a half-bridge type as shown in the circuit diagram of FIG. This switching regulator turns on a pair of transistors Q1 and Q2, which are switching transistors, alternately, and transfers a DC voltage obtained from a commercial power supply 1 through a filter 2 and a rectifying and smoothing circuit 3 to the main transformer T1. 1
In addition to the current in the secondary winding L11, a current is passed in the opposite direction alternately to induce an AC voltage in the secondary windings L12 and L13 of the main transformer T1 determined by the winding ratio with L11. Then, it is rectified by diodes D1 and D2, and smoothed by a choke coil CL and an electrolytic capacitor C1 to obtain a DC output voltage V put at output terminals 7 and 7'. The error amplifier A22 compares the detected output voltage with the voltage of the reference power supply E1 and compares the detected output voltage with the voltage of the reference power supply E1.
The comparator C of the pulse width modulator 4 generates an error signal as shown in FIG.
Compare with the sawtooth wave signal in Figure a. And a NOR circuit synchronized with the signal generated by the flip-flop circuit F only during the period when the sawtooth wave signal exceeds the error signal.
Due to the action of NOR, 1 of drive transformer T2
Drive transistor Q connected to the next side
3. Q4 is turned on alternately. By turning on the pair of transistors Q1 and Q2 on the secondary side in the same way as the transistors on the primary side, pulse width control is performed and the output voltage Vput is maintained at a predetermined value.
誤差増幅器Ａ１１は過電流を検出し保護動作を
行う役割を有しており、誤差増幅器Ａ２２とは
OR接続されている。又Ｅ２は補助電源である。
しかしこのような従来のスイツチングレギユレー
タは負荷が急激に重くなつた場合に主トランスＴ
１のコアが磁気飽和し、トランジスタＱ１、トラ
ンジスタＱ２のいずれかに大きなコンデンサ電流
が流れて破損する事故が発生しやすかつた。動作
波形図である第２図の時刻ｔ１から時刻ｔ３まで
の時間はこの磁気飽和が生じた時の状態を表して
いる。 Error amplifier A11 has the role of detecting overcurrent and performing protective operation, and what is error amplifier A22?
OR connected. Further, E2 is an auxiliary power source.
However, with such conventional switching regulators, when the load suddenly becomes heavy, the main transformer T
The core of transistor Q1 becomes magnetically saturated, and a large capacitor current flows through either transistor Q1 or transistor Q2, easily causing damage to the transistor. The time from time t1 to time t3 in FIG. 2, which is an operation waveform diagram, represents the state when this magnetic saturation occurs.
なお第２図ｃはパルス幅変調器４のP2点の電
圧波形、第２図ｄはドライブトランジスタＱ３の
コレクタ電流波形、第２図ｅはドライブトランジ
スタＱ４のコレクタ電流波形、第２図ｆは主トラ
ンジスタＴ１の１次巻線Ｌ１１を流れる電流波
形、第２図ｇは主トランスＴ１のコアの磁束密度
を夫々表しており、横軸は共通の時間ｔを表して
いる。 Note that Fig. 2c shows the voltage waveform at point P2 of the pulse width modulator 4, Fig. 2d shows the collector current waveform of the drive transistor Q3, Fig. 2e shows the collector current waveform of the drive transistor Q4, and Fig. 2f shows the main waveform. The current waveform flowing through the primary winding L11 of the transistor T1 and FIG. 2g each represent the magnetic flux density of the core of the main transformer T1, and the horizontal axis represents the common time t.
すなわち負荷が急激に重くなり時刻ｔ１で誤差
増幅器Ａ２２の発生電圧が低くなつた場合、（−）
方向にわずかに磁化していた主トランスＴ１のコ
アは１次巻線Ｌ１１の電流により直ちに反対方向
である（＋）方向に磁化されてゆく。そして時刻
ｔ２で（＋）方向の最大磁束密度＋BMに達し磁
気飽和すると、１次巻線Ｌ１１の電流は急激に増
加し、いずれか「オン」しているスイツチングト
ランジスタには「オフ」する時刻ｔ３まで大きな
コレクタ電流が流れる。この種のスイツチングレ
ギユレータの主トランスは最大パルス幅において
正負の磁束飽和する範囲間において磁束変化する
ように設計され、スイツチングトランジスタもこ
れに見合つたものが用いられているが、このよう
に過渡的に流れる過大なコレクタ電流によつて破
壊にいたることが多い。 In other words, if the load suddenly becomes heavy and the voltage generated by the error amplifier A22 becomes low at time t1, (-)
The core of the main transformer T1, which had been slightly magnetized in this direction, is immediately magnetized in the opposite direction (+) by the current in the primary winding L11. Then, at time t2, when the maximum magnetic flux density in the (+) direction reaches +B M and magnetic saturation occurs, the current in the primary winding L11 increases rapidly, and any switching transistor that is "on" is turned "off". A large collector current flows until time t3. The main transformer of this type of switching regulator is designed so that the magnetic flux changes between the positive and negative magnetic flux saturation ranges at the maximum pulse width, and the switching transistors used are also suitable for this. Destruction is often caused by excessive collector current that flows transiently.
従つて電流容量の大きなスイツチングトランジ
スタを用いたり、コアの最大磁束密度の大きな主
トランスを用いる必要があり、不経済であると共
にスイツチングレギユレータ全体の形状も大型に
なつた。 Therefore, it is necessary to use a switching transistor with a large current capacity or a main transformer whose core has a large maximum magnetic flux density, which is not only uneconomical but also increases the size of the entire switching regulator.
本発明はこのような欠点を除き、電流容量に極
端な余裕を持たせたトランジスタやコアの最大磁
束密度の大きな主トランスを用いなくてもスイツ
チングトランジスタの破損を防ぎ得るスイツチン
グレギユレータを提供することを目的とする。 The present invention eliminates these drawbacks and provides a switching regulator that can prevent damage to the switching transistor without using a transistor with an extremely large current capacity or a main transformer with a large maximum magnetic flux density core. The purpose is to provide.
本発明の他の目的は、主トランスを小形化する
ことのできるスイツチングレギユレータを提供す
ることである。 Another object of the present invention is to provide a switching regulator whose main transformer can be downsized.
本発明は、１対のトランジスタを夫々のベース
入力により交互に「オン」して主トランスの１次
側に交互に反対方向の電流を流し、その２次誘起
電圧を整流して直流出力を得ると共に、検出出力
電圧値に応じてパルス幅変調器により前記トラン
ジスタのベース入力のパルス幅を制御して出力電
圧が一定になるようにしたスイツチングレギユレ
ータにおいて、パルス幅変調器の入力側には、コ
ンデンサと抵抗を含む時定数回路、該時定数回路
を負荷とするエミツタホロワ回路が接続され、該
エミツタホロワ回路には検出出力電圧値に応じた
誤差信号を得る誤差増幅器が接続され、さらにエ
ミツタホロワ回路と時定数回路との接続点および
アース間に定電流回路が接続されており、前記ベ
ース入力のパルス幅を増大させる場合には、パル
ス幅変調器に加わる入力の変化が遅延されるよう
にしたことを特徴とする。 In the present invention, a pair of transistors are alternately turned on by their base inputs, currents in opposite directions alternately flow through the primary side of the main transformer, and the secondary induced voltage is rectified to obtain a DC output. In addition, in the switching regulator, the pulse width of the base input of the transistor is controlled by a pulse width modulator according to the detected output voltage value so that the output voltage is constant. is connected to a time constant circuit including a capacitor and a resistor, an emitter follower circuit whose load is the time constant circuit, an error amplifier for obtaining an error signal according to the detected output voltage value is connected to the emitter follower circuit, and an emitter follower circuit is connected to the emitter follower circuit. A constant current circuit is connected between the connection point of the base input and the time constant circuit, and the ground, so that when the pulse width of the base input is increased, a change in the input applied to the pulse width modulator is delayed. It is characterized by
以下本発明のスイツチングレギユレータの一実
施例を示す回路図である第３図により説明する。
なお第１図と同一部分は同じ符号を付与してあ
る。 A description will be given below with reference to FIG. 3, which is a circuit diagram showing one embodiment of the switching regulator of the present invention.
Note that the same parts as in FIG. 1 are given the same reference numerals.
第３図において商用電源１からフイルタ２、整
流平滑回路３を経て得られた直流電圧は電解コン
デンサＣ２，Ｃ３の直列回路の両端に加えられ、
さらにスイツチングトランジスタであるトランジ
スタＱ１のコレクタとトランジスタＱ２のエミツ
タに加えられる。 In FIG. 3, a DC voltage obtained from a commercial power source 1 through a filter 2 and a rectifying and smoothing circuit 3 is applied to both ends of a series circuit of electrolytic capacitors C2 and C3.
Furthermore, it is added to the collector of transistor Q1 and the emitter of transistor Q2, which are switching transistors.
直列回路の中間の接続点は主トランスＴ１の１
次巻線Ｌ１１の一端に接続され、１次巻線Ｌ１１
の他端はトランジスタＱ１のエミツタとトランジ
スタＱ２のコレクタの接続点に接続される。トラ
ンジスタＱ１のベースとエミツタはドライブトラ
ンスＴ２の２次巻線Ｌ２２を介して接続されてお
り、トランジスタＱ２のベースとエミツタはトラ
イブトランスＴ２の他の２次巻線Ｌ２３を介して
接続されている。Ｒ５，Ｒ６はバイアス抵抗であ
る。 The middle connection point of the series circuit is 1 of the main transformer T1.
Connected to one end of the secondary winding L11, the primary winding L11
The other end is connected to the connection point between the emitter of transistor Q1 and the collector of transistor Q2. The base and emitter of transistor Q1 are connected through a secondary winding L22 of drive transformer T2, and the base and emitter of transistor Q2 are connected through another secondary winding L23 of drive transformer T2. R5 and R6 are bias resistors.
主トランスＴ１の２次巻線Ｌ１２，Ｌ１３は整
流、平滑回路を介して出力端子７，７′へ接続さ
れる。出力端子７，７′間に接続される抵抗Ｒ１，
Ｒ２の接続点は誤差増幅器Ａ２の正入力端に接続
され、その出力側はパルス幅変調器４の比較器Ｃ
の入力側に発振器OSと共に接続される。比較器
Ｃの出力側はフリツプフロツプ回路Ｆの入力側に
接続されると共にフリツプフロツプ回路Ｆの出力
側と共に２個のノア回路NORに接続される。ノ
ア回路NORの出力側は夫々ドライブトランジス
タＱ３，Ｑ４のベースに接続される。 Secondary windings L12 and L13 of the main transformer T1 are connected to output terminals 7 and 7' via a rectifying and smoothing circuit. A resistor R1 connected between output terminals 7 and 7',
The connection point of R2 is connected to the positive input terminal of the error amplifier A2, and its output side is connected to the comparator C of the pulse width modulator 4.
is connected to the input side of the oscillator OS. The output side of the comparator C is connected to the input side of the flip-flop circuit F and, together with the output side of the flip-flop circuit F, to two NOR circuits NOR. The output side of the NOR circuit NOR is connected to the bases of drive transistors Q3 and Q4, respectively.
ドライブトランジスタＱ３，Ｑ４のエミツタは
互に接続されており、コレクタはドライブトラン
スＴ２の１次巻線Ｌ２１の両端に接続され、１次
巻線Ｌ２１の中間タツプとドライブトランジスタ
Ｑ３，Ｑ４のエミツタは補助電源Ｅ２に接続され
る。誤差増幅器Ａ１は抵抗Ｒ３により過電流を検
出し保護動作を行う役割を有しており、誤差増幅
器Ａ２とはOR接続されることにより過電流検出
時に誤差増幅器Ａ２より優先して動作する。誤差
増幅器Ａ２の負入力端と、誤差増幅器Ａ１の正入
力端にはバイアス抵抗を介して基準電源Ｅ１が接
続される。なおいずれの誤差増幅器も出力側はエ
ミツタホロワ回路が接続されており、ダイオード
の符号で表してある。またエミツタホロワ回路に
は、負荷としてコンデンサＣ４と抵抗Ｒ４の直列
回路からなる時定数回路５が接続されている。そ
して時定数回路５とエミツタホロワ回路の接続点
Ｐ１およびアース間には、定電流回路６が接続さ
れている。 The emitters of the drive transistors Q3 and Q4 are connected to each other, the collectors are connected to both ends of the primary winding L21 of the drive transformer T2, and the intermediate tap of the primary winding L21 and the emitters of the drive transistors Q3 and Q4 are connected to each other. Connected to power supply E2. The error amplifier A1 has the role of detecting overcurrent using a resistor R3 and performing a protective operation, and is OR-connected with the error amplifier A2 so that it operates with priority over the error amplifier A2 when overcurrent is detected. A reference power source E1 is connected to the negative input terminal of the error amplifier A2 and the positive input terminal of the error amplifier A1 via a bias resistor. Note that the output side of each error amplifier is connected to an emitter follower circuit, which is represented by a diode symbol. Further, a time constant circuit 5 consisting of a series circuit of a capacitor C4 and a resistor R4 is connected as a load to the emitter follower circuit. A constant current circuit 6 is connected between the connection point P1 between the time constant circuit 5 and the emitter follower circuit and the ground.
このように構成されたスイツチングレギユレー
タの動作を第４図を、第５図，第６図を参照しな
がら説明する。 The operation of the switching regulator configured as described above will be explained with reference to FIG. 4, FIG. 5, and FIG. 6.
第４図は動作波形図であり、第４図ａは発振器
OSの発生する電圧波形、第４図ｂは接続点Ｐ１
の電圧波形、つまり点Ｐ１の電圧波形、第４図ｃ
はパルス幅変調器４のＰ２点の電圧波形、第４図
ｄはドライブトランジスタＱ３のコレクタ電流波
形、第４図ｅはドライブトランジスタＱ４のコレ
クタ電流波形、第４図ｆは主トランスＴ１の１次
巻線Ｌ１１を流れる電流波形、第４図ｇは主トラ
ンスＴ１のコアの磁束密度を夫々表しており、横
軸は共通の時間ｔを表している。 Figure 4 is an operating waveform diagram, and Figure 4a is an oscillator.
The voltage waveform generated by OS, Figure 4b is the connection point P1
, that is, the voltage waveform at point P1, Fig. 4c
is the voltage waveform at point P2 of the pulse width modulator 4, FIG. 4d is the collector current waveform of the drive transistor Q3, FIG. 4e is the collector current waveform of the drive transistor Q4, and FIG. 4f is the primary of the main transformer T1. The current waveform flowing through the winding L11 in FIG. 4g represents the magnetic flux density of the core of the main transformer T1, and the horizontal axis represents the common time t.
第５図は主トランスＴ１のコアの磁化特性を示
す図であり、説明を容易にするためにヒステリシ
スがないものとして表してある。横軸は１次巻線
Ｌ１１の電流による磁界Ｈを表している。 FIG. 5 is a diagram showing the magnetization characteristics of the core of the main transformer T1, and is shown without hysteresis for ease of explanation. The horizontal axis represents the magnetic field H due to the current in the primary winding L11.
第６図は誤差増幅器Ａ２の出力側の回路図が示
してある。誤差増幅器Ａ２の出力側に接続するエ
ミツタホロワ回路を構成するトランジスタＱ５が
「オン」した時、定電圧VCCはエミツタに接続さ
れている定電流回路６の数10倍の電流をコレクタ
電流として流し得る。 FIG. 6 shows a circuit diagram of the output side of the error amplifier A2. When the transistor Q5 constituting the emitter follower circuit connected to the output side of the error amplifier A2 is turned on, the constant voltage V CC can flow as a collector current several tens of times the current of the constant current circuit 6 connected to the emitter. .
第３図に示す本発明の実施例のスイツチングレ
ギユレータの全体の動作は第１図で説明した従来
のスイツチングレギユレータとほぼ同じである
が、以下には特に相違する点について説明する。
第４図において負荷が急激に重くなる時刻t0より
前の時間ではトランジスタＱ１，Ｑ２は交互に
「オン」することによりパルス幅制御が正しく行
われている。主トランスＴ１のコアの磁束密度Ｂ
も飽和磁束密度±BMに達しない範囲で変化して
おり、第２図の場合と同じである。 The overall operation of the switching regulator according to the embodiment of the present invention shown in FIG. 3 is almost the same as that of the conventional switching regulator explained in FIG. 1, but the differences will be explained below. do.
In FIG. 4, before the time t 0 when the load suddenly becomes heavier, the transistors Q1 and Q2 are alternately turned on, thereby correctly controlling the pulse width. Core magnetic flux density B of main transformer T1
also changes within a range that does not reach the saturation magnetic flux density ±B M , which is the same as in the case of Fig. 2.
さて時刻toで負荷が急激に重くなつた時、誤差
増幅器Ａ２はトランジスタＱ５を「オフ」しP1
点の電圧を低くし、パルス幅変調器４のP2点の
パルス電圧の幅を広くしようとする。しかし時定
数回路５のコンデンサＣ４が放電するのでP1点
の電圧は急激に低くならない。そしてP1点の電
圧が時刻ｔ１１で一定の低いレベルになるまでに
P2点には複数のパルス電圧が発生する。さらに
このP2点のパルス電圧の数に応じて主トランス
Ｔ１の１次巻線Ｌ１１の電流の方向も（＋）方
向、（−）方向といつたように変化する。第４図
では時刻toから時刻ｔ１１の間にこの電流の方向
が１回変つており、主トランスＴ１のコアの磁束
密度Ｂの変化する方向も同じように変る。しかも
時刻ｔ１１までにP2点のパルス電圧の幅は順次
広がつてゆき、P2点のパルス電圧に応動する１
次巻線Ｌ１１の電流によるコアの磁束密度Ｂの変
化も大きくなる。従つて同方向に磁化する時の磁
束密度Ｂの値も順次大きくなる。 Now, when the load suddenly becomes heavier at time to, error amplifier A2 turns off transistor Q5 and P1
An attempt is made to lower the voltage at the point and widen the width of the pulse voltage at point P2 of the pulse width modulator 4. However, since the capacitor C4 of the time constant circuit 5 is discharged, the voltage at the P1 point does not drop suddenly. By the time the voltage at point P1 reaches a certain low level at time t11,
Multiple pulse voltages are generated at point P2. Furthermore, the direction of the current in the primary winding L11 of the main transformer T1 changes between the (+) direction and the (-) direction in accordance with the number of pulse voltages at the P2 point. In FIG. 4, the direction of this current changes once between time to and time t11, and the direction in which the magnetic flux density B of the core of the main transformer T1 changes also changes in the same way. Furthermore, by time t11, the width of the pulse voltage at point P2 gradually expands, and the width of the pulse voltage at point P2 increases.
The change in the magnetic flux density B of the core due to the current in the next winding L11 also increases. Therefore, the value of the magnetic flux density B when magnetized in the same direction also increases sequentially.
第４図では例えば（−）方向の磁束密度ＢがＢ
１，Ｂ２と順次大きくなつている。このことは次
に生ずる反対方向の磁束密度Ｂの最大磁束密度＋
BM−BM間において許容される変化量が大きくな
ることと等価である。 In Figure 4, for example, the magnetic flux density B in the (-) direction is B
1, B2 and so on. This means that the maximum magnetic flux density of the magnetic flux density B in the opposite direction that occurs next +
This is equivalent to increasing the amount of change allowed between B M - B M.
よつて順次広がつてきたP2点のパルス電圧の
幅が最も大きな幅のパルス電圧を生じ始める時刻
ｔ１１では、磁束密度Ｂの許容される変化量も
P2点のパルス幅が広がり始めて最も大きくなり、
第２図の時刻ｔ１、時刻ｔ３間と同じ幅のパルス
電圧が時刻ｔ１１、時刻ｔ１２間で生じてもコア
の磁束密度Ｂは最大磁束密度＋BMに容易に達す
ることはない。 Therefore, at time t11, when the width of the pulse voltage at point P2, which has gradually expanded, begins to produce the largest pulse voltage, the permissible amount of change in the magnetic flux density B also increases.
The pulse width at point P2 begins to widen and becomes the largest,
Even if a pulse voltage having the same width as that between time t1 and time t3 in FIG. 2 occurs between time t11 and time t12, the magnetic flux density B of the core does not easily reach the maximum magnetic flux density +B M.
これは第５図の磁化特性において例えば本発明
が磁束密度−B2から（＋）方向に磁化させるの
に対し、第１図のスイツチングレギユレータが磁
束密度−B1程度から（＋）方向に磁化させる場
合を対比させれば明らかである。 This is because in the magnetization characteristics shown in Fig. 5, for example, the present invention magnetizes from a magnetic flux density of -B2 in the (+) direction, whereas the switching regulator shown in Fig. 1 magnetizes from a magnetic flux density of about -B1 in the (+) direction. This becomes clear if we compare the case of magnetization.
なお負荷が軽くなる場合はトランジスタＱ５が
「オン」し定電圧VCCにより定電流回路６の電流
に比較して大きなコレクタ電流が流れ、P1点の
電圧は速やかに上昇し応答が遅れることはない。 Note that when the load becomes lighter, transistor Q5 turns on and a collector current that is larger than the current of constant current circuit 6 flows due to constant voltage V CC , and the voltage at point P1 rises quickly and there is no delay in response. .
以上述べたように本発明のスイツチングレギユ
レータは、時定数回路を負荷とするエミツタホロ
ワ回路に誤差増幅器の出力側を接続してあり、さ
らにエミツタホロワ回路と時定数回路の接続点お
よびアース間には定電流回路を接続してある。そ
してパルス幅変調器の入力側には、検出出力電圧
値に応じた入力が加えられる。また、負荷が急激
に重くなつた場合には、主トランスの１次側に接
続した１対のトランジスタのベース入力のパルス
幅を増大させるためのパルス幅変調器の前記入力
の変化が遅延される。 As described above, in the switching regulator of the present invention, the output side of the error amplifier is connected to the emitter follower circuit whose load is the time constant circuit, and the output side of the error amplifier is connected between the connection point of the emitter follower circuit and the time constant circuit and the ground. is connected to a constant current circuit. An input corresponding to the detected output voltage value is applied to the input side of the pulse width modulator. Additionally, when the load suddenly becomes heavy, the change in the input of the pulse width modulator for increasing the pulse width of the base input of a pair of transistors connected to the primary side of the main transformer is delayed. .
このことにより、負荷が急激に重くなつて、主
トランスの１次巻線に大きな電流が流れる時、そ
の電流による磁化とは反対方向のコアの磁化を大
きくしてコアの飽和によるスイツチングトランジ
スタの破損を防ぐことができる。 As a result, when the load suddenly becomes heavy and a large current flows through the primary winding of the main transformer, the magnetization of the core is increased in the opposite direction to the magnetization caused by the current, causing the switching transistor to become saturated due to core saturation. Damage can be prevented.
しかも負荷が急激に軽くなる場合には、ベース
入力のパルス幅を縮めるためのパルス幅変調器の
入力の変化は、負荷が重くなる場合のように遅延
されない。従つて、その場合に整流、平滑回路の
平滑コンデンサの電圧が上昇して破損したり、出
力端子に過電圧が生ずることの不都合が妨がれ
る。 Moreover, when the load suddenly becomes lighter, the change in the input of the pulse width modulator to reduce the pulse width of the base input is not delayed as it would be when the load becomes heavier. Therefore, in this case, the voltage of the smoothing capacitor of the rectifier/smoothing circuit increases and is damaged, and the problem of overvoltage occurring at the output terminal is prevented.
このように本発明のスイツチングレギユレータ
は、負荷が急激に重くなる場合の技術問題を解決
しているが、そのことによつて逆の場合、つまり
負荷が急激に軽くなる場合の不都合は何ら存在し
ない。このような本発明は実施例のようなハーフ
ブリツジ形のものに限定されるものではなく、１
対のスイツチングトランジスタを交互に「オン」
させる他の種々の方式のスイツチングレギユレー
タ、例えばフルブリツジ形やプツシユプル形のス
イツチングレギユレータに応用することができ
る。そして主トランスのコアの１方向だけの磁化
を用いる１石式のスイツチングレギユレータに比
較して、主トランスのコアの最大磁束密度を小さ
くし、その形状も小さくできるという、この種の
スイツチングレギユレータの利点を確実に活かす
ことができる。又実施例ではパルス幅変調器４の
論理、誤差増幅器Ａ２の論理は一例を示したにす
ぎない。上記の説明は誤差増幅器Ａ２の電圧の減
少変化がP2点のパルス電圧の幅を増大させると
共に１対のトランジスタＱ１，Ｑ２にベース入力
のパルス幅を増大させる場合について行なつた
が、逆論理の構成で誤差増幅器Ａ２の電圧の増加
変化がパルス幅を増大させる場合には誤差増幅器
Ａ２の電圧の増加に対して変化を遅延させること
によつて同様に構成することができる。 In this way, the switching regulator of the present invention solves the technical problem when the load suddenly becomes heavier, but it also solves the problem in the opposite case, that is, when the load suddenly becomes lighter. Nothing exists. The present invention is not limited to the half-bridge type as in the embodiment, but
Turning on pairs of switching transistors alternately
The present invention can be applied to various other types of switching regulators, such as full bridge type and push-pull type switching regulators. In addition, compared to a single-stone switching regulator that uses magnetization in only one direction of the main transformer core, this type of switch allows the maximum magnetic flux density of the main transformer core to be lower and its shape to be smaller. You can certainly take advantage of the advantages of the angular regulator. Furthermore, in the embodiment, the logic of the pulse width modulator 4 and the logic of the error amplifier A2 are merely examples. The above explanation was given for the case where a decreasing change in the voltage of the error amplifier A2 increases the width of the pulse voltage at the point P2 and also increases the pulse width of the base input to the pair of transistors Q1 and Q2. In a case where an increasing change in the voltage of the error amplifier A2 increases the pulse width, a similar configuration can be made by delaying the change with respect to the increase in the voltage of the error amplifier A2.
第１図は従来のスイツチングレギユレータを示
す回路図であり、第２図は第１図のスイツチング
レギユレータの動作波形図であり、第３図は本発
明のスイツチングレギユレータの一実施例を示す
回路図であり、第４図は第３図の実施例のスイツ
チングレギユレータの動作波形図であり、第５図
は主トランスのコアの磁化特性を示す図であり、
第６図は第３図の１部回路図である。
Ａ１１，Ａ１２，Ａ１，Ａ２：誤差増幅器、
４：パルス幅変調器、５：時定数回路、６：定電
流回路、Ｑ１，Ｑ２：スイツチングトランジス
タ、Ｑ５：トランジスタ。
FIG. 1 is a circuit diagram showing a conventional switching regulator, FIG. 2 is an operating waveform diagram of the switching regulator of FIG. 1, and FIG. 3 is a circuit diagram of the switching regulator of the present invention. 4 is a circuit diagram showing one embodiment, FIG. 4 is an operating waveform diagram of the switching regulator of the embodiment shown in FIG. 3, and FIG. 5 is a diagram showing the magnetization characteristics of the core of the main transformer. ,
FIG. 6 is a partial circuit diagram of FIG. 3. A11, A12, A1, A2: error amplifier,
4: Pulse width modulator, 5: Time constant circuit, 6: Constant current circuit, Q1, Q2: Switching transistor, Q5: Transistor.
Claims (1)
り交互に「オン」して主トランスの１次側に交互
に反対方向の電流を流し、その２次誘起電圧を整
流して直流出力を得ると共に、検出出力電圧値に
応じてパルス幅変調器により前記トランジスタの
ベース入力のパルス幅を制御して出力電圧が一定
になるようにしたスイツチングレギユレータにお
いて、パルス幅変調器の入力側には、コンデンサ
と抵抗を含む時定数回路、該時定数回路を負荷と
するエミツタホロワ回路が接続され、該エミツタ
ホロワ回路には検出出力電圧値に応じた誤差信号
を得る誤差増幅器が接続され、さらにエミツタホ
ロワ回路と時定数回路との接続点およびアース間
に定電流回路が接続されており、前記ベース入力
のパルス幅を増大させる場合には、パルス幅変調
器に加わる入力の変化が遅延されるようにしたこ
とを特徴とするスイツチングレギユレータ。1 A pair of transistors are alternately turned on by their respective base inputs to alternately flow current in opposite directions to the primary side of the main transformer, and the secondary induced voltage is rectified to obtain a DC output and detected. In a switching regulator, a pulse width modulator controls the pulse width of the base input of the transistor according to the output voltage value so that the output voltage is constant, and a capacitor is connected to the input side of the pulse width modulator. and a time constant circuit including a resistor, an emitter follower circuit whose load is the time constant circuit, an error amplifier that obtains an error signal according to the detected output voltage value is connected to the emitter follower circuit, and an emitter follower circuit and a time constant. A constant current circuit is connected between a connection point with the circuit and ground, and when the pulse width of the base input is increased, a change in the input applied to the pulse width modulator is delayed. Switching regulator.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56064789A JPS57193819A (en) | 1981-04-28 | 1981-04-28 | Switching regulator |
| US06/371,264 US4449175A (en) | 1981-04-28 | 1982-04-23 | Switching regulator |
| CA000401726A CA1180382A (en) | 1981-04-28 | 1982-04-27 | Feedback circuit for switching regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56064789A JPS57193819A (en) | 1981-04-28 | 1981-04-28 | Switching regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57193819A JPS57193819A (en) | 1982-11-29 |
| JPS6353792B2 true JPS6353792B2 (en) | 1988-10-25 |
Family
ID=13268344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56064789A Granted JPS57193819A (en) | 1981-04-28 | 1981-04-28 | Switching regulator |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4449175A (en) |
| JP (1) | JPS57193819A (en) |
| CA (1) | CA1180382A (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4559590A (en) * | 1983-03-24 | 1985-12-17 | Varian Associates, Inc. | Regulated DC to DC converter |
| JPS6022471A (en) * | 1983-07-15 | 1985-02-04 | Kyosan Electric Mfg Co Ltd | Switching regulator |
| JPS6077289U (en) * | 1983-11-01 | 1985-05-30 | 株式会社明電舎 | Switching type DC power supply |
| JPS61161698A (en) * | 1985-01-09 | 1986-07-22 | Hitachi Medical Corp | Inverter type x-ray plant |
| US5252905A (en) * | 1985-12-23 | 1993-10-12 | York International Corporation | Driving system for single phase A-C induction motor |
| US4860185A (en) * | 1987-08-21 | 1989-08-22 | Electronic Research Group, Inc. | Integrated uninterruptible power supply for personal computers |
| US4945467A (en) * | 1988-02-26 | 1990-07-31 | Black & Decker Inc. | Multiple-mode voltage converter |
| US4891746A (en) * | 1988-12-05 | 1990-01-02 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of optimizing the efficiency of a high frequency zero voltage switching resonant power inverter for extended line and load range |
| US5012401A (en) * | 1990-03-19 | 1991-04-30 | Allied-Signal Inc. | Switching power supply with foldback current limiting |
| KR920009016A (en) * | 1990-10-31 | 1992-05-28 | 강진구 | Current sensing circuit using pulse transformer |
| US6020436A (en) * | 1993-03-09 | 2000-02-01 | The Chromaline Corporation | Photosensitive resin composition |
| US7269034B2 (en) | 1997-01-24 | 2007-09-11 | Synqor, Inc. | High efficiency power converter |
| US6246207B1 (en) | 1998-06-26 | 2001-06-12 | A. O. Smith Corporation | Method and apparatus for controlling an induction motor |
| US7016203B2 (en) * | 2003-01-24 | 2006-03-21 | Virginia Tech Intellectual Properties, Inc. | Self-driven circuit for synchronous rectifier DC/DC converter |
| US6819574B2 (en) * | 2003-01-24 | 2004-11-16 | Virginia Tech Intellectual Properties, Inc. | Self-driven circuit for synchronous rectifier DC/DC converter |
| DE102006045970A1 (en) * | 2006-09-27 | 2008-04-03 | Robert Bosch Gmbh | Method and device for operating a transformer |
| US10199950B1 (en) | 2013-07-02 | 2019-02-05 | Vlt, Inc. | Power distribution architecture with series-connected bus converter |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4030019A (en) * | 1975-11-10 | 1977-06-14 | General Electric Company | Static inverter control circuit |
| US4063306A (en) * | 1976-09-24 | 1977-12-13 | General Electric Company | Actively switched damping circuit |
| US4148097A (en) * | 1977-07-01 | 1979-04-03 | Bell Telephone Laboratories, Incorporated | DC to DC converter utilizing current control for voltage regulation |
| US4150424A (en) * | 1978-04-04 | 1979-04-17 | International Telephone And Telegraph Corporation | Dynamic current balancing for power converters |
| US4270164A (en) * | 1979-02-28 | 1981-05-26 | Contraves Goerz Corporation | Short circuit protection for switching type power processors |
| US4344124A (en) * | 1979-03-22 | 1982-08-10 | Motorola, Inc. | Start-up timer for a switching power supply |
| US4371824A (en) * | 1979-07-05 | 1983-02-01 | Eaton Corporation | Base drive and overlap protection circuit |
-
1981
- 1981-04-28 JP JP56064789A patent/JPS57193819A/en active Granted
-
1982
- 1982-04-23 US US06/371,264 patent/US4449175A/en not_active Expired - Fee Related
- 1982-04-27 CA CA000401726A patent/CA1180382A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4449175A (en) | 1984-05-15 |
| JPS57193819A (en) | 1982-11-29 |
| CA1180382A (en) | 1985-01-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6353792B2 (en) | ||
| US3935526A (en) | DC-to-DC converter | |
| US4736284A (en) | Switching power supply circuit including forward converter | |
| US4870554A (en) | Active snubber forward converter | |
| US3573605A (en) | Closed loop ferroresonant regulator | |
| US4417153A (en) | High frequency switching circuit | |
| US4209731A (en) | Magnetic switching regulator for a deflection circuit | |
| JPH0315423B2 (en) | ||
| US4603307A (en) | Inverter using current steering saturable inductors or diodes | |
| JPS626871Y2 (en) | ||
| JPS58148680A (en) | Self-excited oscillator | |
| JPH0635661Y2 (en) | Switching regulator | |
| JP2554158B2 (en) | Mag amplifier circuit | |
| JPH0231913Y2 (en) | ||
| JPS6127939B2 (en) | ||
| JPS5932361A (en) | Power source circuit | |
| JPS6232702B2 (en) | ||
| JPS61132076A (en) | Power source circuit | |
| JPH0667208B2 (en) | Power supply circuit | |
| JPS642963B2 (en) | ||
| JPS6057199B2 (en) | discharge lamp lighting device | |
| JPS6020488A (en) | Induction heating cooking device | |
| JPH0318431B2 (en) | ||
| JPH0138596B2 (en) | ||
| JPH0313826B2 (en) |