JPS6353666A - Peripheral controller for computer system - Google Patents

Abstract

PURPOSE:To maintain ability to offer information services as a whole system by evading a communication error between a peripheral controller and a host computer even if a line switch is operated in any condition. CONSTITUTION:It is assumed that the line switch 31 is changed over before a logical connection with the host computer is established. A processor 60 reads in a switch register 33, knows that the switch 31 is switched off, and impresses a disable signal DA on a receiver controller 25 and a driver controller 26. After that, the processor 60 receives an approval signal AK returned from the controllers 25 and 26. In this case, when the line switch 31 is judged to be switched off, an initial sequence does not start. Therefore an address coincidence FF24 is also reset, and receivers 11 and 13, and drivers 12 and 14 are inoperably controlled. The processor 60 diagnoses its own station as the FF24 is reset.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is electrically connected to an input/output channel of a host computer as a peripheral device, and communicates various necessary information with the host computer through the input/output channel. The present invention relates to a peripheral control device for a computer system that performs input/output services for various data between an input/output device of a terminal under control and a host computer based on exchange.

[Conventional technology]

Generally, such a large-scale computer system consists of a host computer that centrally manages the entire system, and one or more peripheral control devices that are connected as so-called peripheral devices to each of the host computer's multiple input/output channels. And one more for each of these peripheral control devices.
The host computer is configured with input/output devices such as plotters, printers, or keyboards that are connected in plural (generally in parallel), and if we focus on one of the input/output channels of the host computer, there is a A time-sharing logical connection between an input/output channel and each of the peripheral control devices (input/output control devices) connected to it (input/output control devices) using these control devices as a unit (actual sequence between the input/output channels) A connection that is in an executed state - a connection that is electrically connected to an output channel but is in a waiting state is called a "physical connection" or "physical connection" and is called a "logical connection" or "physical connection". Various information services are realized between the input/output device of the terminal further connected to the peripheral control device in the logical connection state and the above-mentioned host computer based on the "logical connection"). It has become.

Here, a brief explanation will be given of the sequence operations performed between one input/output channel of the host computer and the relevant peripheral control device in such a system.

For example, a request is made to the host computer to cause the output device connected to the first peripheral control device connected to the input/output channel to output required data. An outline of the sequence operations performed between the input/output channel and the first peripheral control device in this case will be listed below.

(2) The host computer sends a predetermined address signal for selecting and designating the first peripheral control device through the input/output channel.

■The first peripheral control device that recognized the address signal transmits the address signal of its own station to the corresponding input/output channel of the host computer in order to notify the host computer that its own station has been selected. Reply -3 = I believe.

(2) After confirming this, the input/output channel continues to send a command requesting communication with the first peripheral control device.

(2) The first peripheral control device confirms that the output device connected to its own station is ready for processing, and then returns a status indicating that it responds to the command to the same input/output channel.

(2) As a result, the host computer transfers the data desired to be output to the first peripheral control device through the same input/output channel.

(2) The first peripheral control device performs necessary processing on the transferred data in parallel with this data transfer, and sequentially outputs the processed data to the output device.

■When all the output processing for the transfer data to the output device is completed (the output operation of the output device is finished), the first peripheral control device sends an end status indicating that the output processing has been completed. Reply to input/output channels.

-ζ - 1 4 - ■Thus, the host computer determines that the original request for the transfer data has been achieved.

In addition, in the above sequence (■), the host computer was unable to transfer all the data that it initially wanted to output at once due to communication with other peripheral control devices connected to the same person's output channel. In this case, the above ■
After the sequence 1 to 2, the sequence 1 to 2 is repeated again to process the remaining data. This is the same even if data remains after that. Incidentally, among the sequences (1) to (2) above, the sequences (2) to (2) are referred to as "initial sequences," the sequences (2) to (2) are referred to as "data transfer sequences," and the sequences (2) to (2) are referred to as "end sequences."

By the way, in such computers, each of the peripheral control devices mentioned above usually has an online/offline switch (
A switch means called a line switch (hereinafter simply referred to as a line switch) is provided, and the line switch is turned on/off in advance.
Depending on the off state, the above-mentioned logical connection possible state/physical connection state between each peripheral control device and its corresponding input/output channel is switched. Therefore, the two consecutive sequence operations, especially the operations ① to ②, are actually achieved only when this line switch is on, that is, in a ``state where logical connection is possible''. A peripheral control device whose line sketch is off, that is, in a "physically connected state", exclusively performs its own diagnostic processing and waits.

[Problem that the invention seeks to solve]

If the above-mentioned line switch is operated properly, no particular problem will occur, but for example, if there is a logical connection with the above input/output channel and there is a double "initial sequence" between the same input/output channel. If this line switch is inadvertently turned off in the peripheral control device that is executing the process, the sequence will stop midway and a so-called communication error will occur. on the other hand,
On the input/output channel side, the logical connection obligation with the peripheral control device that is in the logically connected state is canceled only when the above-mentioned termination status is returned from the peripheral control device, so if such a communication error occurs. In this case, the logical connection obligation of this input/output channel to the peripheral control device continues to be maintained, and even the information service of the computer system itself may be lost.

[Means and effects for solving the problem] In the present invention, an address signal is accepted from the input/output channel on the condition that the line switch is turned on, and the received address signal indicates the own station. For peripheral control devices that have confirmed that the line switch
Regardless of the off state, the above-mentioned sequence up to the completion report (replying the completion status) will be executed once, and after this sequence is executed, the state setting at that point by the same line switch will be followed. do.

This avoids at least two consecutive communication errors between input/output channels and peripheral control devices that are in a logically connected state, and the information service of the entire system is interrupted for a long time. Things like that will no longer be the case.

〔Example〕

FIG. 1 shows an embodiment of a peripheral control device for a computer system according to the present invention.

As explained earlier, the computer system targeted here includes a host computer that centrally manages the entire system and provides various information services to various input/output devices through peripheral control devices, which will be explained below. have. Usually, one or more peripheral control devices are connected to each of the one or more input/output channels of the host computer via appropriate communication lines in a so-called master station-slave station relationship, and these peripheral control devices are One or more input/output devices are connected to each of the devices via appropriate communication lines to configure the computer system.

Now, the peripheral control device according to the embodiment shown in FIG. After the above-mentioned "initial sequence j" with the channel, the drawing data transferred from the same input/output channel is subjected to processing such as rask conversion, and then outputted to an output device (not shown) such as a plotter. The configuration and functions will be described in detail below with reference to FIG. 1.

As shown in the figure, this embodiment peripheral control device has a BUS
Address signal AD, command CMD, data (
Drawing data) Receiver 11, B for importing DAT
A driver 12, TAGou, which is connected to the USIn line and is used to send address signals AD, data DAT, and status STS from its own station to the same host computer.
Connected to the t line from the host computer"2 BU
In a broad sense, the data transferred via the SOut line is 1. address signal AD, command CMD.

A receiver 13 for receiving a signal (data) TAGI transferred from the same host computer to indicate the type of data DTA;
In a broad sense, the data connected to the BUS I n line and sent from the own station via the BUS I n line are two address signals AD, data DTA, and status ST.
A driver 14 sends a signal (data) TAG2 indicating the type of S to the host computer, and takes in a select signal SL (a signal indicating that the logical connection is approved) transferred from the host computer. a receiver 15 for transmitting the select signal SL, a driver 16 for sending out the select signal SL when it is for another station, and a driver 16 for temporarily storing the address signal AD taken in through the receiver 11 during the above-mentioned [initial sequence]. an address register 21 for setting the address, and an address setter 22 for presetting the address signal of the own station.
, a comparator 23 that compares these fetched address signals AD with a preset address signal of its own station and outputs an address match signal ADG if they match, and an address set by this address match signal ADG. The matching F/F (flip-flop) 24 activates/inactivates the receivers 11 and 13 based on the set output of this address matching F/F 24 or an enable/disable signal ENI/DA applied from a processor (60) described later. A receiver controller 25 that controls activation, a driver controller 26 that also controls activation/inactivity of the drivers 12 and 14 based on these set outputs or enable/disable signals ENI/DA, and an address matching F/F 24.
When there is a set output, the output end S1 is selected and the select signal SL taken in by the receiver 15 is transferred to the processor to be described later, and when there is no set output, the output end S2 is selected and this taken in Select signal SL
Select controller 2 that transfers the
7. Home station host! - The above-mentioned line switch 31 for switching the connection state to the computer (personnel channel) to a state where logical connection is possible/a state where physical connection is possible;
A well-known chattering prevention circuit 32 for preventing chattering of the switch 31, a switch register 33 for temporarily storing a signal 0N10FF indicating the on/off state of the switch 31, and 1. The data DTA taken in through the receiver 11 is stored sequentially, for example, in segment units that match the raster data (the input/output control method here is assumed to be the MA method, which is common in such computer systems, and will be described later). An input buffer 40 for storing such data (assuming that such data storage is started just by being activated by hardware by the processor), and raster data that is sequentially read from the input buffer 40 and subjected to rask conversion by a processor described later is stored as a frame. a frame buffer 50 for further temporary storage in units; and 1. Based on the contents stored in the switch register 33, when the same contents indicate that the line switch 31 is "on", the above 1.
Applying an enable signal ENI to the receiver controller 25 and the driver controller 26, and applying a disable signal DA to the receiver controller 25 and the driver controller 26 when the same content indicates that the line switch 31 is "off". Receiver 11.13
The enable/disable signal EN/DA and the reset signal RST basically control the active/inactive mode of the driver 12. data DTA that is taken in from the host computer via the receiver 11 on the condition that the logical connection with the host computer (input/output channel) is maintained.
2. Storage in the data buffer 40, sequential reading of the stored data DTA, Rask conversion processing to read data, etc., and output of the processed data to an output device (not shown) via the frame buffer 50. sequential output of,
Return of the completion status (Status 5TS), which is enforced on the condition that all the output processing for one section of data transferred from the host computer to the local station has been completed (
Each of the peripheral controllers includes a processor 60 programmed to collectively execute various controls required for the respective peripheral controllers (through drivers 12 and 14), etc.

Note that the comparator 23 is connected to the processor 6 described above.
The address matching F/F 24 is controlled by the enable/disable signal EN/DA from 0 to become active only when the data in a broad sense taken into the receiver 11 is the address signal AD. , it is assumed that when the above-mentioned end status (status 5TS) is returned, it is reset by the reset signal RST from the processor 60. Furthermore, the receiver controller 25 and the driver controller 26 basically activate the receivers and drivers to be controlled by the enable signal ENI from the processor 60 mentioned above, and activate the receiver and driver to be controlled by the enable signal ENI from the processor 60, and by the disable signal D from the processor 60.
A makes the receiver and driver inactive, and operates to send back to the processor 6o an approval signal AK indicating that the application of the enable signal ENI and the disable signal DA is approved. However, regarding active control, the set output of the address matching F/F 24 is also referred to and is given priority over the disable signal AD. Therefore, even if the disable signal DA is applied from the processor 6o, this When address match F/F 24 is set and this set output is applied (including when these are applied at the same time), this set output is prioritized and the receivers and drivers to be controlled are activated respectively. Suppose we want to control it like this. Moreover, even in this case, the acknowledgment signal AK is returned in response to the application of the disable signal DA. However, when the enable signal ENI is applied from the processor 60, two consecutive active controls are executed regardless of the presence or absence of this set output. In FIG. 1-15, in consideration of these functions of the receiver controller 25 and driver controller 26, the enable signal applied to them from the processor 60 is denoted by rENIJ to mean the first enable signal. The set output of the address matching F/F 24, which is applied to the address matching F/F 24, is shown with rEN2J attached thereto to mean a second enable signal.

Next, refer to the flowchart in Figure 2 at the same time.''-2
The main operations of the peripheral control device of this embodiment, centering on the operations of the processor 60, will be described in detail.

Note that the outline of the operation of this computer system as a whole is as described above, and a redundant explanation will be omitted here.

As mentioned above, if the line switch 31 is set to "off" in advance, only diagnostic processing of the own station is performed and no communication with the host computer is performed, so here, "2" The operation will be explained on the premise that the line switch 31 is in the "on" state at least initially, and is in a state where the above-mentioned "initial sequence" can be started.

In such a case, in the peripheral control device of this embodiment, (1) the line switch 31 is maintained in the "on"state;

(2) When the line switch 31 is turned "off" before the start of the "initial sequence", that is, before the logical connection with the host computer is established.

(3) After the start of the [Initial Sequence], the line switch 31 is turned off while the logical connection with the host computer is established.

The following operations are performed in accordance with three types of operating conditions that may actually occur.

First, in the case (1) above, the processor 60 is initialized appropriately (step S2 in FIG. 2), then reads out the contents of the switch register 33 and sets the line switch 31 to "
In step S2 in FIG. 2), the receiver controller 25 and the driver controller 2
The enable source signal ENI is applied to 6 (step S3 in FIG. 2).

As a result, the receiver controller 25 and the driver controller 26 activate the receivers 11, 13 and drivers 12, 14, respectively, to be controlled, and transmit the approval signal AK to the processor 60. Processor 6 that received this approval signal AK
0 (step S4 in FIG. 2) waits for a communication request from the host computer, and when there is a communication request, it drives the comparator 23 and confirms that the address signal AD matches its own. After that (at this point, the address matching F/F 24 is set), on the condition that a channel command (communication command) from the same host computer is set in a register (not shown) inside the processor 60 (step 2 in FIG. S5) The address matching F/F 24 is reset by executing necessary processes such as the above-mentioned command processing, data processing, and completion report (step S6 in FIG. 2). And after that, double step S2
→S3→S4→S5→S2 are repeated and the process waits until there is another communication request from the host computer.

In the case of (2) above, the processor 60, after being appropriately initialized (step Sl in FIG. 2), reads the contents of the switch register 33 and sets the line switch 31 to "
It is determined that the state is "off" (step S2 in FIG. 2),
A disable signal DA is applied to the receiver controller 25 and the driver controller 26 (step S7 in FIG.
Figure step S8). In the case of condition (2), the "initial sequence" has not started at the time it is determined that the line switch 31 is in the "off" state, and therefore the address matching F/F 24 is also reset. state (comparator 23 itself is not driven). For this reason, receiver 11.13 and driver 12.14
The processor 60 is inactively controlled by the controllers 25 and 26, and the processor 60 determines that the address matching F/F 24 is not set (step S9 in FIG. 2). This will be executed (
Figure 2 Step 5IO). After that, if it is confirmed that the in-switch 31 described in - is turned on, the operation shifts to the case (1) described above.

In the case of (3), the processor 60, after being appropriately initialized (step Sl in FIG. 2), reads the contents of the switch register 33 and sets the line switch 31 to
In step S2 of FIG. 2, it is determined that the
), the disable signal DA is applied to the receiver controller 25 and the driver controller 26 (step S7 in FIG. 2), and then these controllers 2
Accept the acknowledgment signals AK returned from 5 and 26 (
FIG. 2 step S8). However, in the case of condition (3), the "initial sequence" has already started when it is determined that the line switch 31 described in "1" is in the "off" state, and therefore The address matching F/F 24 has also been set (the "initial sequence" has been executed under this condition). Therefore, from the processor 60
Although the disable signal DA was sent to the controllers 25 and 26 as in two series, the receiver 11.
13 and drivers 12 and 14 are actively controlled by the same controllers 25 and 26 (more precisely, they are maintained in an active state), and the processor 60, which has determined that the address matching F/F 24 is set, (Step S9 in FIG. 2), on the condition that a channel command (communication command) from the host computer is set in a register (not shown) inside the processor 60 as described above (Step S5 in FIG. 2), command processing, data processing, and completion report. After performing the necessary processing such as "2 Address Match F/
F24 is reset (step S6 in FIG. 2). After that, while it is confirmed that the line switch 31 in item 1 is ``off'', the operation in case (2) above is executed, and when it is confirmed that the switch 31 is ``on'', Then, the operation changes to the case (1) above.

In this way, according to the peripheral control device of this embodiment, no matter what conditions the line switch 31 is switched, communication errors between the peripheral control device and the host computer can be effectively avoided.

Note that the configuration shown in FIG. 1 is only an example, and the address signal from the host computer (input/output channel) is accepted on the condition that the input signal described in 1 is turned on. Once it is confirmed that the received address signal indicates the own station and a logical connection is established with the same host computer, the process until the end report is completed regardless of the subsequent on/off state of this line switch. Any other configuration may be used as long as it satisfies the minimum function of executing a series of sequences once and then following the current state setting by the same line switch after the execution of these sequences.

Further, the peripheral control device of the present invention is a computer in which a logical connection possible state/physical connection state between the peripheral control device and a host computer is switched in accordance with turning on/off of the above-mentioned line switch in advance. It can be applied to any other system as long as it is a system.

〔Effect of the invention〕

As explained above, according to the present invention, no matter what conditions the line switch is operated, communication errors between the peripheral control device and the host computer can be avoided and the information service of the entire system can be improved. ability can be maintained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a peripheral control device for a computer system according to the present invention, and FIG. 2 is a flowchart showing an example of the operation of the peripheral control device of the embodiment. 11.13.15...Receiver, 12,14°16.
...Driver, 21...Address register, 22...
・Address setter, 23... Comparator, 24...
・Address matching F/F, 25... Receiver controller - 23 = U, 26... Driver controller, 27... Select controller, 31... Line switch, 32...
...Chattering prevention circuit, 33... Switch register, 40... Input buffer, 50... Frame buffer, 60... Processor.

Claims (1)

[Scope of Claims] An input/output channel of a host computer and an appropriate output device such as a plotter are electrically connected via appropriate communication lines, so that logical connection with the input/output channel is possible. /On condition that the online/offline switch for switching and setting the physical connection state specifies the logical connection possible state, accepts the address signal sent from the same input/output channel and indicates the own station. When it is confirmed that the address signal indicates the own station, a logical connection with the input/output channel is established and processing related to commands and data transferred from the input/output channel is executed. At the same time, in the peripheral control device of the computer system, which sends a completion report to the input/output channel when the processing is completed and releases the logical connection obligation of the input/output channel to its own station, the input/output is performed by confirming the address signal. After the logical connection with the output channel is once established, a series of processes up to the completion report is executed regardless of the status setting by the online/offline switch, and then the status setting by the online/offline switch is followed. A peripheral control device for a computer system, characterized in that: