JPS6352488A - Manufacture of avalanche photo diode - Google Patents
Manufacture of avalanche photo diodeInfo
- Publication number
- JPS6352488A JPS6352488A JP61195217A JP19521786A JPS6352488A JP S6352488 A JPS6352488 A JP S6352488A JP 61195217 A JP61195217 A JP 61195217A JP 19521786 A JP19521786 A JP 19521786A JP S6352488 A JPS6352488 A JP S6352488A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- inp
- providing
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000031700 light absorption Effects 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000002994 raw material Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- PSCMQHVBLHHWTO-UHFFFAOYSA-K indium(iii) chloride Chemical compound Cl[In](Cl)Cl PSCMQHVBLHHWTO-UHFFFAOYSA-K 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 35
- 239000013078 crystal Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野〕
この発明は長波長帯の受光素子に係シ、特にアバランシ
ェフォトダイオードの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a light receiving element in a long wavelength band, and particularly to a method for manufacturing an avalanche photodiode.
（従来の技術）
ｐ−ｎ接合に逆バイアスを印加し、光によって生じたキ
ャリアを雪崩増倍させて用いる所謂アバランシェフォト
ダイオード（ＡＰＤ）には高速応答、内部増幅作用、高
量子効率等の優れた特徴がある。(Prior art) The so-called avalanche photodiode (APD), which applies a reverse bias to the p-n junction and avalanches multiplies carriers generated by light, has advantages such as high-speed response, internal amplification, and high quantum efficiency. It has some characteristics.
特にＩｎＰ系材料を用いて光吸収層と′電流増倍層を独
立にもつＡＰＤは長波長帯光伝送システムのキーコンポ
ーネントとして、近年さかんに研究開発が進められてい
る。In particular, APDs, which are made of InP-based materials and have independent light absorption layers and current multiplication layers, have been actively researched and developed in recent years as key components of long wavelength band optical transmission systems.
この穆のＡＰＤにおいて＾あ電界を印加した除に発生す
る電界集中による局所ブレークダウン全防ぎ、又、動作
電圧を下げる為に、高濃度のｎ型埋め込み層を受光領域
内に設ける工夫がこれまでになされている。In this APD, in order to completely prevent local breakdown due to electric field concentration that occurs when an electric field is applied, and to lower the operating voltage, it has been devised to provide a highly concentrated n-type buried layer within the light receiving area. is being done.
従来は、この高儂度の埋め込み層をシリコン（Ｓｉ）セ
レン（Ｓ ｅ ） 等にイオン注入する憂により形成し
ていた。しかし、イオン注入を行なう事によって結晶は
損傷を強く受け、イオン注入後の熱処理によっても、結
晶性の回復は、不充分であった。従ってイオン注入を行
った種晶層上へ結晶成長全行なっても良好な結晶が得ら
れなかった。Conventionally, this high-temperature buried layer has been formed by ion implantation into silicon (Si), selenium (S e ), or the like. However, the crystal was severely damaged by the ion implantation, and even with heat treatment after the ion implantation, recovery of crystallinity was insufficient. Therefore, even if crystal growth was performed on the seed crystal layer into which ions were implanted, no good crystal could be obtained.
１檀品性の悪い層中にｐ−ｎ接合を設けると、接合部に
印加される高電界のため、ＡＰＤの破壊が多発しＡＰＤ
製造上の障害となっていた。1. If a p-n junction is provided in a layer with poor quality, the high electric field applied to the junction will cause frequent destruction of the APD.
This was an obstacle in manufacturing.
（発明が解決しようとする問題点）
ＡＰＤの特性向上のため、イオン注入により、高不純物
ａ間層が作られているが、イオン注入によ）結晶が損傷
しそれが原因と思われる素子の不良が多発し九、これを
解決するｔめに、本発明は結晶性の良い高不純物濃反層
を持ち、特性及び信頼性の良いＡＰＤ金得る事を目的と
する。(Problem to be solved by the invention) In order to improve the characteristics of APD, a highly impurity interlayer is created by ion implantation. In order to solve this problem, the present invention aims to obtain APD gold having a high impurity concentration layer with good crystallinity, and having good characteristics and reliability.
（問題点を解決する九めの手段）
この発明は、形成し九半導体層に凹部を設け、該凹部に
キャリア４度の大きい半導体２１を役ける工程により、
結晶性の良好な埋めこみ、ｉＩｔ得てアバランシェフォ
トダイオードｔａ造するものである。(Ninth Means for Solving the Problems) The present invention provides a recessed portion in the formed semiconductor layer and a semiconductor 21 having a large carrier 4 degree in the recessed portion.
An avalanche photodiode can be fabricated by obtaining an embedment with good crystallinity.
（作用）
イオン注入プロセスを用いて、ｎ＋層’ｉ形成する従来
の方法に比べ１本発明においては結晶性の良いｎ中層が
得られる念め、局部ブレークダウンや、暗電流等が小さ
くなり、素子の特性及び信頼性が向上した。(Function) Compared to the conventional method of forming an n+ layer by using an ion implantation process, the present invention provides an n-middle layer with good crystallinity, which reduces local breakdown, dark current, etc. The characteristics and reliability of the device have improved.
（実施例）
以下本発明を第１図を参照して説明する。第１図は、ア
バランシェフォトダイオードの断面図であり、次に述べ
るように構成した。まず、ｎ型ＩｎＰ基＠１１ 上ＫＩ
ｎＧａＡｓ及びＩｎＧａＡｓＰのｎ型混合層１２ 、１
３ｔ−ＩｎＰに格子整合する様に結晶成長し念、混合層
のキャリア濃度は４刈Ｑ１５Ｃｆｆｌ １として厚さを
それぞれ３μｍ ｓ ０．５μｍとし次。(Example) The present invention will be described below with reference to FIG. FIG. 1 is a sectional view of an avalanche photodiode, which is constructed as described below. First, the n-type InP group @11 upper KI
n-type mixed layer 12, 1 of nGaAs and InGaAsP
In order to grow the crystal so as to lattice-match it to 3t-InP, the carrier concentration of the mixed layer was set to 4, Q15Cffl 1, and the thickness was set to 3 μm and 0.5 μm, respectively.
次に混合層上にキャリア濃度２Ｘ１０’３ｃｍ−”厚さ
ｌ−ｍのｎ −ＩｎＰｎ五層を成長した。Next, five n-InPn layers with a carrier concentration of 2×10'3 cm-'' and a thickness of 1-m were grown on the mixed layer.
次にｎ −ＩｎＰｎ五層の上にマスクを設けて円形状の
選択的エツチングを施こし、深さ０．７μｍの凹部を形
成し九。Next, a mask was provided on the five n-InPn layers, and circular selective etching was performed to form a recess with a depth of 0.7 μm.
凹部を設は九ウェハーに原料温度６７０℃ 基板温度６
２０℃でＩｎＰとＩｎＣｌ５’ｚ原料としてマストラン
スポートを行ない、凹部にＩｎＰ層１５を成長した。こ
の際ｎ型ドーパントとして、Ｓｔ−加え、キャリア濃度
を３ Ｘ １０” ｃｍ−”とした。The concavity was formed on the 9 wafers at a raw material temperature of 670°C and a substrate temperature of 6.
Mass transport was performed using InP and InCl5'z raw materials at 20° C. to grow an InP layer 15 in the recessed portion. At this time, St- was added as an n-type dopant, and the carrier concentration was set to 3 x 10''cm-''.
次にマスクを取り除き、キャリア濃度２Ｘ１０”ｃｍ−
”厚さ２，２μｍのｎ−ＩｎＰ層１６ｔ−成長した。Next, remove the mask and reduce the carrier concentration to 2X10"cm-
``A 16t-n-InP layer with a thickness of 2.2 μm was grown.
次にＩｎＰ層１６にマスクを設けて円形状の選択的拡散
を行なり、拡散は５６０℃２０分間Ｐ圧下でＣｄ元素を
２μｍの深さまで導入しＰ型層１７を形成し比、拡散の
円形パターンは前記凹部１５の円形パターンより大きく
設定した０次に絶縁膜１８ｔｌ−ＣＶ Ｄ （Ｃｈｅｍ
ｉｃａｌ ｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ ）
ｉにより形成し、７１１ｔ極１９を形成して素子を作
成しｔ。Next, a mask is provided on the InP layer 16 to perform selective diffusion in a circular shape, and the diffusion is performed at 560° C. for 20 minutes under P pressure to introduce Cd element to a depth of 2 μm to form a P-type layer 17. The pattern is a zero-order insulating film 18tl-CVD (Chem.
ical vapor deposition)
i, and form the 711t pole 19 to create an element.
発明の第２の実施例
第２図ｔ−参照して他の実施例を説明する。第２図はバ
ララシエフォトダイオードの断面図を示すもので次に述
べるように構成した。！ず ＨｉＭＩｎＰ基板２１上に
、順次ｎ型ＩｎＰ第１層２２゜ｎ型１ｎＧａＡｓ第２層
２３．ｎ型ＩｎＧａＡｓＰ第３層２４．ｎ形１ｎＰ’、
再４層２５ｔ″結晶成長した。各々のキャリア濃度及び
膜厚は、第１１２１はｌ×１０”ｃ＋−’ ＋ １ μ
ｍ 第２層２２は３×１０” ’ ｃｍ−” ＋ ３μ
ｒｒｚＪ ３ ｆ？３２３は４ Ｘ １０” Ｃｍ−３
＋第４鳴２４ｆｌ、ｌ Ｘ Ｉ Ｏ”ｃｍ ｔ １．８
μｍとした。Second Embodiment of the Invention Another embodiment will be described with reference to FIG. FIG. 2 shows a cross-sectional view of a Bararassie photodiode, which was constructed as described below. ! On the HiMInP substrate 21, an n-type InP first layer 22.degree., an n-type 1nGaAs second layer 23. n-type InGaAsP third layer 24. n-type 1nP',
A 4-layer 25t'' crystal was grown again.The carrier concentration and film thickness of each layer were l x 10''c+-' + 1μ for the 1121st layer.
m second layer 22 is 3×10"cm-" + 3μ
rrzJ 3 f? 323 is 4 x 10” Cm-3
+4th sound 24fl, l X I O”cm t 1.8
It was set as μm.
次に第４層上にマスクを設けて、円形状の選択的なエツ
チングを行ない、深さ２μｍの凹部を形成した。Next, a mask was provided on the fourth layer, and circular selective etching was performed to form a recess with a depth of 2 μm.
次に凹部中にキャリア濃度３ ＸＩＯ” ＣＩ！１−”
のＩｎＰ層２６を放長しｔ。Next, the carrier concentration in the recess is 3XIO"CI!1-"
The InP layer 26 of t is elongated.
次にＷ、４層上ＫＩｎＰ、唱２６より大きな円形上のマ
スクを設けて５６０℃１５分間Ｐ圧下でＣｄ元索を１．
５μｍの深さまでＰ耐層２７を形成した。Next, a circular mask larger than W, KInP on the 4th layer, and Sho 26 was provided, and the Cd original cable was heated at 560°C for 15 minutes under P pressure.
The P resistance layer 27 was formed to a depth of 5 μm.
次に、？、縁膜を形成した０次に、絶縁膜２８．電極２
９を形尺して素子を完成した。next,? , an insulating film 28 . Electrode 2
9 was cut to size to complete the element.
本発明はＩｎＰ／ＩｎＵａＡｓ ＡＰＤＫ適用し念とこ
ろ、結晶性の良好な高不純物８′−度部分を得ることが
でき、その上に成長したＩｎＰｆＪについても、イオン
注入を行なった層の上に成長したＩｎＰ層に比べ良好な
結晶性のものが得られた。これにより得られた素子は、
劣下が少なく、高い＠軸性を得られた。又、歩留り率も
向上し、非常に有効であり之。The present invention was applied to InP/InUaAs APDK, and it was possible to obtain a highly impurity 8'-degree part with good crystallinity, and the InPfJ grown on it was also grown on the ion-implanted layer. A layer with better crystallinity than the InP layer was obtained. The device obtained in this way is
Less deterioration and high @axis properties were obtained. In addition, the yield rate is improved, making it very effective.
第１図に、本発明のアバランシェフォトダイオードの製
造方法の第１の芙施例を説明するための構成断面図、第
２図は本発明の第２の実施例を説明する為の構成断面図
である。
１１９２１・ ｎ型ＩｎＰｉ板、１２，２３・ ｆｌｌ
ニジ、ＩｎＧａ ノ＼Ｓ層、 １３．２４−ｎ 型
ＩｎＧａＡｓＰ１０．１４＋１ｔ３．２２ｓ２５・ｎ
型ＩｎＰ、５．１５．２６−・・ｎ＋型ＩｎＰドーピン
グ層、１８．２８・・・絶縁膜、１９．２９・・・電柵
。
代理人 弁理士 則 近 宵 佑
同 竹 花 喜久男FIG. 1 is a cross-sectional view of the structure for explaining the first embodiment of the method for manufacturing an avalanche photodiode of the present invention, and FIG. 2 is a cross-sectional view of the structure for explaining the second embodiment of the present invention. It is. 11921・n-type InPi board, 12,23・fl
Niji, InGa＼S layer, 13.24-n type InGaAsP10.14+1t3.22s25・n
Type InP, 5.15.26-... n+ type InP doping layer, 18.28... Insulating film, 19.29... Electric fence. Agent Patent Attorney Nori Yudo Chikayo Kikuo Takehana
Claims (3)
する第１導電型の第１の半導体層を設ける工程と、該第
１の半導体層に接して該第１の半導体層より禁制帯幅が
大きい第１導電型の第２の半導体層を設ける工程と、該
第２の半導体層に接して該第２の半導体層以上に禁制帯
幅が大きい第１導電型の第３の半導体層を設ける工程と
、選択的に該第２の半導体層もしくは該第３の半導体層
もしくは該第３の半導体層より該第２の半導体層に至る
凹部を設ける工程と、該凹部に第１導電型で、該第３の
半導体層よりキャリア濃度が大きい第４の半導体層を設
ける工程を少なくとも含むアバランシェフォトダイオー
ドの製造方法。(1) A step of providing a first semiconductor layer of a first conductivity type constituting a light absorption layer on a III-V group compound semiconductor substrate, and a step of providing a first semiconductor layer of a first conductivity type constituting a light absorption layer, and a step of providing a second semiconductor layer of a first conductivity type having a large band width; and a third semiconductor of the first conductivity type having a forbidden band width larger than that of the second semiconductor layer in contact with the second semiconductor layer. a step of selectively providing the second semiconductor layer or the third semiconductor layer or a recess extending from the third semiconductor layer to the second semiconductor layer; A method for manufacturing an avalanche photodiode, including at least the step of providing a fourth semiconductor layer having a higher carrier concentration than the third semiconductor layer.
層をＩｎＧａＡｓ又はＩｎＧａＡｓＰ、該第２の半導体
層をＩｎＧａＡｓＰ又はＩｎＰ、該第３の半導体層をＩ
ｎＰ、該第４の半導体層をＩｎＰとする特許請求の範囲
第１項記載のアバランシェフォトダイオードの製造方法
。(2) The compound semiconductor substrate is InP, the first semiconductor layer is InGaAs or InGaAsP, the second semiconductor layer is InGaAsP or InP, and the third semiconductor layer is I
2. The method for manufacturing an avalanche photodiode according to claim 1, wherein the fourth semiconductor layer is InP.
電型のドーパントを選択的に拡散もしくはイオン注入す
る事により、該第４の半導体層内に接合を設ける工程を
有する特許請求の範囲第１項記載のアバランシェフォト
ダイオードの製造方法。(3) A patent claim comprising the step of providing a junction in the fourth semiconductor layer by selectively diffusing or ion-implanting a second conductivity type dopant from the surface after providing the fourth semiconductor layer. A method for manufacturing an avalanche photodiode according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61195217A JPS6352488A (en) | 1986-08-22 | 1986-08-22 | Manufacture of avalanche photo diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61195217A JPS6352488A (en) | 1986-08-22 | 1986-08-22 | Manufacture of avalanche photo diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6352488A true JPS6352488A (en) | 1988-03-05 |
Family
ID=16337410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61195217A Pending JPS6352488A (en) | 1986-08-22 | 1986-08-22 | Manufacture of avalanche photo diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6352488A (en) |
-
1986
- 1986-08-22 JP JP61195217A patent/JPS6352488A/en active Pending
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