JPS6352434A - Wafer external appearance inspecting apparatus - Google Patents

Abstract

PURPOSE:To make it possible to inspect a defect at a high speed without errone ously informing or missing the defect by providing a detecting sensitivity setter for suitably switching the defect detecting sensitivity at the time of inspecting. CONSTITUTION:A detecting sensitivity setter 11 which can alter the detecting sensitivity by a microcomputer 12 is provided in a device for irradiating a light to a predetermined position of a wafer pattern to detect the reflected light thereby obtained to detect a defect. A fine pattern part is inspected by a high detecting sensitivity and a large pattern part is inspected by a relatively low detecting sensitivity. Thus, a wafer external appearance inspecting apparatus which less erroneously informs or misses the defect and can inspect it at a high speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor manufacturing technology, and relates to a technology that is effective when applied to, for example, a wafer visual inspection apparatus.

[Prior Art] Patterns of diffusion layers, wiring layers, and insulating films of wafers tend to become finer and more dense year by year. In order to produce wafers with fine patterns at low cost and with high yield, it is necessary to perform defect inspection as early as possible to detect defective locations.

Pattern defect inspection on a wafer generally involves a combination of electrical property inspection and visual inspection. Here, for example, even if the wiring pattern on the wafer has defects such as uneven line width, scratches, or chips, electrical continuity is still maintained, so it is difficult to detect pattern defects by electrical property inspection. be. Therefore, visual inspection has an important meaning.

For example, for visual inspection, light 'FX (halogen lamp)
is converted into a line light source using an optical fiber, multiple irradiation is performed on the wafer surface from an oblique direction, and the reflected light is converted into 2048
Pixel CCD (charge coupled dev
ice) There is a known method for detecting with a line sensor.
). (See page 156 of "Nikkei Microdevices" published by Nikkei McGraw-Hill, June 1, 1986).

[Problems to be Solved by the Invention] The above-mentioned visual inspection method can be applied to parts such as memory cells in the wafer that require high-sensitivity inspection where fine patterns are formed, and relatively large patterns around the memory. The formed parts were also inspected with the same set sensitivity.

Here, when inspecting with a high inspection sensitivity, in the part where a relatively large pattern is formed, parts that do not need to be marked as defects are determined to be defects (hereinafter referred to as defect false alarms).
Resulting in.

Moreover, since the portion where a large pattern is formed is detected with a higher sensitivity than necessary, there is a problem in that the loss of inspection time becomes large.

On the other hand, when inspecting with a low detection sensitivity, there is a time-consuming process in which areas where fine patterns are formed are judged to be defect-free (hereinafter referred to as missed defects) when they should originally be judged to be defective. there were.

The purpose of the present invention is to minimize false alarms and oversight of defects.
Moreover, it is an object of the present invention to provide a wafer appearance inspection apparatus that can inspect at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, irradiating light onto a predetermined position on the wafer pattern,
A device for detecting defects by detecting the reflected light thus obtained is provided with a detection sensitivity setting circuit whose detection sensitivity can be changed by a microcomputer.

[Function] According to the above-mentioned means, fine pattern areas can be inspected with high detection sensitivity, and large pattern areas can be inspected with relatively low detection sensitivity, so that wafers can be inspected at high speed with fewer false alarms and missed defects. The above object of providing an appearance inspection device can be achieved.

[Embodiment] FIG. 1 is an explanatory diagram of a wafer visual inspection apparatus showing an embodiment of the present invention.

This wafer appearance inspection apparatus sequentially moves a wafer 2 fixed on a stage 1 in X, Y, and
The pattern on the wafer 2 is inspected for defects by moving it a desired distance in both directions. In the pattern of the wafer 2, the lights from the light sources P1 and P2 are reflected by the half mirrors M1 and M2, respectively, and are focused by the objective lenses OL1 and OL2 to the image detectors 4,
5.

The image detectors 4 and 5 include, but are not particularly limited to, CCDs (Charge Co.
Upled Device).

In other words, the image detectors 4 and 5 are light sources P1 and P, respectively.
The irradiation light of 2 receives the light reflected by the wafer 2, and an analog signal proportional to the amount of light is sent to the AD conversion circuit 6.
and output to 7.

The AD conversion circuit 6 receives the analog signal from the detector 5, converts it into a binary signal, and supplies it to the positional deviation detection circuit 8 and the image signal shift circuit 9.

On the other hand, the AD conversion circuit 7 receives the analog signal from the detector 4, converts it into a binary signal, and supplies the binary signal to the mismatch detection circuit 10 and the positional deviation detection circuit 8.

The positional deviation detection circuit 8 detects, for example, the position of the binary data sent out by the AD conversion circuit 6 and the binary data sent out from the AD conversion circuit 7 due to a positional deviation of the comparison pattern due to deformation of a wafer or the like. If the signals are supplied with a relative shift, a positional shift detection signal is supplied to the image signal shift circuit 9.

The image signal shift circuit 9 receives the positional deviation detection signal and
The binarized data sent out from the D conversion circuit 6 is shifted by a predetermined bit to the right or left to match the binarized data sent out from the AD conversion circuit 7, that is, the data is compared at a predetermined comparison position. It is supplied as the mismatch detection signal 1o. If the positional deviation detection signal is not supplied, the binary data is supplied as is to the mismatch detection circuit 10.

The mismatch detection circuit 10 is not particularly limited.

It consists of an exclusive OR gate. In this example, the nine pixels in comparison areas A to A as shown in FIG. 2 are compared with the binarized data of nine pixels in comparison areas A' to A'. An inspection is to be carried out. Therefore, the comparison areas A~■ and A'~
Exclusive OR gate (hereinafter referred to as
G1 to G9 (simply referred to as gates) are provided. Then, gates G1 to G9 have no defects, that is.

When the levels of the two input terminals of each of the gates G1 to G9 are made the same, a signal "'0" is output to the detection sensitivity selection circuit 11.

The detection sensitivity selection circuit 11, as shown in FIG.
ND gate Gl'-Gn' (however, n'≦511)
Consisted of. The input terminals of AND gates 61' to On' are connected to gates 61 to G9 depending on the test sensitivity.
Out of the two output signals, the number of signals and combinations of signals are varied and supplied. The output signals of the gates 61 to G4 are supplied to the input terminal of the AND gate Gl',
The output signals of gates G8 and G9 are supplied to the input terminal of gate On'. Setting of the detection sensitivity at the time of inspection is performed by a detection sensitivity selection circuit sent from the microcomputer 12. That is, this selects one of the AN D gates Gl' to Gn' and selects the other AN
All outputs of the D gates are taken to II OIT. As a result, the gate GIO outputs an output signal that depends only on the AND gate Gl'.

In FIG. 2, although not particularly limited, the signal output from the gate G10 is set to "1++" when there is a defect. That is, as is clear from the logic configuration of FIG. In terms of sensitivity, if even one pixel matches, it will not be determined that there is a defect.

The inspection method will be described below.

For example, in a part such as a memory where fine patterns are wired, even the slightest chipping of the wiring pattern or the presence of pinholes is undesirable, so the inspection is performed with a high detection sensitivity.

That is, in FIG. 2, for example, the AND gate Gn' is selected by the detection sensitivity selection signal Sn sent from the microcomputer 12 (the gate Grh' has two input terminals, and the gate Gl' has four input terminals). Therefore, when gate G n' is selected, the detection sensitivity is set twice as much as when gate Gl' is selected), that is, H indicated by the chain line in the figure ■
The inspection will be performed in two pixel constituent units, H' and I'.

For example, only when the signal levels supplied to the two input terminals of gate G8 are different and the signal levels supplied to the two input terminals of gate G1 are different, the signal sent out from gate G10 is II I ++, and it is determined that there is a defect.

On the other hand, when inspecting areas around memory where relatively large wiring patterns are formed, when inspecting with high defect detection sensitivity, there are many false alarms where areas that do not need to be detected are determined to be defective, and the inspection takes a long time. It will take a while. Therefore, it is necessary to carry out inspections with relatively low detection sensitivity.

For example, the AND gate Gl' is selected by the detection sensitivity detection signal S1 sent from the microcomputer 12. As a result, inspection is performed in four pixel constituent units, A-D and A'-D', indicated by two diagonal lines in the figure.

In the above-mentioned embodiment, the device for detecting defects by irradiating light onto a predetermined position on a wafer pattern and detecting the reflected light obtained by the light is equipped with a detection device whose detection sensitivity can be changed by a microcomputer. By providing a sensitivity setting circuit, fine pattern areas can be inspected with high detection sensitivity, and large pattern areas can be inspected with relatively low detection sensitivity, which reduces false alarms and missed defects, and allows for faster inspection. This has the effect of being converted into

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the case where the mismatch detection circuit is composed of a plurality of exclusive OR gates is explained, but if this is composed of exclusive NOR gates, in the defect detection area, If even one pixel is found to be inconsistent,
It may be determined that it is defective.

Further, in the above embodiment, the 2″′ formed on the wafer
Although defect inspection is performed by comparing the patterns of ), it is also possible to perform defect inspection by comparing with a reference pattern (non-defective product).

In the above explanation, the invention made by the present inventor was mainly applied to a wafer visual inspection device, which is the background field of application, but the invention is not limited to this. Applicable to appearance inspection equipment, etc.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, erroneous reporting or oversight of defects during the visual inspection of wafers is reduced.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of the case where the present invention is applied to a wafer visual inspection apparatus, and FIG. 2 is an explanatory diagram of the mismatch detection circuit 10 and detection sensitivity selection circuit 11 in FIG. 1...Stage, 2...Wafer, 3...°°
Stage moving table, 4, 5... Image detector, 6, 7...
... AD conversion circuit, 8 ... Position shift detection circuit, 9
. . . Image signal shift circuit, 10 . . . Mismatch detection circuit, 11 . . . Detection sensitivity selection circuit, 12 . . . Microcomputer.

Claims (1)

[Scope of Claims] 1. A wafer visual inspection device that detects defects in a pattern on a wafer by comparing a comparison pattern with a pattern to be inspected, the detection sensitivity setting circuit being capable of appropriately switching the defect detection sensitivity during inspection. A wafer appearance inspection device characterized by: 2. Comparison of the above comparison pattern and the pattern to be inspected is as follows:
2. The wafer appearance inspection apparatus according to claim 1, wherein the inspection is performed for each divided area by an optical inspection method. 3. The above-mentioned detection sensitivity setting circuit is composed of a plurality of AND circuits, each input terminal is supplied with a signal based on the comparison of divided regions of the comparison pattern and the pattern to be inspected, and each 3. The wafer visual inspection apparatus according to claim 1, wherein the input terminals of the AND circuit are supplied with different numbers of signals or different combinations of signals.