JPS6352379A - Digital information signal reproduction system - Google Patents

Abstract

PURPOSE:To reproduce signals of maximum 32 systems at a time by obtaining from signals reproduced from a recording medium in which compressed time division multiplexed digital information signals are stored with digital data signals made to line data. CONSTITUTION:A reproducing circuit 68 is used to reproduce four reproduced signals of A, B, C, D systems in the higher bit of (ch) 1 simultaneously. At the time of reproducing four reproduced signals of E, F, G, H systems in the lower bit of (ch) 1 simultaneously with four reproduced signals of A, B, C, D systems which are in the higher bit of (ch) 1, a reproducing circuit 69 of the same constitution with the reproducing circuit 68 is connected in parallel to the reproducing circuit 68 in the next stage of a higher rank/lower rank dividing circuit 52, and the reproduced digital signals of 9-15 bits out of lower bits (9-16th bit) of output of the higher rank/lower rank dividing circuit 52 are supplied to the reproducing circuit 69. Thereby, the eight reproduced signals of A, B, C, D, E, F, G, H of (ch) 1 can be reproduced simultaneously. Similarly, the reproduced signals of 32 systems in total can be reproduced at a time.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a digital information signal reproduction system, and in particular to a digital information signal reproducing system that reproduces a compressed digital information signal together with a digital data signal from a recording medium with high density. Regarding signal regeneration methods.

(Prior Art) Recently, the development of a digital information recording disk (hereinafter referred to as a digital disk) in which high-fidelity audio and still images are converted into digital signals and these digital signals are recorded has been announced and put into practical use.

On the other hand, image data files using video discs have not been put into practical use due to the extremely high price and problems with image quality since the video signals recorded on video discs are analog signals. is problematic.

In order to address these issues, compressed audio systems for digital discs have been developed that take advantage of the high quality of digital signals.

The modulation method for the S-angle signal recorded on this digital disc is to directly modulate the PCM (Pulse Code
HOdurationOn'), and logarithmic (LOG) compression is performed to 15 in the amplitude direction. The sampling frequency is 44.1kHz, which is the basic sampling frequency used for conventional digital discs, to make it easier to handle as an integer ratio.
, the relationship is 4:1.

FIG. 16 is a diagram showing an example of a signal recording format on a conventional digital disc.

This digital disc has 16 bits per channel (however, the dambling frequency is 44.1
kHz>, of which 10 bits are allocated to compression fame. In order to time-division multiplex and record four types of compressed audio per channel,
The dambling frequency of this pressure ll1i voice is IL025
Since it is kH2, data only needs to be sent once every four times, and two bits are assigned to the identification bits for identifying these four types of compression fame.

Furthermore, the remaining 4 bits other than those mentioned above are used for recording digital data signals such as character data.

For example, if compressed voices are time-division multiplexed and recorded on the four channels of the digital disc mentioned above, there will be a total of 16 compressed audio channels (4 channels x 4 types), and when this disc is in normal playback mode, 4”l with a sampling frequency of 44.1kHz.
If the signals are extracted at an interval (f x 44.1k) I2), 16 systems (species m) of compressed audio signals can be independently reproduced.

Therefore, normal playback only needs to be performed 16 times to extract all the information recorded on the disc, and if one hour of compressed audio is recorded per channel, the playback time will be 16 hours.

Also, two of the four channels of the digital disc mentioned above (for example, Chl.

If you want to record compressed audio on channel 2) and still image data on the other two channels (for example, ch3.4),
The compressed audio of each system is recorded on two channels, and the still images corresponding to the eight compressed audio systems are recorded in order on the other two channels, and the identification code (3 bits) in the data header is used to To extract an image corresponding to the audio channel.

Therefore, the present invention further provides a method for generating a desired information signal@(digital information signal and digital data An object of the present invention is to provide a digital information signal reproducing method in which the signal (signal) is transmitted at t7.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides digital data obtained by converting compressed pressure, 1-division multiplexed digital information signals into line data using logarithmic conversion and differential pulse code modulation. a first selection stage for selecting a reproduced digital signal corresponding to one channel from among reproduced digital signals corresponding to a plurality of channels reproduced from a recording medium recorded with the signal; a dividing means for dividing the reproduced digital signal into a reproduced digital signal of upper bits and lower bits; and a detecting means for detecting a particular system of reproduced digital signal in the reproduced digital signal supplied from the dividing means; an inverter for inverting the polarity of 1+1 constant bits of the reproduced digital signal supplied from the dividing means when a particular system of reproduced digital signal is supplied, and a pulse train signal generated in response to the signal from the detector 〇. Ii' for the pulse signal generating means and the pulse signal 1 signal.
1, a second selection means for selecting a reproduced digital signal supplied from the inversion means; and control for supplying a control signal to the first selection means, the division means, the inversion means, and the signal generation means. a signal generating means, a first processing means for obtaining a digital data signal from the reproduced digital signal from the dividing means, and a digital signal supplied from the second selecting means and modulated by the logarithmic conversion and differential pulse code modulation method. A digital information signal reproducing system is provided which is separated from a second processing means that inversely transforms an information signal and performs processing for keeping the amplitude level of the inversely transformed signal within a predetermined amplitude level range.

(Function) In the digital information signal reproduction method described above, 1
A desired information signal (digital information signal and digital data signal) is obtained from the signal reproduced from the recording medium on which the digital information signal compressed and time-division multiplexed by the conversion and differential pulse code modulation method is converted into line data. get.

(Example) First, before explaining the digital information signal reproducing method according to the present invention, we will explain the digital information signal compressed by logarithmic conversion and differential pulse code modulation method into line data (recorded together with g. A digital information signal recording method for recording on a medium will be explained.

FIG. 4 is a block system diagram showing an embodiment of a digital information signal recording method corresponding to the digital information signal reproduction method of the present invention, and FIG. FIG. 2 is a diagram showing an example of a signal recording format on a disc.

In FIG. 4, reference numeral 1 denotes an audio signal reproducing device, which is, for example, a device such as a magnetic tape reproducing device for reproducing a magnetic tape recording a high-pitched signal of an audio log. This 8-voice signal reproducing device 1 is capable of supplying 8-voice information for a maximum of 32 systems on a disc having a signal recording format as shown in FIG. I'll have to prepare it.

That is, as shown in Fig. 5, on the disk, there are 16 bits per channel (however, the sampling frequency is 4a1k) in the data recording direction (vertical direction in the figure).
1. ) (hereinafter referred to as chl, 2.3.4), and one
The two channels are divided into two by the upper 8 bits and the lower 8 bits, and the upper 8 bits of each channel (ch1 to ch4) are
For each bit and lower 8 bits, four types of compressed audio (upper one is A, B, C, D, lower one is E, F, G, H) are recorded by dividing them into multiple parts. There is. Therefore, a total of 32 systems (4 channels x 8 types) of compressed audio can be recorded.

In addition, in FIG. 5, 32 systems (types) of compressed audio are represented, for example, the top four types of chl are IA.

Indicated by IB, IC, 1D, and the lower four types of chl are IE
, IF, IG, 1t-(, and ch2.3°4 is similarly shown as shown in the figure.1 In addition, in FIG. 5, in the data recording direction, the upper and lower of each channel are Each consists of 8 bits,
Compressed audio is recorded in 7 bits of these, and a digital data signal is recorded in 1 bit following the least significant bit (L, SB) of these 7 bits. Furthermore, as will be described later, this digital data signal is composed of line data (li) having a length such that one data packet (block) can be completed in one track (one round of the track).
ne-Data).

Here, the explanation will be given again by returning to the block system diagram shown in FIG.

In FIG. 4, as described above, the audio signal reproducing device 1
must be prepared for a maximum of 32 systems, but since Ch1 to Ch4 have the same configuration, in the same figure, c
Upper and lower 8 strains of hl (1A, IB, 1C, 1D
and 1E, IF, IG.

1H) is shown. In addition, the upper four systems and the lower four systems of each channel have the same configuration, and each of the upper or lower four systems also has the same configuration except for a part, so the following is as follows. In the following, we will mainly explain the upper 1A system of chl, and omit the explanation of the other systems (18 to 1)-1), the upper 4 systems and the lower 4 systems of each other channel.

The analog 8-voice signal reproduced by the audio signal reproducing device 1 is passed through a low-pass filter (LPF) to prevent area sync.
2, by passing only signals in a frequency band equal to or less than the sampling frequency, aliasing is prevented, and furthermore, after being sampled at a rimbling frequency fifs of 44.1 kHz in the sample hold circuit 3, the A/ D (
The signal is supplied to an analog/digital (analog/digital) converter 4, where it is converted into a digital passenger car number n. Then, this digital audio signal is processed by L, OG DPCM (logarithmic transformation and difference P
CM) is supplied to the processing circuit 5, where it is subjected to logarithmic compression and differential PCM processing to become a 7-bit compressed audio signal.

Note that the sampling frequency at this time is the same as the sampling frequency fS in the sample hold circuit 3.

The 7-bit II compressed audio signal output from the LOG-DPCM processing circuit 5 is processed by the MSB inverting circuit 6 so that the most commercially available bit of the 7-bit compressed audio signal (digital signal) <MSB
B) is inverted and supplied to the time division multiplexing circuit 7.

However, this M S 8 inverting circuit 6 is provided for the upper four systems of each channel (A system of A, B, C, D>) and the subordinate four systems of each channel (E, F). ,G.
Of H), it is only the E strain.

Here, the reason why only the A and E systems are MS8 inverted is to distinguish the Δ and E systems from the messenger system. In other words, the specific data (1000000'' in binary two's complement representation) appears only in the A and E systems.

Therefore, during reproduction, the A and E systems can be detected, and since they are repeatedly recorded in a fixed order following the A or E system, it is possible to detect other systems.

In addition, for channels other than channels A and E of each channel mentioned above, the 7-bit compressed fame signal output from the LOG-DPCM processing circuit 5 is converted into 7-bit compressed audio by the bit conversion circuit 8. Signal (digital signal)
For example, the two's complement representation of the binary number ``100000''
By bit-converting the data of 0'' to 1000001'', as described above, the same data as the specific data ('1oooooo'> that serves as the mark of the A and E systems) does not appear.

In other words, '1000000' in binary two's complement representation
That is, the binary expression data “ooooooo○°” indicates the one-bit (reference) level of the audio signal.

This is the same as inverting the MSB of ``'o
1,000,000 for strains other than the A and Snake strains because it is the same as the specific data that appears as the landmark mentioned above by reversing the MSB of "o o o o o o".
Bit convert the data of '” to '10000O1' and
1,000,000" is prohibited.

Therefore, by detecting the appearance of "1000000'", it is possible to identify the A and E strains, and furthermore, by identifying the A and E strains, it is possible to identify the A and E strains for other strains as well.
Alternatively, since they are repeatedly recorded in a fixed order following the E line, it is also possible to identify other lines. Also, A
Since there is no need to provide a special bit for identifying the system tJc of the systems tJc and E, the bits for system identification can be saved, and the bits for the r′f compressed audio signal can be taken as extra bits, and the reproduced audio The quality of irises can be improved.

The 7 bits of the B, C, and D systems (or the F, G, -1 systems) other than the A system (or the E system) that have been bit-converted by the bit conversion circuit 8 as described above. The compressed B real signal is supplied to the division multi-base processing circuit 7.

In the 91 multi-hand processing circuit 7, the MSB inversion circuit 6
A is a 7-bit compressed audio signal of system A (or system Vt of E) supplied from system A and a 7-bit compressed quality signal of system other than system A (or system E).

B, C, D lineage (or E, F, G, H lineage)
A, B, C are time-division multi-Φized in the order of A, B, and C.

7 of each system of D (or each system of E, F, G, H)
BIT's compressed Fusei Shintan is 11.025kHz each.

It is output from here in a time-division multiplexed state at a transmission rate of .

On the other hand, 9 is a data signal reproducing device, which is, for example, a device such as a magnetic disk reproducing device that reproduces a magnetic disk on which digital data signals are recorded. The 8-bit digital data signal reproduced by this data signal reproducing device 9 is supplied to a data processing circuit 10, which converts the signal format from bucket 1 to middle (block 1) as shown in FIG. 9) generates and outputs a time-series synthesized digital signal.

Here, in the one packet signal shown in FIG.
Pl, GAP2. GAP3 is HULL DATA
(invalid data), SOP (SYNCC0DE O
"PACKET), SOD (SYNCCOD
E OF DATA), EOP (END C
0DE OF PACKET) are the start of a packet and the start of data, respectively.

A fixed pattern of Iv each indicating the end of a packet.
l Indicates the signal layout N position. IQ (IDENTlrl
CATION) is identification data, P I, (PAR
[TY Of' 10) indicates the arrangement position of 10 error correction parities. In addition, Do~D (DATA> is a data signal, P o ・” P 15 (PARITY
OF DATA) indicates the location of the data error correction parity 1.

The constituent parts of one packet mentioned above are composed of the number of numerical bytes (BYTE) as shown in the figure, and the total number of bytes consists of 294 bytes. Then, one byte consists of 8 bits (-2 nibbles, N1bble) of actual content.
As will be explained later, between the 1st bit of the 8 bits (i.e., before the top 0th nibble) and the 4th and 5th bits of the 8 bits (i.e., between the top nibble and the bottom nibble). One byte is made up of 10 bits by adding one bit to each bit (between
-294x10), which is a data length that matches the track length for one revolution of the disk. FIG. 7 is a diagram showing the signal format of the identification data 10, and FIGS. 8, 9, and 10 show the identification data IDV, which constitutes the identification data ID,
FIG. 3 is a diagram showing signal formats of channel data C1+ and flag data FLG. Identification data 10 is ID
It consists of 10 bytes of V-PRC.

In the IDV of the identification data ID shown in FIG.
NORHAL)T- records data of "00000000". When the configuration of the identification data 10 is changed, "o o" is used to sequentially distinguish them.

Data from 00001″ to “11111111” is recorded.

In channel data C1+ in FIG.
The 4th and 5th bits at the bottom are used to select the chl-4 channel, and the 4 scale channels from 00'' to 11'' are identified, and the 6th to 8th bits of the 8 bits are used to select the chl-4 channel. Used for selection of A・-H strains, “o o o
Eight types of strains from ``111'' are identified.

In the flag data FLOG in FIG.
ARTPACKET), DC(DATA C0N
TINUE PACK[T], DE(DATA E
ND PACKET), these indicate whether each packet is a single packet, the beginning, the end, or a continuation; for example, "101" indicates a single packet, and "110" indicates a starting packet. 010'' is a continuing packet, ``oii''
” is the last packet, “' o o o
” indicates a blank (no data) packet.

Also, ADDIt (Relation Address
s or eachchannel) is for each channel (
PRL (P
ROTECT L[:VEL') and PRC(PRO
TECT C0DE) indicates the level and code of the data protection area, and REV (Reserve) indicates reserved data.

Also, as mentioned above, each byte of one bucket of signals shown in FIG. 6 has 8 bits (-2 nibbles) of substantial content.
between the 1st bit of the 8 bits (i.e., before the upper nibble) and the 4th and 5th bits of the 8 bits (i.e., between the upper nibble and the lower nibble)
One byte is made up of 10 bits by adding one bit to each, but the added 2-bit data is SOP,
S.O.D.

Data of "1" is added to EOP, and as shown in FIG. 12, data of O' is added to SUP, SOD, and other than EOP to distinguish them. Thereby, by detecting SOP, SOD, and EOP, it is possible to prevent the signal of one packet shown in FIG. 6 from shifting in the direction of the track length.

As described above, the data processing circuit 10 in FIG.
, a data signal of signal format 1 as shown in FIG.
) The processing circuit 11 converts the 8-bit parallel data into 1-bit serial data, and the timing circuit 12
The output timing is controlled so that the beginning of one packet shown in FIG. 6 is output at the timing (44, 1 kHz) when the compressed fame signal chl output from the time division multiplexing circuit 7 is output. And this timing circuit 12
1-bit data signal (line data) output from
and the 7-bit compressed high-pitched digital signal outputted from the time division multiplexing circuit 7 to form an 18-bit digital signal, and further combine this 8-bit digital signal with the E~ of chl.
A total of 8-bit digital signals outputted from the route division multiplexing circuit 7 and the timing circuit 12 of the system 1 are supplied to the font conversion circuit 13 as a synthetic 16-bit digital signal (chl).

Furthermore, with respect to Ch2 to Ch4, a digital signal including 8116 bits (ch2.3.4) is supplied from each channel to the format conversion circuit 13, respectively, with the same configuration as chi.

The format conversion circuit 13 generates and outputs a digital signal that is synthesized in a time-series manner in block units in the H format shown in FIG. 13, which is known for digital discs.

Here, in one block of signals shown in FIG.
indicates the placement position of an 8-bit fixed page synchronization signal indicating the start of a block. chl.

ch2. Ch3 and Ch4 each indicate the arrangement position of one word of the 1 Gbit digital signal of each of the last four channels.

Furthermore, P and Q shown in FIG. 13 are each 16-bit error correction codes. Furthermore, the CRC has 23 bits of error correction.
ch1 to ch4. which are arranged in the same block. P,
Each word of Q, i4 Eva x 23+X5+X' +X+
It is a 23-bit remainder obtained when divided by a generator polynomial of 1, and during reproduction, the signal from the 9th bit to the 127th bit of the same block is removed by the above generator polynomial,
When the resulting remainder is U, it is used to detect that there is no error.

Furthermore, in FIG. 13, △dr is various control signals (address ic+) used for random access etc.
It shows the multi-movement of 1 bit. This control signal distributes each bit data and transmits one bit in one block. For example, all bits of the control signal are transmitted in 196 blocks (that is, one block signal consists of 196 bits).

Furthermore, U is two bits for reserve called user's bits, and transmits a language for connecting a computer to a playback device and having it perform an interactive game, for example. One block of signals is composed of a total of 130 bits from S to U shown in FIG. 13, and the digital signals are synthesized in blocks at a frequency of 44.1KH2 and transmitted in time series. The above 196-bit control signal has a configuration in which four types of address codes of 19 bits each are synthesized in time series, and these four types of address codes all have the same signal format.

The digital signal extracted from the format conversion circuit y113 in time series at block ψ of the signal format as shown in FIG. 13 is scrambled NR as shown in FIG.
The signal is supplied to the Z modulator 14, where the signal excluding the 8-bit synchronization signal is scrambled NRZ modulated by modulo 2 addition with a signal from a preset random number table (for example, ~1 sequence code). After the FM modulation circuit 1
5. The frequency-modulated digital signal taken out from the FM modulation circuit 15 is supplied to a recording device 16 such as a known cutting machine, and after being converted into a modulated light beam, it is focused and irradiated onto the photosensitive material on the disc-shaped recording master 17. be done. By passing this disk-shaped recording master disk 17 through a known development process and I process, a large number of disks (digital disks) can be reproduced.

Note that it is of course possible to record on a recording medium other than a disc.

Furthermore, in the disk shown in FIG. 5, there are four systems (A, B, C) in the time division direction for each channel.

D or E, F, G, H), and digital disc Itl! 44.1kl which is the simbling frequency,
1 1 , 025k, which has an integer ratio of 4:1 to
Although we have explained the case where the compressed audio of each series is recorded at a sampling frequency of Hz, for example, each series may be recorded at a standard sampling frequency of 5:1 or 6:1, or at other integer ratio rimbling frequencies. Of course, it is also possible to divide each channel into five or six systems in the time division direction so that the compressed audio can be extracted. It is sufficient to divide the audio into n (n is an integer of 2 or more) systems in the division direction and record the compressed audio of each system so that it can be extracted at a standard sampling frequency of 1/n-fs with respect to the standard sampling frequency fs.

Furthermore, even if digital signals consisting of compressed audio and digital data are not recorded on all four channels of a disc, two of the four channels (
or only one or three channels),
Image data may be recorded in other channels.

Next, an embodiment of the digital information signal reproducing method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the digital information signal reproducing method according to the present invention, FIG. 2 is a configuration circuit diagram of an exponent conversion and addition circuit 37, and FIG. 3 is a timing signal generation circuit 2.
9 is a timing chart of latch pulses generated from 9.

In FIG. 1, 21 is a player, 22 is an FM demodulation circuit, 23 is an error correction circuit, 24 is a channel selection circuit, 2
5 is Ch1-4 select circuit (first selection means), 2G
, 34 is a serial/parallel (S/P) conversion circuit, 2
7 is an upper/lower selection circuit (dividing means), 28 is an A (or E) system detection circuit (detection means), 2 is a timing signal generation circuit (signal generation means), and 30 is a selection signal generation circuit (control signal generation means). ), 31 is an MS8 inverting non-inverting circuit (inverting means), 32 is a latch circuit (second selection means)
, 33 is a read timing circuit, 35 is a data processing circuit, (the first processing means in this application is a read timing circuit 33, a serial-parallel (S/P) conversion circuit 3
4, consisting of a data processing circuit 35), 3G is a data output terminal, 37- is an index conversion and addition circuit (second processing means), 38 is a D/A converter, 3 is a δ flow cutoff circuit, 40 is a This is an analog signal output terminal f.

The channel selection circuit 24 is a channel selection circuit 2
5. S/P conversion circuit 26. Upper and lower selection circuit 27゜A (
E) System detection circuit 28. Timing signal generation circuit 29.
Select signal generation circuit 30. MS8 inversion male inversion circuit 31
．． It consists of a wrap circuit 32.

Now, the moving parts of the block system diagram shown in FIG. 1 will be explained.

For example, the fifth record recorded by the recording method described above.
An FM digital signal reproduced from a digital disc (f not shown) with a signal as shown in the figure is supplied from the player 21 to the FM demodulation circuit 22, where F l
After being demodulated, the first
The reproduced digital signal has the signal format shown in FIG. 3.

This reproduced digital signal is sent to the channel selection circuit 24.
is supplied to the h1-4 select circuit 25, where the c
The reproduced digital signal of any one channel of the four channels h1 to Ci4 (hereinafter abbreviated as "ch") is selected. The select signal generating circuit 3o is connected to a channel select button (not shown) of the refurbished equipment, and a select signal (control tllll signal) is generated by operating the select button.
is configured to be supplied with.

The 1-bit serial reproduced digital signal outputting Ch 1 to 4 select from one circuit 25 is supplied to the S/P conversion circuit 26, where it is converted into a 16-bit parallel reproduced digital signal, and then sent to the upper/lower selection circuit 27. Here, the 16-bit reproduced digital signal consists of the upper bits (1 to 8
The reproduced digital signal of the lower bit (9th to 1st bit)
6th bit) and the reproduced digital signal. Of this reproduced digital signal, the reproduced digital signal of 1 to 7 bits of the upper bits (or 9 to 15 bits of the lower bits) is transmitted to the A(E) system detection circuit 27 and the MS.
It is supplied to the B inverting and non-inverting circuit 31, and also 8 bits of the upper bits or 16 bits of the lower bits.
The reproduction digital signal of bit 1) is supplied to the readout timing circuit 33, where the limp ring frequency f s
(44.1kHz), the data is supplied to the S/P conversion circuit 34, where it is converted from 1-bit serial data to parallel data, and the data processing circuit 35 processes the data signal in a predetermined manner (for example, channels identification, error correction, etc.), and the digital data is sent to the data output GF.
Output from 3G.

On the other hand, the A(E) system detection circuit 28 detects the supplied
Alternatively, when the reproduced digital signal of the last 7 bits of the upper bits is specific data of the A system (or the E system), this is detected and a detection signal is supplied to the timing signal generation circuit 29. Timing signal generation circuit 29 receives this detection signal and sends a latch pulse shown in FIG. 3 to latch circuit 32.

The timing signal generation circuit 29 is the select signal 8 generation circuit 3.
Pulses a to d shown in FIGS. 3(A) to 3(D) are sent out in response to select signals of A to D systems (or E to 11 systems) from O.

How to use, A system (or E system) is selected, and M S
When a signal is output from the select signal generation circuit 30 to the B inverting/non-inverting circuit 31, the polarity of the MSB of this signal is inverted. Furthermore, when a system other than the A system (or the E system) is selected, the positivity of the signal ~1SB is not inverted here.

The output signal from the MSB inversion circuit 31 is sent to the latch circuit 32, where it is latched with a latch pulse corresponding to each system as shown in FIG. 3 from the two timing signal generation circuits, and then The signals are supplied to the conversion and addition circuit 31, where they are converted and added to the "c" index, and then supplied as a 1 Gbit signal to the D/A converter 38, where they are converted to analog playback signals and then passed through the DC cutoff circuit 39. A reproduced analog signal is output from the analog signal output screw 40 via the analog signal output screw 40.

In the manner described above, a reproduced analog signal such as an a-angle signal is reproduced from a digital disc recorded using the above-described recording method.

Here, the above-mentioned finger ¥1. The role of the conversion and addition circuit 37 is to inversely convert the recorded signal that has undergone logarithmic conversion (signal compression) and differential PCM into the original digital audio signal, and to vary the reference level of the reproduced signal to adjust its amplitude. The goal is to keep the level within a predetermined amplitude level range.

The above-mentioned index conversion and addition circuit 37 is constructed as shown in FIG. In the figure, 41 is an index conversion circuit, 42 is an addition circuit, 43 is a latch circuit, 44 is a data selector, 45 is a latch circuit, 46 is an EX-OR circuit, 4
7 is an inverter circuit.

Next, the operation of the exponent conversion and addition circuit 37 will be explained.

The reproduced digital signal from the latch circuit 32 described above is supplied to the index conversion circuit 41, where it is expanded by an index, and then sent to the OG-DPCM processing circuit 5 in the recording system shown in FIG. It is assumed that the reproduced signal is inversely transformed using an exponential curve with characteristics opposite to that of the 3-digit logarithmic transformation curve.

Furthermore, this signal is supplied to the addition circuit 42, and furthermore, the output signal from the addition circuit 42 is supplied to the latch circuit 43,
After being held for 1/fs (fs is the sampling frequency) vI, it is supplied to one input side of the data selector 44.

The data selector 44 has one input side A supplied with the output signal from the latch circuit 43 as described above, and the other input side B supplied with a signal to be described later. This signal is output only when a control signal is output from the EX-OR circuit 46.

Further, the output signal from the data selector 44 is supplied to another latch circuit 45, where it is latched and then supplied to the D/A converter 38 at a required timing.

Here, normally (that is, when the reproduced signal from the adder circuit 42 is within a predetermined amplitude level range), the data selector 44 is switched to one input side, and the output signal from the latch circuit 43 is The signal is supplied (feedback) to the adder circuit 42 via the data selector 44, where it is added to the new reproduced signal from the index conversion circuit 41, and then held in the latch circuit 43. Then, the signal supplied (feedback) from the data selector 44 and the new reproduced signal from the index conversion circuit 41 are sequentially added.

However, when the level of the reproduced signal from the latch circuit 43 exceeds the predetermined amplitude level range (that is, the upper two bits (15th and 16th bits) of the 16-bit reproduced signal are set as excessive level detection bits, When these 2 bits do not match (“o o” or '11')
), an 8 select signal is output from the EX-OR circuit 46, and a signal supplied to the other input side B of the data selector 44 is output.

This signal is used to vary the reference level of the reproduced signal so that its amplitude level falls within a predetermined amplitude level range.

As described above, the signal from the other input side B of the data selector 44 is supplied to the addition circuit 42, where it is added to the new reproduced signal from the index conversion circuit 41.

When the signals of the 15th and 16th bits, which are the excessive level detection bits supplied to the EX-OR circuit 46, match, the A select signal from the EX-OR circuit 46 is output, and thereby the latch circuit 43 The held reproduced signal is supplied to the adder circuit 42 via the data selector 44, where it is added to the reproduced signal from the index conversion circuit 41, and then sequentially combined with the signal supplied (feedback) from the data selector 44 and subjected to index conversion. A new reproduction signal from circuit 41 is added.

In this way, the exponential conversion and addition circuit 37 returns the logarithmically converted (signal compression) and differential PCM-converted playback signal to the original digital audio signal, and when the level of the playback signal is excessive, it converts it to an appropriate level. can be in a state.

In addition, although the above description was about reproducing only the reproduced digital signal of any one of the four channels Chl to Ch4, the reproduced digital signals of these four channels (total of 32 systems of reproduced digital signals) To play simultaneously, this can be achieved by configuring as follows.

FIG. 15 is a block system diagram for simultaneously outputting 32 systems of reproduction signals.

In the figure, 50 is chl, 2 switching circuit, 51 is chl
3, 4 switching circuit, 52.53 is upper/lower division circuit, 5
4 is an A system detection circuit, 55 is a timing signal generation circuit,
56 to 59 are latch circuits, 60 is an MS8 inversion circuit, 61
-63 are shift circuits, 64-67 are index conversion and addition circuits, and 68.69 are reproduction circuits.

First, A, B, and C in the first bit of Chi.

The simultaneous reproduction of four reproduction signals of the D system will be described.

For example, the fifth record recorded by the recording method described above.
An FM digital signal reproduced from a digital disk (not shown) having the signal format shown in the figure and on which 32 signals are recorded is supplied from the player 21 to the FM demodulation circuit 22. After FM demodulation here, the reproduced digital signal is supplied to the error correction circuit 23, where descrambling and decoding error correction have been performed, and the reproduced digital signal is supplied to the chl, 2 switching circuit 50, where the sampling frequency fis 44,1KH,),
The reproduced digital signal of chl or ch2 is switched, and the reproduced digital signal of chl is output from here. C
The reproduced digital signal of hl is supplied to the upper/lower dividing circuit 52, and this signal is divided into the reproduced digital signal of the upper bits (1st to 8th bits) and the reproduced digital signal of lower bits (9th to 16th bits). be done.

One of the upper bits of this reproduced digital signal
The 7-bit reproduced digital signal is supplied to the A-system detection circuit 54, and is also supplied to the A-, B-, C-, and D-system latch circuits 56.
~59 respectively.

The A system detection circuit 54 detects whether the supplied reproduced digital signal is A
When it is system specific data, it is detected and a detection signal is supplied to the timing signal generation circuit 55. Upon receiving this detection signal, the timing signal generation circuit 55 generates a signal as shown in FIG.
Latch pulses a to d shown in ) to (D> are supplied to each of the latch circuits 56 to 59.

In this way, the reproduced digital signals of the A, B, C, and D systems are latched by the latch circuits 56 to 59 for a predetermined period of time in response to the latch pulses ad from the timing signal generation circuit 55. The reproduced digital signal of the A system latched by the wrap circuit 5G is supplied to the MS8 inversion circuit 60, and after the polarity of the MSB of this signal is inverted, it is supplied to the shift circuit 61 three times, where the rimbling frequency fs is shifted three times. B (
C) The reproduced digital signal of the system is passed through the two-time shift circuit 62 (
The signal is supplied to a one-time shift circuit 63), where it is shifted twice (once) at the ring-ring frequency fs. The A to C reproduced digital signals shifted by the shift circuits 61 to 63 are supplied to index conversion and addition circuits 64 to 66, respectively. The reproduced digital signal of the D system latched by the latch circuit 59 is directly supplied to the index conversion and addition/falsification circuit C7. After this, it goes without saying that a D/A converter and a δ@ cutoff circuit (none of which are shown) are cascade-connected at the next stage of the index conversion and addition circuits 64 to 67, respectively.

In this way, with the above-described configuration, the four reproduction signals A, B, C, and D@in the upper bits of chi can be simultaneously reproduced.

Now, the reproduction circuit 68 includes the A system detection circuit 54, the timing signal generation circuit 55, the latch circuits 56 to 5, and the MSB
It is composed of an inversion circuit 60, shift circuits 61-63, and index conversion and addition Q circuits 64-67.

As described above, the reproduction circuit 68 has a configuration used to simultaneously reproduce the four reproduction signals of A, B, C, and D systems in the upper bits of Ch. ,B,C.

When simultaneously reproducing the four reproduction signals of the E, F, G, and H systems located in the lower bits of chi at the same time as the four reproduction signals of the D system, a reproduction circuit 68 is installed at the next stage of the upper digit division circuit 52.
A reproducing circuit 69 having the same configuration as the reproducing circuit 68 is connected to the reproducing circuit 68 in W columns, and reproduces the reproduced digital bits of the 9th to 15th bits of the lower bits (9th to 16th bits) of the output of the upper/lower dividing circuit 52. The signal may be supplied to the reproducing circuit 69.

Thus, A, B, C, D, E, F of chl.

Eight reproduction signals of the G and l-1 systems can be reproduced simultaneously.

Hereafter, Δ, B, C, D of ch2 in the same manner.

In order to simultaneously reproduce the eight re-1 signals of the E, F, G, and H systems, two reproducing circuits having the same configuration as the above-mentioned reproducing circuit 68 are connected in parallel to the upper/lower dividing circuit 530 and the next stage. good.

Furthermore, A, B, C, D of ch3 (ch4).

In order to simultaneously reproduce eight reproduction signals of the E, F, G, and H systems, an upper/lower dividing circuit 52 (not shown) and a reproduction circuit 68 (not shown) are connected in cascade at the next stage of the channel 3, 4 switching circuit 51. Just connect two of the same configuration in parallel.

In this way, by simultaneously using all the configurations in ch 1 to ch 4 described above, each A of ch 1 to ch 4,
It is possible to simultaneously reproduce reproduction signals of B, C, D, E, F, G, and H systems, a total of Δ132 systems.

(Effects of the Invention) As described above, according to the digital information signal reproducing method of the present invention, logarithmic conversion and differential pulse code modulation (LOG
- A desired information signal (digital information signal) is obtained from a signal reproduced from a recording medium recorded with a digital data signal obtained by converting a digital information signal compressed into 5 divisions into line data by the DP CM method) method. Because of this, compared to conventional playback methods, it is possible to arbitrarily select the number of audio channels that can be played back, and has the advantage of being able to play back up to 32 systems (32 types) of signals at the same time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the digital information signal reproducing method according to the present invention, FIG. 2 is a configuration circuit diagram of the index conversion and addition circuit 37, and FIG. 3 is a timing signal generation circuit 2.
9 is a timing chart of latch pulses generated from 9, FIG. 4 is a block system diagram showing an embodiment of a digital information signal recording method corresponding to the digital information signal reproducing method according to the present invention, and FIGS. 5 and 14 are FIG. 4 is a diagram showing an example of a signal recording format on a disc recorded by the recording method configured as shown in FIG. Figures 7 to 12 are shown in Figure 6.
A diagram showing an example of each format that makes up the signal format of a packet, FIG. 13 is a diagram showing an example of the signal format of one block of digital signals recorded on a disk, and FIG. 15 is a diagram showing an example of the signal format of one block of digital signals recorded on a disk. FIG. 16 is a block diagram showing an example of a signal recording format on a conventional digital disc. DESCRIPTION OF SYMBOLS 1... Audio signal reproducing device, 2... Low pass filter, 3... Sample hold circuit, 4... A/D converter, 5... t, OG-DP CM processing circuit, 6
...MS8 inverting circuit, 7... time division multiplexing circuit,
8...Pitch conversion circuit, 9...Data signal generation circuit, 10...Data processing circuit, 11...Parallel/serial processing circuit, 12...Timing circuit, 13...F4 - conversion circuit to pine 1, 1
4...Scrambled NRZ modulator, 15...FM
Modulation circuit, 16... Recording device, 17... Deployment master,
21... Player, 22... FM demodulation circuit, 23
...Error correction circuit, 24...Channel selection circuit,
25...Chi~4 selection circuit (first selection means)
, 26, 34... Serial/parallel (S/P) conversion circuit, 27... Upper/lower selection circuit (dividing means), 28
, 54... A (or E) system detection circuit (detection means), 29, 55... Timing signal generation circuit (signal generation circuit), 30... Select signal generation circuit (AI control signal generation stage, 31, 60... MSB inverting non-inverting circuit (inverting means), 32, 56 to 5... latch circuit (second selection means), 33... read timing circuit, 35... data processing Circuit, to 33. 35... First processing means, 36... Data output terminal, 37, 64-G7... Index conversion and numbing circuit (second processing means), 38... D /A converter, 39... DC cutoff circuit, 40... Analog signal output terminal, 41... Index conversion circuit, No. 12... Addition circuit, 13, 45... Latch circuit, 44...・Data selector, 46...EX-OR circuit, 47...Inverter circuit, 50, 51...Switching circuit, 52.53...Upper/lower division circuit, 01-63...Shift circuit, 68
．． 69... Regeneration circuit. From Figure 6, V 0000Q000-Ill (We “IAL ship) δゝ
C] Saiq1 Koi 10 Figure Sai/φKoshifu/6 Q]

Claims (1)

[Claims] One channel from among the reproduced digital signals corresponding to a plurality of channels that are reproduced from a recording medium in which a digital information signal compressed and time-division multiplexed by logarithmic conversion and differential pulse code modulation is recorded together with a digital data signal converted into line data. a first selecting means for selecting a reproduced digital signal corresponding to the first selecting means; a dividing means for dividing the reproduced digital signal selected by the first selecting means into a reproduced digital signal of upper bits and lower bits; a detecting means for detecting a specific system of the reproduced digital signal in the supplied reproduced digital signal; and a detection means for detecting the polarity of a particular bit of the reproduced digital signal supplied from the dividing means when the particular system of the reproduced digital signal is supplied. an inverting means for inverting, a signal generating means for generating a pulse train signal in response to a signal from the detecting means, and a second selecting means for selecting a reproduced digital signal supplied from the inverting means in synchronization with the pulse train signal. a control signal generating means for supplying a control signal to the first selecting means, the dividing means, the inverting means and the signal generating means; a first means for obtaining a digital data signal from the reproduced digital signal from the dividing means; processing means, and inversely converting the digital information signal supplied from the second selection means and modulated by the logarithmic conversion and differential pulse code modulation method, and converting the amplitude level of the inversely transformed signal to a predetermined amplitude level. A digital information signal reproducing method comprising: a second processing means that performs processing for keeping the signal within the range.