JPS58224412A - Method for recording digital information signal - Google Patents

Abstract

PURPOSE:To reduce synchronization with an incorrect synchronous pattern which will be sometimes generated when all information data in a digital signal are ''0'' or ''1'' at the time of reproducing by using a code array preventing the generation of the same pattern with the synchronous signal in the digital signal. CONSTITUTION:A random code array outputted from a data scramble circuit 22 and a synchronizing signal outputted from a synchronizing signal circuit 21 are selected so as to coincide with prescribed patterns respectively. A main information signal is recorded in a spiral main track and burst-like 1st and 2nd tracking controlling signals fp1, fp2 having different frequency each other both of which are lower than the recording frequency band of the main information signal are switched every rotational period and recorded in a subtrack formed on almost the intermediate part of the center line of the track. In addition, the 3rd tracking signal fp3 is recorded in the main track at the switching/connecting part of the fp1 and fp2 by a prescribed level or less without exerting an influence on the main information signal. Consequently, synchronization with an incorrect synchronous pattern can be reduced.

Description

[Detailed Description of the Invention] The present invention relates to a digital information signal recording method, in which a code sequence having a specific rule for generating a randomized digital signal does not produce the same pattern as a synchronization signal in the digital signal. By using a code sequence, all information data in the digital signal is "0" during playback.
It is an object of the present invention to provide a digital information signal recording method that can reduce synchronization to an erroneous synchronization pattern that may occur when the signal is "1" or "1".

Digitally modulates an analog information signal such as an audio signal or a video signal, thereby dividing the digital data into predetermined sections, and adding a synchronization signal, an error detection code, and an error correction code to each section signal. A digital signal that constitutes one frame, and this frame signal is synthesized in time series, is stored on a disc-shaped recording medium (hereinafter referred to as a "disk").
Conventionally, it has been known to record the presence or absence of pits. If this disc is of a variable capacitance reading type, it has a wide playback band and can secure the number of customers who can transmit 16-bit digital information through four channels. Furthermore, since a sufficient transmission band can be obtained, it is advantageous for data transmission to perform frequency modulation that is resistant to dropouts and level fluctuations.

The data format when recording with frequency modulation is NR.
Z (Men Return to Zero) is advantageous in terms of bandwidth usage, but depending on the information being transmitted, there may be many "0" or "1" bits, and all signal bits in one frame may be "0" or "1" bits.
When the bit is "0" or "1", or in a state close to this, stable or locked playback becomes difficult, and bit synchronization may not be achieved. On the other hand, it is also possible to modulate and record data that can be self-clocked, but in this case, the frequency spectrum is concentrated in the high range, and the noise spectrum of frequency demodulation is called triangular noise, and the high frequency components are Since there is a lot of noise, the influence of deterioration of the high-frequency 4 ratio of the demodulated signal is large, and there are also drawbacks such as... -doware is a dog.

Therefore, the present applicant previously proposed a method of randomizing and recording the NRZ signal in Japanese Patent Application No. 1203511/1983. FIG. 1 shows a block diagram of an example of a reproducing apparatus for a disc recorded using the proposed digital information signal recording method. In the figure, the signal picked up and reproduced from the disk 1 by the pickup circuit 2 is a frequency modulated wave signal obtained by frequency modulating a carrier wave with a randomized digital signal, and is supplied to the FM demodulation circuit 3. After being subjected to FM demodulation, the signal is supplied to the data and clock recovery circuit 4.

The data and clock regeneration circuit 4 extracts a randomized digital signal (data) from the FM demodulated signal as a required rectangular wave, and also regenerates a clock signal from the signal obtained by detecting the edge portion. , and supplies the reproduced clock signal to a synchronization detection protection circuit 5, a random code sequence control circuit 6, and a random code sequence generation circuit 7, respectively. In addition, the reproduced digital signal is supplied to the synchronization detection protection circuit 5, and even if synchronization (1) is detected in one frame and the same pattern as the KfiM period signal exists in the information data in one frame, this This synchronization detection protection circuit 5 prevents erroneous detection of synchronization signals, and in case a signal is lost due to dropout or the like, if a number of consecutive synchronization signals cannot be obtained, the data is discarded. The synchronization signal detection signal taken out from the synchronization signal is supplied to the random code sequence control circuit O, where it is made into a control signal and then supplied to the random code sequence generation circuit γ, from which the data input period after the synchronization signal is recorded. This random code sequence and the reproduced digital signal are each supplied to an exclusive OR circuit 8, where addition modulo 2 (addition modulo 2) is performed. The signal is then restored to the original digital signal (NRZ signal) and output to the output terminal 8.

Here, if the information data in the randomized digital signal sequence reproduced and extracted by the clock and reproduction circuit 4 is digital audio data and the information is silent, or if the information data is additional information of the music signal. If the data is still image data that is played back as a period of time ( (Normally, the longer the playback period of the first still image data, the longer this data non-transmission period becomes.) Since the information data is all "0" or "1", it is randomized by addition modulo 2. The random code sequence appears as is. Therefore, in such a case, if a code sequence with the same pattern as the synchronization signal is used as the random code sequence, in addition to the true synchronization signal transmitted at the shaded position in Figure 2 (A), there will be A false synchronization signal appears periodically as shown by the broken line in (Figure 2 (A), the false synchronization signal appears in one place within the same frame, but it may appear in two or more places depending on the selection of the random code sequence. ).

The above-mentioned periodic false synchronization signal is normally rejected by the synchronization detection protection circuit 5 using autocorrelation as described above, and the periodic false synchronization signal is detected as being phase-synchronized with the true synchronization signal as shown in FIG. Since the signal is obtained, bit synchronization can be achieved stably, but if a part of the signal is lost due to a dropout etc. and the synchronization is lost, and then the dropout disappears and the synchronization pull-in operation starts, depending on the timing The above periodic false synchronization signal is detected as a synchronization signal,
The signal shown in FIG. 2(0) was sometimes output from the synchronization detection protection circuit 5 as a synchronization signal detection signal.

In this way, in the above-mentioned recording method proposed by the present applicant, if a random code sequence in which pseudo-synchronization patterns are likely to appear in the data is used, the pseudo-synchronization signal will be erroneously detected and a randomized digital signal will be generated. The problem is that it may not be possible to restore the original digital signal properly, and the time it takes to discard data becomes longer (synchronization recovery time becomes longer), and effective data transmission may not be possible, resulting in poor efficiency. was there.

The present invention solves the above problems, and one embodiment thereof will be described with reference to the drawings from FIG. 3 onwards.

FIG. 3 shows a block system diagram of an embodiment of the method of the present invention. This embodiment has the same block configuration as the digital information signal recording method previously proposed by the applicant.
The key point is that the output random code sequence of the data scrambling circuit 22 and the output synchronization signal of the synchronization signal generator 21 are respectively selected to have predetermined patterns. Further, the recording medium recorded in this embodiment does not have a needle guide groove (i.e., the main information signal is recorded on a spiral main track).
j? Moreover, the first and second tracking control reference signals (hereinafter referred to as "
Tracking signals (referred to as "tracking signals") f and fp2 are alternately switched every rotation period of the disk and are recorded to form a sub-track approximately in the middle between the track center lines of adjacent main tracks. For example, consider a disk that has an electrode function where the tracking signal 'pi of i'iea is recorded at a level below a predetermined level on the main track so that it does not affect the main information signal at the switching connection part of fpl and tp2. I will explain it to you.

Here, the main information signals may be audio signals for all four channels, but are assumed to be three channels of audio signals and one channel of still image signals. That is, three channels of audio signals are input to the input terminals 11, 12 and 13, respectively, and a still image signal is input to the input terminal 14. The audio signals inputted to the input terminals 11 to 13 are respectively sampled by AD converters 15 to 17 at a sampling frequency of 44.1 kHz, for example.
After being quantized and converted into a digital audio signal (POM audio signal) with a quantization number of 16 bits (14 to 16 bits are required for high-fidelity reproduction), it is supplied to a signal processing circuit. Ru. On the other hand, input terminal 14
The incoming still image signal is supplied to the AD converter 18,
Here, after being sampled at a sampling frequency of, for example, 10.7 MHz, quantized, and converted into a digital video signal with a quantization number of about 8 bits, a random access memory and a control circuit (not shown) convert the time axis into a digital video signal. The signal is stretched to a sampling frequency of 88.2 kHz and quantization of several bits (this is equivalent to a sampling frequency of 44.ikiss and a quantization number of 16 bits), and then supplied to the signal processing circuit 1g.

The signal processing circuit Ill divides these 16-bit four-channel input digital signals into predetermined intervals, and divides them into multiple frames in order to achieve a higher correction rate even for burst errors during playback. It performs interleaving that is distributed in a periodic manner, and also generates an error correction code for correcting code errors caused by dropouts caused by dust on the disk h or other causes. Generates an error detection code (0ROO) that determines whether an error has occurred during transmission of four channels of input digital signal data and error correction code, and address data information, and generates a signal by time-division multiplexing these. do. This time division multiplexed signal is added with a fixed turn synchronization signal bit by a synchronization signal generator 21 in a frame signal generation circuit 20 to form a frame input signal.

FIG. 4 is a diagram schematically showing one frame (one block) in each frame signal generated by the frame signal generation circuit 20, and YNO is an 8-bit fixed pattern synchronization signal indicating the beginning of the frame signal. indicates the area of existence. The preferred synchronization pattern for 8 bits is from the literature (edited by Hiroshi Inose:
As shown in POM communication basics and new technology, page 286, Sanho], r33J, r35J, rzγ in Nisshin display.
"and so on. Complementary code, reverse code,
Since each reverse complementary code is equivalent to the original code, for example, if the reverse code of "35" in Japanese decimal notation is used as a synchronization pattern, "1"
0111000'', and its waveform becomes as shown in FIG.

Next, 0h-1 to 0h-5 shown in FIG. 4 are respective channel data existence areas of the 16-bit digital audio signal of the three channels, and 0h-4 is the 16-bit Daisimel Video No. 1 (still video). In addition, P and Q each indicate the existence area of a 16-bit error correcting code generated by the following equation, for example.

However, in the above formula w1. W-w! , w4 is 0h-1
~oh-4 16-bit digital signals (usually digital signals that each belong to a different frame), T
is an auxiliary matrix of a predetermined polynomial, and ■ represents addition modulo 2 for each corresponding bit. Note that the above formula is an example.

Furthermore, in FIG. 4, ORO indicates the area where a 23-bit error p detection code exists, and this error detection code is arranged in the same frame, for example, from 0h-1 to oh-4,p.

This is the 23-bit remainder obtained when each word of Q is divided by a generator polynomial of, for example, X 10x 10x +X+1. Furthermore, FIG. 4 shows the area in which the Adri'i address information bit exists, one bit is transmitted in one frame signal, and all bits of address information are transmitted in, for example, 186 frames (that is, the address information is 116
(composed of bits). The last two bits are reserved bits called user's bits.

The digital signal (this is an 'NRZ signal) that constitutes one frame with a total of 130 bits from 5YNO to ■ mentioned above has a repetition frequency of, for example, 441kHz, which is the same as the sampling frequency, and a transmission bit rate of 5.733kHz. Mb
/s, each frame is sequentially extracted from the frame signal generation circuit 20 in time series, and the data is sent to the data scramble circuit 2.
2, and here the frame signal portion excluding the synchronization signal is randomized (this is called scrambling). Note that the entire frame signal may be scrambled.

In the data scrambling cycle 22, a random code sequence such as an M sequence is generally used as the random code sequence used for the scrambling process, since the purpose is to randomize the signal to be recorded. 1 frame 13
To randomize 0 bit data, 127<-2
-1) VCJI data can be cyrandomized by using a 7th-order random code sequence that completes with -1). 7
The next random code sequence includes a sequence with a period of 127.

Here, as mentioned above, when recording multiple music programs sequentially onto a disc, if there is silence between songs, 2.
In the complement representation, all "0" or all "1" data continues, so when scrambling such data, sufficient consideration is required in selecting a random code sequence. The synchronization pattern is rtotttaoo as described above.
'', it is necessary to select a code sequence that does not produce the same pattern as the synchronization pattern when all other signals except the synchronization signal in one frame are "0" or "1". When data other than the synchronization signal is scrambled, 122 bits out of 130 bits in one frame are scrambled, but in this embodiment, the data words from the 8th bit to the 104th bit in Fig. 4 are scrambled. And Oshi p correction code! A random code sequence that does not generate the same pattern as the synchronization pattern over a t86-bit data sequence is generated by the circuit shown in FIG.

In FIG. 6, 30a to 30g are D-type flip-flops, and flip-flops 301L to 30d are connected in cascade, and the Q output terminal of the flip-flop 30d is connected to one input terminal of a two-man exclusive OR circuit 31. has been done. Further, the output of the exclusive OR circuit 31 is sent to an output terminal 34 via cascade-connected flip-flops 308 to 30g.
, are connected to the data input terminal D1 of the flip-flop 30a and the other input terminal of the exclusive OR circuit 31, respectively. A clock pulse a shown in FIG. 7(A) K enters the input terminal 32 and is supplied to the flip-flops 30a to 30g, respectively. On the other hand, the control signal shown in FIG.
g is applied to the preset terminal. When the control signal goes to H level, the C1 force of flip-flops 30a to 30g goes to L level (logic "0") at the rising edge of clock pulse a.
”), and when the next clock pulse a rises and enters the top 9, only the Q output of the flip-flop 30θ goes to the iEH level (
logic "1"). Then the next clock pulse a
At the rising edge of clock pulse a, each Q output of flip-flops 30θ and 30f becomes H level, and at the rising edge of the next (fourth) clock pulse a, the outputs of flip-flops 300 to 30f become H level.
The Q output of 30g becomes H level. Hereinafter, the fifth time the clock pulse a rises and enters the flip-flop 30f.

Q output of 30g and 30a is H level, 30 on the 6th time
The Q outputs of g, 30a, and 10b are at H level, the Q outputs of 30a to 300 are at H level at the first time, and 3 at the sixth time.
The Q outputs from 0b to 30θ are at H level, and at the 8th time, the q outputs at 300°30d and 30f are each at H level.

Thereafter, in the same manner as above, the outputs of the flip-flops 30a to 30g change every time the clock pulse a rises,
The M sequence code 0 shown in FIG. 7(0) according to the generating polynomial of X1X-1-1 is serially output to the output terminal 34. This M-sequence code 0 is applied to one input terminal of an exclusive OR circuit (not shown), and the M sequence code 0 is applied to one input terminal of an exclusive OR circuit (not shown), and the M sequence code 0 is applied to one input terminal of an exclusive OR circuit (not shown), and is used as a modulo 2 for each "pit" corresponding to the digital signal of the frame structure shown in FIG. 4 to be recorded. A scrambled digital signal is obtained.

Here, if all 96 bits of ah-1 to 0h-4, p, and Q of the input digital signal of the exclusive OR circuit are all "0", the output of the exclusive OR circuit is M The series code C appears as is.

In this case, the value of the output digital signal (ie, M sequence code C) of the exclusive OR circuit is as shown in FIG.

In the figure, the vertical direction shows the bit array, and the top one is MsB (
most significant bit), the lowest is the LSB (
In addition, the horizontal direction indicates each word. The above output digital signal is
Oh, -1 MSB value "0" is output serially in the vertical direction from LSBO value "0", then 0h-2 MSB
is serially output in the vertical direction from the value ``1'' to the LSBO value ``1'', and thereafter is output serially in the same way, and the last 8C bit output is the LSB value of the error correction code Q ``
1”.

As can be seen from FIG. 8, the above M sequence code q is ob
-t~0h-4, P, and Q data are all "0" (
The same applies to the case of "Total of 11"), the same pattern as the synchronization pattern "rlotttooo" is not allowed to exist.

In this way, the digital signal randomized by the M-sequence code 0, which does not produce the same pattern as the synchronization signal, is supplied to the frequency modulation circuit 23 shown in FIG. The signal is recorded on the disk 211 through the signal recording failure shown in the figure. That is, the frequency modulated wave signal is supplied to the mixer 24, where it is mixed with the third tracking signal fpi at the input terminal 25p, and then supplied to the recording device 26 as a main information signal.

The recording device 26 applies the main information signal to, for example, an optical modulator (not shown) to modulate the laser beam and convert it into a modulated optical beam, which is then converted into a disc-shaped recording medium that rotates synchronously at a constant rotational speed. Light is applied to the photosensitive agent coated on the master disc, and through a well-known development process, a main track is formed as a pit row that is intermittent in accordance with the repetition frequency of the main information signal.

Therefore, each digital signal of the four channels will be recorded on the same main track. Note that the tracking signals f and f are input to the input terminals 27 and 211pi.
p2 Okay, connect the input terminal 25 to a different optical modulator (not shown) than the one above.
The third tracking signal fp5 is switched and applied alternately every revolution of the recording master, and similarly modulates the laser light and converts it into a modulated light beam, and then tracks the sub-tracks of the intermittent pit row. It is formed at the same time as the main track. Disc 2B is produced from the recording master through the well-known lid making process.
is replicated.

Note that the random code sequence generated in the present invention may be any code sequence in which the same pattern as the synchronization pattern does not appear when all information data is "0" or "1", so the invention is limited to the above embodiment. It is not something that is done, but
Therefore, the synchronization pattern is the same as above rlollooJ
For example, X'10X'+1, X'10X50X2+X+1,
X+Xi-, x10X+1, X'10X'+! '+42
11 #X7+X +1 ;””z7+x6+x5
The code sequence may be a code sequence generated according to a generator polynomial represented by +x2+, 1, and a - generator polynomial among the generator polynomials that obtain their complementary codes.

As described above, the digital information signal recording method according to the present invention divides a signal obtained by digitally modulating an analog information signal into predetermined sections, and adds a synchronization signal, an error correction code, and an error detection code to each section signal. A randomized digital signal is obtained by adding, modulo 2, the whole of one frame signal or the frame signal part excluding the synchronization signal, and a separately generated random code sequence. When generating the random code sequence, when at least the above section signal and error correction code in the frame signal are all "0" or "1", the random code sequence is generated based on the above section signal and error p-correction code in the randomized digital signal. By selecting a specific code sequence that does not have the same pattern as the synchronization signal, performing randomization, and recording the randomized digital signal on a recording medium after changing the frequency, when this recording medium is played back. , when the information data is all "0", such as silent digital audio data between songs or data during still image data non-transmission period.
” or “1” continues for a period of time,
Even if part of the signal is missing due to dropout or the like, it is possible to reduce the probability that the period in which data is discarded in synchronization with a false synchronization signal as in the conventional method becomes long. This device has features such as being able to perform r data transmission and also being able to simplify the synchronization detection and protection circuit compared to the prior art.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing an example of a disc playback device, Fig. 2 (A) to (0) are time charts for explaining the operation of Fig. 1, and Fig. 3 shows an embodiment of the method of the present invention. 4 is a diagram schematically showing an example of the structure of one frame of a digital signal to be recorded by the method of the present invention, FIG. 5 is a diagram showing an example of the waveform of a synchronization signal, and FIG. 6 is a block diagram. A circuit diagram showing an embodiment of the main part of the method of the present invention, FIG. 7(A)
-(0) are time charts for explaining the operation of FIG. 6, and FIG. 8 is a diagram showing an example of the value of a digital signal recorded by the method of the present invention. 1.29... Disk, 8.31... Exclusive OR circuit, 11-14... Input terminal, 15-18... AD converter, 19... Signal processing circuit, 20... Frame A signal generation circuit, 21... synchronous signal generator, 22... data scramble circuit, 23... frequency modulation circuit, 26...
・Recording device. Figure 7 Two days ago Figure 8 Continued from page 1 0 Inventor Shoji Ueno 3-12 Moriyamachi, Kanayō-ku, Yokohama City, Japan Victor Co., Ltd. Amended Procedures July 27, 1980 1, Case Display Patent Application No. 107389 of 1988 2, Title of Invention Digital Information Signal Recording System 3, Amendment Patent Applicant Address It 22] 3-12 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name ( 432) Japan Victor Co., Ltd. Representative Director and President Michi Shishi - Department 4, Agent 5, Date of amendment order 6, Detailed explanation of the invention in the specification to be amended. 7. In the statement of contents of the amendment, IT2-W+j on page 11, line 20 is changed to [T2
・Correct with W3J.

Claims (1)

[Claims] The signal obtained by digitally modulating an analog information signal is divided into predetermined sections], and a 1-frame signal is constructed by adding a synchronization signal, an error correction code, and an error detection code to each section signal. The entire frame signal part or the frame signal part excluding the synchronization signal and the separately generated random code sequence are each
When generating a randomized digital signal by performing addition modulo A specific code sequence in which the interval signal and the IB correction code in the digital signal do not have the same pattern as the synchronization signal is selected and randomized, and the randomized digital signal is frequency modulated and then recorded on a recording medium. A digital information signal recording method characterized by recording.