JPS6334771A - Digital information signal recording system - Google Patents

Abstract

PURPOSE:To reproduce a compressed digital information signal with high quality by recording digital information signals compressed and multiplexed with time vision by logarithmic conversion and differential pulse code modulating system in a recording medium together with digital data signals formed as line data. CONSTITUTION:Plural digital information signals are converted into compressed sound signals by LOG-DPCM (logarithmic conversion and differential PCM) processing circuits 5 and multiplexed with time division by time division multiplexing circuits 7. On the other hand, digital data signals reproduced by data signal reproducing devices 9 are converted into digital signals synthesized in each serial data by P/S processing circuits 11. Then, digital signals outputted from the circuits 7, 12 are supplied to a format conversion circuit 13 to form a digital signal with a prescribed signal format and record the formed signal in the recording medium 17.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a digital information signal recording method, and particularly to a digital information signal recording method for recording compressed digital information signals together with digital data signals on a recording medium at high density. Regarding.

(Prior Art) Recently, the development of a digital information recording disk (hereinafter referred to as a digital disk) in which high-fidelity audio and still images are converted into digital signals and these digital signals are recorded has been announced and put into practical use.

On the other hand, image data files using video discs have not been put into practical use due to the extremely high price and problems with image quality since the video signals recorded on video discs are analog signals. is problematic.

In order to address these issues, compressed audio systems for digital discs have been developed that take advantage of the high quality of digital signals.

The modulation method of the audio signal recorded on this digital disc is directly PCM (Pu1se Code
HOdlJlatiOn ), and logarithmic ([-0G) compression is performed in the amplitude direction. The sampling frequency was set to 44.1kl to make it easier to handle as an integer ratio with 44.1klz, which is the basic sampling frequency used for conventional digital discs.
There is a 4:1 relationship with respect to z.

FIG. 15 is a diagram showing an example of a signal recording format on a conventional digital disc.

This digital disc has 16 bits per channel (however, the sampling frequency is 44.1
kH, ), of which 10 bits are allocated to compressed audio. 1 and 4 per channel
In order to time-division multiplex and record different types of compressed audio, the sampling frequency of this compressed audio must be 11.025k.
Since it is HA, it is only necessary to send data once every four times. Therefore, 8 compressed voices of 4 types per channel are time-division multiplexed and recorded on the disk, and the identification bit (b
2 bits are assigned to it). Furthermore, the remaining 4 bits other than those mentioned above are used for digital data signals for character data customers.

Also, for example 1. If compressed audio is time-division multiplexed and recorded on the four channels of the digital disc listed in J-, there will be a total of 16 compressed audio channels (4 types per 4 channels), and this disc will be played (played) in normal playback mode. 4 with a sampling frequency of 44.1klz
If the signals are extracted at the Zamble interval (↓x44.1kHz), 16 systems (types) of compressed sound signals can be independently reproduced.

Therefore, normal playback only needs to be performed 16 times to extract all the information recorded on the disc, and if one hour of compressed audio is recorded per channel, the playback time will also be 16 hours.

Also, when recording compressed audio on two of the four channels of the digital disc mentioned above and recording still image data on the other two channels, eight systems of compressed audio can be recorded on two channels. Then, in the other two channels, records corresponding to these eight compressed audio systems are recorded in order, and the identification code (3) in the data header is recorded.
bit) to extract the image corresponding to the audio channel.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a digital information signal recording method that allows digital information signals and digital data signals to be recorded with even higher density on the conventional digital audio disc as described above.

(Means for Solving the Problems) In order to achieve the above object, the present invention compresses digital information signals of $1 loss system by logarithmic conversion and differential pulse code modulation, as shown in FIG. and the means to
means for time-division multiplexing the plurality of compressed digital information signals, means for converting the digital data signal into line data, and converting the time/minute υj multiplexed plurality of compressed digital information signals and the line data; The present invention provides a digital information signal recording system characterized by using means for generating a digital signal in a predetermined signal format from a digital data signal 8 generated by the present invention, and means for recording this digital signal on a recording medium.

(Function) In the digital information signal recording method described above, a digital information signal compressed into a time-division column by logarithmic conversion and a differential pulse code modulation method is recorded on a recording medium together with a digital data signal converted into line data.

(Embodiment) An embodiment of the digital information signal recording method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the digital information signal recording method according to the present invention, and FIG. 2 is an example of a signal recording format on a disk recorded by the recording method configured as shown in FIG. 1. FIG.

In FIG. 1, reference numeral 1 denotes an audio signal reproducing device, which is, for example, a magnetic tape reproducing device or the like which reproduces a magnetic tape recording an audio signal of an analog log. and,
This audio signal reproducing device 1 should be prepared for a maximum of 32 systems so that it can supply audio information for a maximum of 32 systems on a disk having a signal recording format as shown in FIG. become.

In other words, as shown in Figure 2, on the disk there is 1 Gbit per channel in the data recording direction (vertical direction in the figure) (however, the sampling frequency is 44.1kHz).
z) (hereinafter, this channel will be referred to as Chl, 2.3.4), and one channel is further divided into two by the upper 8 bits and the lower 8 bits. , there are four types for the upper and lower levels of each channel (ch1 to 4) in the length direction of the track (horizontal direction in the figure) (with the upper levels being A, B, C, and D,
The compressed audio of the lower order is E, F, G, H) is time-division multiplexed and recorded. Therefore, a total of 32 systems (
This means that it is possible to record compressed audio of various types.

In addition, in FIG. 2, 32 systems (types) of compressed audio are represented, for example, the top four types of chl are IA.

Indicated by IB, 1C, ID, and the lower four types of Chl are IE
, IF, 1G, and 1H, and channels 2 and 3°4 are similarly shown as shown.

In addition, in Fig. 2, the upper and lower parts of each channel are composed of 8 bits, of which compressed audio is recorded in 7 bits, and the least significant bit of these 7 bits (L
A digital data signal is recorded in the 1 bit following SB). Furthermore, as will be described later, this digital data signal is line data having a length such that one packet unit (midblock) of data is completed in one track (one round of the track). It is configured.

Here, the explanation will be given again by returning to the block system diagram shown in FIG.

In Fig. 1, as mentioned above, the fame (No. 8 endogenous device 1) must be prepared for a maximum of 32 systems, but chi.~4 has a similar configuration, so in the same figure, chl upper and upper 8 systems (1A, IB, 1G,
10 and IE, IF, IG.

IH> is illustrated. In addition, the upper four systems and the lower four systems of each desennel have the same configuration, and each of the upper or lower four systems also has the same configuration except for a part, so below we will focus on The 1A system above chl will be explained below.

The analog audio signal reproduced by the audio signal reproduction neck device 1 is passed through a low-pass filter (LPF) 2 for preventing area synchronization.
By passing only signals in the frequency band below the sampling frequency, aliasing noise is prevented. Digital) conversion: supplied to W4, where it is converted into a digital audio signal. This digital audio signal is converted into LOG-DPCM (logarithmic conversion and differential PCM).
) is supplied to the LOG-DPCM processing circuit 5, where it is subjected to logarithmic compression and differential PCM processing to form a 7-bit compressed audio signal. Note that the sampling frequency at this time is equal to 1 of the sampling frequency fs at J3 in the sample and hold circuit 3.

The 7-bit compressed audio signal output from the LOG-DPCM processing circuit 5 is sent to the MSB inversion circuit 6 at J3, where the least significant bit (MSB) of the 7-bit compressed audio signal (digital signal) is processed.
B) is inverted and supplied to the time division multiplexing circuit 7.

However, this MS8 inversion circuit 6 is provided in the A system of the upper four systems (A, B, C, D) of each channel and the lower four systems (E, F, G, l-
1> is only the E strain.

Here, the reason why only the 8th and E systems are inverted is to distinguish the A and E systems from other systems. In other words, only these 8 and E systems have specific data (binary 2
'1000000' (complement representation of '1000000') will appear, and as will be described later, this specific data will be prohibited from appearing in other systems, and so-called landmarks (specific data) will be placed only in the 8 and E systems. Therefore, it is possible to detect the A and E strains. Since the data are recorded repeatedly in a fixed order, it is also possible to detect other systems.

In addition, for systems other than the above channels and the E system, the 7-bit 1- compressed audio signal output from the LOG-DPCM processing circuit 5 is converted into 7-bit compressed audio signal by the bit conversion circuit 8. Binary 2's complement representation of the signal (digital signal) c7) "1000000" (7)
data') is bit-converted to "1000001", and as mentioned above, the specific data (1
000000'') is prohibited.

In other words, "1000000" in binary two's complement representation
That is, it is the same as inverting the MSB of the binary representation data "" o o o o o o o" indicating the pyro level of the audio signal, and this is inverted by the MSB inverting circuit 6 in systems A and E. Indicates a pillow-level audio signal that frequently appears in normal audio signals' o o o o
It is the same as the above-mentioned landmark specific data that appears by reversing the MSB of "o o o", so in systems other than the 8 and E systems, "1o o o o o o
” data is bit-converted to 1000001 ” and “
1000000" is prohibited.

Therefore, by detecting the appearance of "1000000", it is possible to detect the A and E strains, and furthermore, if the A or E strain is detected, other strains can be detected following the A or E strain. Since the data are repeatedly recorded in a fixed order, it is also possible to detect other systems. In addition, since there is no need to provide a special detection bit for detecting the A and E systems, the number of pins can be saved, and
It is possible to take extra bits for the reduced name signal, and the quality of the reproduced audio can be improved.

The 7-bit compressed audio signals other than the A system (or the E system) that have been bit-converted by the bit conversion circuit 8 as described above are supplied to the time division multiplexing circuit 7.

In the time division multiplexing circuit 7, the 7-bit compressed audio signal of the A system (or the E system) supplied from the MS8 inverting circuit 6 and the 7-bit compressed audio signal of the A system (or the E system) supplied from the MS8 inverting circuit 6
The bit compressed audio signal is A.

Time division multiplexing is performed in the order of B, C, and D systems, and A.

The 7-bit compressed audio signals of each system B, C, and D are time-division multiplexed and output at a transmission rate of 11.025 kHz.

On the other hand, 9 is a data signal reproducing device, which is, for example, a device such as a magnetic disk reproducing device that reproduces a magnetic disk on which digital data signals are recorded. The 8-bit digital data signal Q(D) reproduced by this data signal reproducing device 9 is supplied to a data processing circuit 10,
The data processing circuit 10 generates and outputs a digital signal synthesized in a time-series manner in packet units (block units) in a signal format as shown in FIG.

Here, in the signal of 1 packet 1- shown in FIG.
APl, GAP2. GAP3 C NULL DATA
(Invalid data) SOP (SYNCC0DE
OFP to C), Son (SYNC
COD [: or DATA), EOP (EN
D C0DE OF PACKET) [The beginning of packet 1- and the beginning of data.

The positions of fixed pattern synchronization signals each indicating the end of a packet are shown. 10 ([DENTIFICAT
ION) is identification data, P, , (PARITY
OF 10) indicates the arrangement position of the error correction parity of ■0. Also, Do~D (DATA) is a data signal, P o ”-P 15 (P^Old TV OF DAT
A) shows the arrangement position of the data error correction burr 1.

The constituent parts of one packet described above are composed of the number of numerical bytes (BYTE) as shown in the figure, and the total number of bytes is 294 bytes. One byte consists of 8 bits (= 2 nibbles) of actual content, as described below.
Before the 1st bit of the 8 bits (that is, before the upper nibble) and between the 4th and 5th bits of the 8 bits (in other words, between the upper nibble and the lower nibble) One byte is made up of 10 bits by adding one bit at a time.
The packet signal is 2940 bits (=294x10)
This data length corresponds to 1-rack for one rotation of the disk. .

FIG. 4 is a diagram showing the signal format of the identification data 10, and FIGS. 5, 6, and 7 are identification data rov constituting the identification data 10.

It is a diagram that does not show the signal format of channel data C11 and flag data FLOG. One piece of data for identification is I
It consists of 10 bytes of Q, ~[Dg.

Identification data in Figure 5 ■In the IDV of 0, normally (
N0IIHA1. ) then °' o o o o o
When the configuration of the identification data 10 is changed, data "0OO00001" to "11111111" are recorded in order to distinguish them sequentially.

In the channel data C1+ of FIG. 6, the 4.5th bit out of the 8 bits is used to select the channels of Chi~4 to identify four types of channels from "00pa~"11'''. The 6th to 8th bits of the 8 bits are used to select the A to H system of each channel, and
Eight types of strains from ``o'' to ``111'' are identified.

In the flag data FLOG in FIG.
n IPAC to ET), DC (roΔ■^ C0NTI
NUE PACKET), Kano (D to Ding A [8
0PACKET), these indicate whether each packet is a single packet, a starting packet, an ending packet, or a series of N packets. For example, "101" indicates a single packet, and "iio" indicates a starting packet. That is,"
010'' indicates a continuing packet;
” is the last packet, “o o o
” indicates a blank (data 1) packet.

Also, 80OR (Relation Address
ss or eachchannels) is the address of any position of each channel (system), PRL
(pHOf[CdingLEV[L) andhiPItC(P
ItOTECT COD[) indicates the level and code of the data protection area, and REV (Reserve) indicates reserved data.

Furthermore, as mentioned above, each byte of the 11 packet signal shown in FIG. That is,
” - in front of the second bit) and the 4th and 5th bits behind the 8 bits
One bit is added between each bit (that is, between the upper nibble and the lower nibble) so that 1 byte becomes 1 bit.
It is configured to consist of 0 bits, but the added 2-bit data is SOP as shown in Figure 8.
, S.O.D.

Data "1" is added to EOP, and as shown in FIG. 9, data "O" is added to SOP, SOD, and others other than EOP to distinguish them. This makes it possible to prevent the signal of one packet shown in FIG. 3 from shifting in the h direction of the track length when detecting sop, soout, and EOP.

As described above, the data processing circuit 10 in FIG.
, generates a data signal in the signal format shown in Figure 3, and converts it into parallel/serial (P/S).
) The processing circuit 11 converts the 8-bit parallel data into 1-bit serial data, and then the timing circuit 12
The compressed audio signal chl output from the time division multiplexing circuit 7 is output (44, 1k)l, ).
The output timing is controlled so that the beginning of one packet 1- in FIG. 3 is output. The 1-bit data signal (line data) output from the timing circuit 12 and the 7-bit compressed audio digital signal output from the time division multiplexing circuit 7 are converted into a white 18-bit digital signal, and 8-bit digital signal and chi
A total of 8 bits of digital signals outputted from the time division multiplexing circuit 7 and the timing circuit 12 of the E-H system are supplied to the format conversion circuit 13 as a 1 Gbit digital signal (chl). .

In addition, channels 2 to 4 have the same configuration as CH, and a total of 11 Gbit digital signals (ch2, 3.4) are transmitted from each channel to format i.
The signal is supplied to the conversion circuit 13.

The format conversion circuit 13 generates and outputs a digital signal synthesized in time series in block units of the known signal format shown in FIG. 10 for digital discs.

Here, at the signal J3 of one block shown in FIG. 10,
S indicates the placement position of a fixed pattern synchronization signal of 8 pins 1- indicating the start of a block. chl.

ch2. ch3 and ch4 each indicate the arrangement position of one word of the 16-bit digital signal of one channel among the four channels.

Further, P and Q shown in FIG. 10 are approximately 16-bit error correction codes. Furthermore, the CRC is a 23-bit error code and a positive code for chi to ch4 . P
, Q(7) Each '7-de, for example, t is X73+X5+X'
This is the 23-bit remainder obtained when dividing by the generator polynomial +x+1, and when the signal from the 9th bit to the 121st bit of the same block is divided by the above generator polynomial during playback, the remainder obtained is It is used to detect that there is no error in the case of pyro.

Furthermore, in FIG. 10, Adr is one of various control signals (address signals) used for random access, etc.
Indicates the 5-level position of the bit. This control signal distributes each bit data and is transmitted one by one in one block. For example, all bits of the i control blade 8 are transmitted by 196 blocks (that is, the control signal is composed of 196 bits). ).

Furthermore, U is 2 bits for backup called user's bits, and for example, you can connect a computer to the playback system and play it interactively! Transmits the language for performing IJRI. Then, from S to U shown in FIG.
A total of 130 bits constitute one block of signals, and the digital signals are synthesized in block units at a frequency of 44.1 KHz and transmitted in time series. 19 above
The 6-bit control u signal has a configuration in which four types of address codes of 49 bits each are synthesized in chronological order, and these four types of seven address codes are all in the same signal format 1~. .

The digital signal extracted from the format conversion circuit 13 in block units in the signal format as shown in FIG. 10 in time series is scrambled NRZ as shown in FIG.
The signals are supplied to the modulator 14, where the signals other than the 8-bit synchronization signal are converted into signals from a preset random number table (
For example, the signal is subjected to scrambled NR7 modulation using modulo 2 (M-sequence code) and modulo-2 modulation, and is then supplied to the FM modulation circuit 15. The frequency-modulated digital signal taken out from the FM modulation circuit 15 is supplied to a recording device 1G such as a known cutting machine, and after being converted into a modulated light beam, a disc-shaped recording source! The photosensitizer on 817 is focused and irradiated.

By passing this disk-shaped recording master disk 11 through a known development process and a J disk process, a large number of disks ('F digital disks) can be reproduced.

Note that it is of course possible to record on a recording medium other than a disc.

Furthermore, in the disk shown in FIG. 2, there are four systems (A, B, C) in the time division direction for each channel.

D or E, F, G, H) and compress each series at a limp ring frequency of 11.025 kHz, which has an integer ratio of 4:1 to 44.1 kHz, which is the standard limp frequency for digital discs. Although we have explained the case where 8 voices are recorded so that 8 voices can be extracted, it is also possible to extract compressed voices of each series at sampling frequencies that have a reference rimbling frequency of 5=1 or other integer ratios such as 6:1. Of course, it is also possible to record each channel by dividing it into five or six systems in the time division direction, and as shown in FIG. (an integer of ), and 1/n-
It is sufficient to record the compressed audio of each series so that it can be extracted at the reference sampling frequency of fs.

Furthermore, even if digital signals consisting of compressed audio and digital data are not recorded on all four channels of a disc, two of the four channels (
Alternatively, the image data may be recorded on only one channel or three channels, and image data may be recorded on the other channels.

Next, a reproduction method for reproducing a recording medium (disk) recorded by the above-described digital information signal recording method according to the present invention will be described below with reference to the drawings.

FIG. 12 is a block diagram of an example of a digital information signal reproducing system, FIG. 13 is a configuration circuit diagram of the exponential conversion and addition Q circuit 37, and FIG. 14 is a timing chart of latch pulses generated from the timing signal generation circuit 29. be.

In FIG. 12, 21 is a player, 22 is an FM [1 circuit, 23 is an error correction circuit, 24 is a channel selection circuit,
25 is a Ch1-4 selection circuit, 26.34 is a serial/parallel (S/P) conversion circuit, 27 is an upper/lower selection circuit, 28 is an A (or E) system detection circuit, 29 is a timing signal generation circuit, and 30 is a Select signal generation circuit, 3
1 is an MS8 inverting non-inverting circuit, 32 is a latch circuit, 33 is a read timing circuit, 35 is a data processing circuit, 36
is a data output terminal, 37 is an exponent conversion and addition circuit, 38
is a D/A converter, 39 is a DC cutoff circuit, and 40 is an analog signal output terminal.

The channel selection circuit 24 is a channel selection circuit 2
5. S/P conversion circuit 26. Upper/lower selection circuit 27゜A
(E) System detection circuit 28. Timing signal generation circuit 29
．． Select signal generation circuit 30. MSB inverting non-inverting circuit 3
1. It consists of a latch circuit 32.

Next, the operation of the block system diagram shown in FIG. 12 will be explained.

For example, the second
A digital disc with a signal format as shown in the figure (
The FM digital signal reproduced from the player 21 (not shown) is supplied from the player 21 to the FM demodulation circuit 22, where it is FM demodulated, and then supplied to the error correction circuit 23, where descrambling and decoding error correction are performed. 1°, this reproduced digital signal becomes a reproduced digital signal of the signal format shown in FIG.
hi~4 is supplied to the select circuit 25, where it is supplied to the channel select 1 from the select signal generating circuit 30 in accordance with the signal.
The reproduced digital signal of any one of the four channels (hereinafter abbreviated as "ch") from chi to ch4 is selected. The select signal generating circuit 30 is connected to a channel select button (not shown) of the playback device, and is configured such that a select signal is supplied by operating the select button.

The 1-bit reproduced digital signal output from the ch1-4 select circuit 25 is supplied to the S/P conversion circuit 2G, where it is converted into a 16-bit reproduced digital signal, and then supplied to the upper and lower select circuit 27, where it is The 16-bit reproduced digital signal is divided into a reproduced digital signal of the upper bits (1st to 8th bits) and a reproduced digital signal of the lower bits (9th to 16th bits). Of this reproduced digital signal, the reproduced digital signal of the last 1 to 7 bits of the upper bits (or the 9 to 15 bits of the lower bits) is supplied to the A (E) system detection circuit 27 and the MS8 inverting and non-inverting circuit 31. Furthermore, the reproduced digital signal of the 8th bit of the upper bits (or the 16th bit of the T bits) is supplied to the readout timing circuit 33, where the simbling frequency fs (44, 1k) is lz)
After being read out, the data is supplied to the S/P conversion circuit 34, where it is converted from 1-bit serial data to parallel data, and the data processing circuit 35 performs predetermined processing (for example, channel identification, error corrections, etc.)
The digital data is output from the data output terminal 36.

On the other hand, the Δ(E) system detection circuit 28 detects the supplied upper (
Alternatively, when the reproduced digital signal of 7 bits l~ of the lower bits is specific data of the A system (or E system), this is detected and a detection signal is supplied to the timing signal generation circuit 29. Timing signal generation circuit 9 receives this detection signal and sends a latch pulse shown in FIG. 14 to latch circuit 32.

The timing signal generation circuit 29 is the select signal generation circuit 3
Pulses a to d shown in FIGS. 14(A) to 14(D) are sent out in response to select signals of the A to D systems from 0 to 14, respectively.

On the other hand, when the A system (or the E system) is selected and a signal is output from the select signal settling circuit 30 to the MSB inverting/non-inverting circuit 31, the polarity of the MSB of this signal is inverted. Further, when a system other than the A system (or the E system) is selected, the polarity of the MSB of the signal is not inverted here.

The output signal from the MSB inverting non-inverting circuit 31 is sent to the wrap circuit 32, where the timing signal generating circuit 29
After being latched with the latch pulse applied to each system as shown in FIG.
After being converted into an analog playback signal as a 6-bit signal by the D/A converter 38, it is passed from the analog signal output terminal 40 to the 1
4 cow analog signals are output.

In the manner described above, a reproduced analog signal such as an audio signal is reproduced from a digital disc recorded using the above-described recording method.

Here, the role of the above-mentioned exponent conversion and addition circuit 37 is as follows.
Logarithmic conversion (signal compression) and differential PCM recording signals are inversely converted to return to the original (C') signal, and the reference level of the reproduced signal is varied to keep its amplitude level within a predetermined amplitude level range. The goal is to keep it within the range.

The above-mentioned index conversion and addition circuit 37 is configured as shown in FIG.

In the figure, 41 is an index conversion circuit, 42 is an addition circuit,
43 is a latch circuit, 44 is a data selector, 45 is a latch circuit, 46 is an EX-OR circuit, and 47t is an inverter circuit.

Next, the operation of the exponent conversion and addition circuit 37 will be explained.

The reproduced digital signal from the latch circuit 32 described above is supplied to the exponential conversion circuit 41, where it is expanded exponentially, and the logarithmic conversion curve is opposite to the logarithmic conversion curve in the LOG-DPCM processing circuit 5 in the recording method shown in FIG. The reproduced signal is inversely transformed using an exponential curve of characteristics.

Furthermore, this signal is supplied to an adder circuit 42, and the output signal from the adder circuit 42 is further supplied to a latch circuit 43,
After being held for a time of 1/fs (fs is the sampling frequency), it is supplied to one input A side of the data selector 44.

The data selector 44 has the -h input A side supplied with the output signal from the latch circuit 43 as described above, the other input B side supplied with a signal to be described later, and the other input B side of the data selector 44. The signal supplied to the EX-OR circuit 46 is output only when the control signal is output from the EX-OR circuit 46.

Further, the output signal from the data selector 44 is supplied to another latch circuit 45, where it is latched and then supplied to the D/A converter 38 at a required timing.

Here, in the above circuit, normally (that is, when the reproduced signal from the adder circuit 42 is within a predetermined amplitude level range), the data selector 44 is switched to one input A side, and the latch The output signal from the circuit 43 is supplied (feedback) to the addition circuit 42 via the data selector 44, where it is added to the new reproduction signal from the index conversion circuit 41, and then this signal is held in the latch circuit 43. Ru.

Then, the signal supplied (feedback) from the data selector 44 and the new reproduction signal from the index conversion circuit 41 are sequentially added by 1°, but the reproduction signal from the latch circuit 43 exceeds a predetermined amplitude level range. When the output level reaches the specified level (in other words, the upper 2 bits (15, IG) of the 16-bit reproduced signal) are set as the level over-detection bits, and when these 2 bits match (“00” indicates a certain ,t ” 11 ”
(7) time)), EX-OR [ili] road 46/l”
l i! +' control signal is output and the data selector 44
The signal supplied to the other human power B side is output.

This signal is used to vary the reference level of the reproduced signal so that its amplitude level falls within a predetermined amplitude level range.

As described above, the signal from the input B side of the input terminal 1 of the data selector 44 is supplied to the addition circuit 42, where it is added to the new reproduced signal from the index conversion circuit 41.

After this, when the signals of the 15th and 113rd bits, which are the excessive level detection bits supplied to the EX-OR circuit 46, do not match, the Ll+ control signal from the EX-OR circuit 46 is no longer output, and this causes the latch The reproduced signal held in the circuit 43 is added via the data selector 44.
The signal is supplied to the circuit 42, where it is added to the reproduction signal from the index conversion circuit 41, and the signal supplied (feedback) from the data selector 44 and the new reproduction signal from the 1-bacteria count conversion circuit 41 are sequentially added. Added. .

In this way, the exponential conversion and addition circuit 37 converts the logarithmically converted (signal compression) and differential PCM-converted playback signal into an original signal, and when the level of the playback signal is excessive, it can bring it into an appropriate state. can.

(Effects of the Invention) As described above, according to the digital information signal recording method of the present invention, logarithmic conversion and differential pulse code modulation (LOG-D
Since the digital information signal compressed and time-division multiplexed using the PCM) method is recorded on the recording medium together with the digital data signal converted into line data, the compressed digital information signal can be reproduced with high quality, especially conversational audio. Since the reproduced audio becomes clearer and a digital data signal is also recorded at the same time, this data signal can be used to control the operation of the player and various devices. It has the advantage that there is no need to provide a special auxiliary storage device (memory) for recording such control data signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the digital information signal recording method according to the present invention, and FIGS.
A diagram showing an example of a signal recording format on a disc recorded by a recording method having the configuration as shown in the figure, and FIG. 3 shows an example of a signal format of one packet of a digital data signal recorded on a disc. Figures, Figures 4-9
The figure shows an example of each format constituting the signal format of one packet shown in Fig. 3, Fig. 10 shows an example of the signal format of one block of a digital signal recorded on a disk, and Fig. 12 shows an example of the signal format of one block of a digital signal recorded on a disk. FIG. 13 is a block diagram of an example of a digital information signal reproducing system. FIG. 13 is a configuration circuit diagram of an exponent conversion and addition circuit. FIG. 14 is a timing chart of wrap pulses generated from a timing signal generation circuit. FIG. 15 is a conventional digital FIG. 2 is a diagram showing an example of a signal recording format on a disc. 1...Audio signal reproducing device, 2...Low bass noise filter. 3... Ripple hold circuit, 4... A/1] conversion tube. 5-LOG-DP CM processing circuit, 6...MS
8 inverting circuit, 7... time division multiplexing circuit, 8... bit conversion circuit, 9... data signal reproducing device, 10...
・Data processing circuit, 11... Parallel/serial processing circuit, 12... Timing circuit, 13... Format conversion circuit, 14
... Scrambled NRZ modulation, 15... FM modulation circuit, 16... Recording device, 17... Recording master. Hiro"
2) Age 61] 70 ding T T
-111'/-f・saiyf group 1,15m procedure netti official book October 1986 C3b day! , @ft Display Patent Application No. 177152 of 1985 2 Name of Invention Detei Tal Information Signal Recording System 3 ? l1iii'Thoughts to make = C matter Which relationship Patent applicant 11 places 3] Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture 12-4.71! 81 inch spontaneous correction of iiF command! ``Detailed explanation of the invention and drawings'' in Specification 71-1 of ``Li Publishing'' n-. Correct “mo” with “ha”. (2) Same, page 15, line 4 and page 15, line 20 r
Correct FLOGJ to “FLAGJ.”
Correct J to 'i' channel J. (4) Same, page 16, line 13, “Okino” is changed to “Oki no 1”
and correct it. (5) Same, page 24, line 20, "tono" is replaced with "toshiri i'"
). (6) Same as above, in the first line of page 25, ``Bit no'' is corrected to ``E bit parallel''. (7) Same, page 28, line 20, “control signal”
1'3 select signal". (8) Same as above, correct the first line of page 30 to ``Do not add 1-5 · to the matched j''. (Huh) Correct r'' o o°'-1 in the first line of page 30 to M'01''. (10) Correct "'11°'" in the second line of page 30 to "1゛10". (11) “Control signal” on page 30, lines 2 to 3 of the same page
is corrected as "B select signal". (12) "When they no longer match" on page 30, lines 13 to 14 of the same page is corrected to "when they match." (13) In the same page 30, lines 14 to 15, "the control signal is no longer output" is corrected to "the A select signal is output". (14) The drawings, Figures 4 and 7 will be corrected as shown in the attached sheet. From the above, k4. Record

Claims (1)

[Scope of Claims] A means for compressing a plurality of systems of digital information signals by logarithmic conversion and a differential pulse code modulation method, a means for time-division multiplexing the compressed digital information signals of a plurality of systems, and a digital data signal. means for generating a digital signal in a predetermined signal format from the plurality of time-division multiplexed compressed digital information signals and the digital data signal converted into line data; A digital information signal recording method characterized by using a means for recording on a recording medium.