JPS6351647A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6351647A JPS6351647A JP19592386A JP19592386A JPS6351647A JP S6351647 A JPS6351647 A JP S6351647A JP 19592386 A JP19592386 A JP 19592386A JP 19592386 A JP19592386 A JP 19592386A JP S6351647 A JPS6351647 A JP S6351647A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- resin
- semiconductor element
- semiconductor device
- silica powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 23
- 239000000057 synthetic resin Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000843 powder Substances 0.000 claims abstract description 15
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 15
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 10
- 238000000465 moulding Methods 0.000 claims description 21
- 229920005989 resin Polymers 0.000 abstract description 29
- 239000011347 resin Substances 0.000 abstract description 29
- 238000007789 sealing Methods 0.000 abstract description 18
- 239000003822 epoxy resin Substances 0.000 abstract description 7
- 229920000647 polyepoxide Polymers 0.000 abstract description 7
- 238000001721 transfer moulding Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 230000005587 bubbling Effects 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000008646 thermal stress Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は２回のトランスファーモールドにより熱硬化性
合成樹脂で封止された半導体装置を製造する方法におい
て、半導体素子に熱応力が作用しにり）シ且つ耐湿性を
向すさせるために、シリカ粉高充填合成熱硬化性樹脂を
使用し、最初の成形を上記樹脂がスムーズに充填される
形状の金型を使用して行なうようにしたものである。[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a semiconductor device sealed with a thermosetting synthetic resin by two transfer molding processes, in which thermal stress is applied to the semiconductor element. In order to improve moisture resistance, a synthetic thermosetting resin highly filled with silica powder is used, and the initial molding is carried out using a mold shaped so that the resin can be smoothly filled.
本発明はず導体装置の製造方法、特に半導体素子を熱硬
化性合成樹脂により封止しｌζ半導体装置の製造方法に
関する。The present invention relates to a method for manufacturing a conductor device, and more particularly to a method for manufacturing a semiconductor device by sealing a semiconductor element with a thermosetting synthetic resin.
この種の半導体装置は、第１に半導体素子がこれを封止
する合成樹脂により熱応力を作用されないこと、第２に
耐湿性に優れていることが必要とされる。This type of semiconductor device requires, firstly, that the semiconductor element is not subjected to thermal stress by the synthetic resin used to seal it, and secondly, that it has excellent moisture resistance.
半導体素子が合成樹脂で封止された半導体装置を製造す
る方法の一つとして、２回のトランスファーモールドを
行ない、第１回目には半導体素子を封止し、第２回目に
半導体装置の外形形状を形成するようにした製造方法が
知られている。As one method for manufacturing a semiconductor device in which a semiconductor element is encapsulated with synthetic resin, transfer molding is performed twice, the first time encapsulating the semiconductor element, and the second time molding the external shape of the semiconductor device. There is a known manufacturing method for forming.
特に第１回目の成形は、￥尋体素子、内リード。In particular, the first molding was for the ¥300 body element and inner lead.
及び両者間に配線された複数のＡＵ線を包囲するように
行なわれるものであり、Ａ ＵＦＪはキ１１ごティ内に
流入１６合成樹脂により力を作用され、損傷し易い。This is done so as to surround a plurality of AU wires wired between the two, and the A UFJ is easily damaged by the force exerted by the synthetic resin flowing into the key 11.
従来の第１回目の成形に使用される金型は、ゲートが同
幅のま）キャピテイに到り、且つキ１νビテイも角ばっ
た形状であった。In the conventional mold used for the first molding, the gate had the same width until reaching the cavity, and the width was also square.
また合成樹脂としては、ＡＵ線を石勾しにくいように、
流動性の良い合成樹脂が使用されていた。In addition, as a synthetic resin, it is difficult to make the AU line rough.
A synthetic resin with good fluidity was used.
〔発明がｗｌ決しようとり−る問題点〕第１回旧の成形
時に、合成樹脂は狭いゲートを通った後急に広いキャビ
ティ内に広がり、しかも主１１ビテイが角ばった形状で
あるため、合成樹脂Ｇ、ｔ ４＝ヤビデイ内で比較的激
しく流動１−る。このため、流動性の良い合成樹脂を使
用したとしても、上記激しい流動により、Ａ ｔＪ線は
大なる抵抗力を受けて帽Ｉることかあり、完成した半導
体装置が不良品となってしまうこともあるという問題点
があった。またキャビティが角ばった形状て゛あるため
、キャビティの容積は大きく、それだけ多くの合成樹脂
がキャビティ内に流れ込んでＡＵ線の近傍を流動する。[Problems that the invention is trying to solve] During the first molding process, the synthetic resin suddenly spreads into a wide cavity after passing through a narrow gate, and the main 11 bits have an angular shape. Resin G, t4=flows relatively vigorously in Yavidi. For this reason, even if a synthetic resin with good fluidity is used, the A tJ wire may be subject to a large resistance force due to the above-mentioned intense flow, and the completed semiconductor device may become a defective product. There was also a problem. Further, since the cavity has an angular shape, the volume of the cavity is large, and a large amount of synthetic resin flows into the cavity and flows near the AU line.
このこともＡＵ線を損傷する一因となっていた。This also caused damage to the AU wire.
また合成樹脂の上記の比較的激しい流動により、微小な
泡が樹脂内に発生していた。Further, due to the above-mentioned relatively intense flow of the synthetic resin, minute bubbles were generated within the resin.
また、合成樹脂が比較的激しく流動し易い上記の金型を
使用しているため、合成樹脂としては、Ａｕ線の損傷を
出来るだけ抑えるように、流動性の良いものを使用せざ
るを１！？ず、封止に最適な樹脂を使用することが出来
ないという問題点もあった。In addition, since the above-mentioned mold is used in which the synthetic resin tends to flow relatively violently, it is necessary to use a synthetic resin with good fluidity in order to prevent damage to the Au wire as much as possible! ? First, there was a problem in that it was not possible to use the most suitable resin for sealing.
本発明は、４′導体素子を熱硬化性合成樹脂により該半
導体素子及びこれに接続されたワイｔ ｅ包囲ｊるよう
に１回目の成形を行ない、次に半導体装置の外形形状を
形成する２回目の成形を行なって半導体装置を製造づ−
る方法において、上記１回目の成形を、上記半導体索子
を囲む曲面状のキャビティと、ゲートより該キャビティ
に向かうにつれて幅広となるバスとを有する形状の金型
を使用し、熱膨張係数が半導体素子のそれに近似したシ
リカ粉高充填熱硬化性合成樹脂を使用して行なうように
したものである。In the present invention, a 4' conductor element is first molded using a thermosetting synthetic resin so as to surround the semiconductor element and the wires connected thereto, and then the outer shape of the semiconductor device is formed. Perform the second molding to manufacture semiconductor devices.
In this method, the first molding is performed using a mold having a curved cavity surrounding the semiconductor cord and a bus that becomes wider from the gate toward the cavity, and has a coefficient of thermal expansion of the semiconductor. This is done by using a thermosetting synthetic resin highly filled with silica powder that is similar to that of the element.
（作用〕
上記の金型のうち、キトビティに向かうにつれて幅広と
なるバスは、キャビティ内に流入する樹脂の流動をスム
ーズにする。曲面状のキャピテイはキャビティの容積を
最小とし、キ１７ビデイ内に充填される樹脂の置部らワ
イヤ近傍を流動する樹脂の４を最小とし、流動性の良く
ないシリカ粉高充填樹脂の使用を可能とづる。(Function) Among the molds mentioned above, the bus, which becomes wider as it goes toward the mold, smoothes the flow of resin flowing into the cavity.The curved cavity minimizes the volume of the cavity, This minimizes the amount of resin flowing in the vicinity of the wire from where the resin is filled, making it possible to use a resin highly filled with silica powder, which does not have good fluidity.
第１図（Ａ）、（Ｂ）は本発明の一実施例になる半導体
装置の製造方法の第１回目の封止成形を説明する図、第
２図（Ａ）、（Ｂ）は第２回目の封止成形を説明する図
、第３図は本発明の製造方法により￥Ａ造された半導体
装置１を示す図である。FIGS. 1(A) and (B) are diagrams for explaining the first sealing molding of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(A) and (B) are diagrams for explaining the second FIG. 3, which is a diagram illustrating the second sealing molding, is a diagram showing the semiconductor device 1 manufactured by the manufacturing method of the present invention.
第１図（Ａ）、（Ｂ）は第１回目の封止成形用金型２を
示す。この金型２は上型３と下型４とよりなる。FIGS. 1(A) and 1(B) show the mold 2 for sealing molding for the first time. This mold 2 consists of an upper mold 3 and a lower mold 4.
５は４−ヤビティであり、上型３の凹部６と下型４の凹
部７とが組み合わされてなり、輻平な円板形状の空間で
ある。キャビティ５の径りは、４ヤビデイ５内に半導体
素子８．半導体索子８が載置されるステージ９．一端が
半導体８にボンディングされた複数のＡＵね１０．複数
のり一ド１１のうちの内リードｉｌａに対する上記△（
」線１ｏの伸悩のボンディング部を収容するのに要する
最小寸法に定めてあり、キャピテイ５はこれらを収容す
るのに要する最小容積としである。5 is a 4-yavity, which is formed by combining the recess 6 of the upper mold 3 and the recess 7 of the lower mold 4, and is a flat disk-shaped space. The diameter of the cavity 5 is such that a semiconductor element 8. A stage 9 on which the semiconductor cord 8 is placed. A plurality of AU wires 10, one end of which is bonded to the semiconductor 8. The above △(
The capacitance 5 is defined to have the minimum size required to accommodate the bonding portion of the tension wire 1o, and the cavity 5 has the minimum volume required to accommodate these.
１２はランナ、１３はゲート、１４はエアベントである
。12 is a runner, 13 is a gate, and 14 is an air vent.
１５はバスであり、ゲート１３と４ヤビテイ１５との間
に延在形成しである。パス１５は、第１図（Ｂ）に示す
ようにキャビティ１５に向かうにつれて幅広とされた扇
形状であり、Ｗｚ＞Ｗ＋である。15 is a bus extending between the gate 13 and the fourth cavity 15. The path 15 has a fan shape that becomes wider toward the cavity 15, as shown in FIG. 1(B), and Wz>W+.
第２図（△＞、（Ｂ）は、第２回目の封止成形用金型２
０を示す。この金型２０は、上型２１と下型２２とより
なり、内部には第３図の半導体装置１の外形形状に対応
するキャビティ２３が形成しである。２４はランナ、２
５はゲートである。Figure 2 (△>, (B) shows the second sealing mold 2
Indicates 0. This mold 20 consists of an upper mold 21 and a lower mold 22, and has a cavity 23 formed therein corresponding to the external shape of the semiconductor device 1 shown in FIG. 3. 24 is runner, 2
5 is a gate.
次に上記の金型２，３０を使用して行なう１１止成形に
ついて説明する。Next, the 11-stop molding performed using the molds 2 and 30 described above will be explained.
封止のための合成樹脂としては、熱膨張係数がエポキシ
樹脂より小さいフィラー（例えばシリカ粉末）が７５〜
９０重吊部と高充填されたエポキシ樹脂を使用する。こ
の樹脂は、上記シリカ粉が高充填されていることにより
、熱膨張係数が半導体素子８の熱膨張係数に極めて近（
、熱応力の点で従来の樹脂より優れている。また、シリ
カ粉が高充填されていることにより吸湿呈が減少し、実
装時半田耐熱＋ｉ（パッケージ割り及び、樹脂とリード
フレーム界面の剥離等）が向トする。結末として、耐湿
性が改良される。しかし、シリカ粉が高充填されている
ため、流動性が悪く、成形には遺さないが、この問題は
第１図（Ａ）、（Ｂ）に示す金型２を使用することによ
り以下に述べるように解決している。As a synthetic resin for sealing, a filler (for example, silica powder) whose coefficient of thermal expansion is smaller than that of an epoxy resin is used.
Uses 90-layer suspension and highly filled epoxy resin. This resin has a thermal expansion coefficient extremely close to that of the semiconductor element 8 due to the high filling of the silica powder.
, superior to conventional resins in terms of thermal stress. In addition, the high filling of silica powder reduces moisture absorption and improves mounting and soldering heat resistance +i (package cracking, peeling at the interface between the resin and the lead frame, etc.). As a result, moisture resistance is improved. However, since the silica powder is highly filled, the fluidity is poor and it cannot be used for molding, but this problem can be solved as described below by using the mold 2 shown in Fig. 1 (A) and (B). It's solved like this.
第１回目の封止成形は、第１図（Ａ）、（１３）に示す
ように、半導体素子８がステージ９上に固定されたリー
ドフレーム３０を、半導体素子８がキャビティ５の中央
に位置するように位置決めして、金型２を閉じ、上記の
シリカ粉高充填エポキシ樹脂をキャピテイ５内に充填す
る。キャビティ５内には、半導体索子８．ステージ９に
加えて、ＡＵ線１０及びＡｕｌｍ１０の内リード１０ａ
へのボンディング部が収容されている。In the first sealing molding, as shown in FIGS. 1A and 13, the lead frame 30 with the semiconductor element 8 fixed on the stage 9 is placed in the center of the cavity 5. The mold 2 is closed, and the cavity 5 is filled with the epoxy resin highly filled with silica powder. Inside the cavity 5 is a semiconductor cord 8. In addition to the stage 9, the AU wire 10 and the inner lead 10a of the Aulm 10
The bonding part for the is housed.
上記樹脂は、ランナ１２よりゲート１３に入り、バス１
５を通ってキャビティ５内に流れ込み、キャビティ５内
を満たし、第２図（Ａ）、（Ｂ）及び第３図に示すよう
に、半導体素子８及びＡＵ線１０を包囲してこれらを封
止する。３１は封止した樹脂層、３２は封止成形体であ
る。The resin enters the gate 13 from the runner 12 and enters the bus 1
5, flows into the cavity 5, fills the inside of the cavity 5, surrounds the semiconductor element 8 and the AU wire 10, and seals them, as shown in FIGS. 2(A), (B) and FIG. do. 31 is a sealed resin layer, and 32 is a sealed molded body.
パス１５はキャビティ５に向かうにつれて徐々に幅広と
なっているため、樹脂はゲート１３を通過した後、主１
１ビテイ５に到る間に広がり、幅がＷｚと幅広となった
状態でキャビティ５内に流れ込む。従って、樹脂のゲー
ト１３よりキャピテイ５内への流動はスムーズとなる。Since the path 15 gradually becomes wider as it goes toward the cavity 5, the resin passes through the gate 13 and then passes through the main path 15.
It spreads while reaching the cavity 5 and flows into the cavity 5 with a wide width Wz. Therefore, the resin flows smoothly into the cavity 5 from the gate 13.
またキャビティ５は偏平な円板形状であり、容積が最小
となっているため、樹脂がキャビティ５内を満たすとき
Ａｕね１０の近傍を流動する樹脂Ｍは自ずと少なくなる
。このため、上記のような流動性が良くない樹脂を使用
しても、ＡＵ線１０の変形を最小限に抑えて、樹脂はキ
ャビティ５内に充填される。また、泡の発生も抑制され
る。Further, since the cavity 5 has a flat disk shape and has a minimum volume, when the cavity 5 is filled with resin, the amount of resin M flowing near the Au layer 10 naturally decreases. Therefore, even if a resin having poor fluidity as described above is used, the resin can be filled into the cavity 5 while minimizing deformation of the AU wire 10. Moreover, generation of bubbles is also suppressed.
上記のように、第１図（Ａ）、（Ｂ）の金型２を使用す
ることにより、フィラー高充填エポキシ樹脂を使用して
、半導体索子８．Ａｌｌｌｌ線香０変形させずに１・１
止することが出来、しがも、封止した樹脂層３１を耐熱
応力性に優れ、且つ耐湿性が向上したものとし得る。As described above, by using the mold 2 shown in FIGS. 1(A) and 1(B), the semiconductor cord 8. Allll incense 0 without deformation 1・1
However, the sealed resin layer 31 can have excellent heat stress resistance and improved moisture resistance.
また、上記の樹脂は、熱膨張係数が半導体素子８の熱膨
張係数に近似しているため、半導体素子８は、封止した
樹脂３１により熱応力を受けにくい。Further, since the above-mentioned resin has a thermal expansion coefficient close to that of the semiconductor element 8, the semiconductor element 8 is not easily subjected to thermal stress due to the sealed resin 31.
第２回目の封止成形は、第２図（Ａ）、（Ｂ）に示すよ
うに、封止成形体３２をキｉＩビティ２３の中央に配し
て金型２ｏを閉じ、上記のフィラー高充填エポキシ樹脂
をキャビディ２３内に充填することにより行なわれる。In the second sealing molding, as shown in FIGS. 2(A) and (B), the sealing molded body 32 is placed in the center of the groove 23, the mold 2o is closed, and the filler height is set as above. This is done by filling the cavity 23 with a filled epoxy resin.
この封止成形により、第３図に示す半導体装置１が完成
する。３３は第２回目の封止成形により前記の封止成形
体３２を覆って形成された樹脂層である。Through this sealing molding, the semiconductor device 1 shown in FIG. 3 is completed. Reference numeral 33 denotes a resin layer formed to cover the sealing molded body 32 by the second sealing molding.
従って、上記のように％Ｊ造された半導体装置１は、熱
応力に強（且つ耐湿性に優れたものとなる。Therefore, the semiconductor device 1 manufactured as described above is resistant to thermal stress (and has excellent moisture resistance).
第３図中、１１ｂは下方に折曲された外リードである。In FIG. 3, 11b is an outer lead bent downward.
なお、前記キャビティ５の形状は円板状に限るものでは
なく、例えば楕円板状又はラグビーボール状でもよく、
要は、容積が小となるように内面が曲面とされていれば
よい。Note that the shape of the cavity 5 is not limited to a disk shape, and may be, for example, an elliptical plate shape or a rugby ball shape.
In short, it is sufficient that the inner surface is curved so that the volume is small.
また、シリカ粉高充填合成樹脂としてはエポキシ樹脂に
限るしのではなく、熱硬化性合成樹脂であればよい。Further, the synthetic resin highly filled with silica powder is not limited to epoxy resin, and any thermosetting synthetic resin may be used.
本発明によれば、流動性の良くないシリカ粉高充填樹脂
を使用して、ワイヤを損傷させることなく半導体素子を
封止することが出来、然して、熱応力に強く且つ耐湿性
に優れた半導体装置を（ｑることが出来る。According to the present invention, it is possible to seal a semiconductor element without damaging the wire by using a resin highly filled with silica powder that has poor fluidity, and it is possible to seal a semiconductor element with high resistance to thermal stress and excellent moisture resistance. It is possible to (q) the device.
第１図（Ａ）、（Ｂ）は本発明の一実施例になる半導体
装置の製造方法の第１回目の封止成形を説明する図、
第２図（△）、（Ｂ）は第２回目の封止成形を説明する
図、
第３図は木発ｆｐｌ （７）製造方法により製造された
半導体装置を示で図である。
図中、
１は半導体装置、
２は第１回目の封止成形用金型、
５はキャビティ、
８は半導体素子、
１０は八〇８．
１３はゲート、
１５はパスである。
８半弗体軒
ＣＢ）
本１≦前可の牛廊Ｆ利（す（青１０喪ε孜コγ褒型ｎ第
１卸口の払ｊ゛］」〈’＋ンＶ整り用謁田第１図
第２因Figures 1 (A) and (B) are diagrams explaining the first sealing molding of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and Figures 2 (△) and (B) are diagrams explaining the second FIG. 3 is a diagram illustrating the second sealing molding process. FIG. In the figure, 1 is a semiconductor device, 2 is a first sealing mold, 5 is a cavity, 8 is a semiconductor element, and 10 is 808. 13 is a gate, and 15 is a path. 8 half-flat eaves CB) Book 1 ≦ front-possible cow corridor F interest (su (blue 10 mourning ε ko γ reward type n payment of the first wholesaler)) Figure 1 2nd cause
Claims (1)
子及びこれに接続されたワイヤを包囲するように１回目
成形を行ない、次に半導体装置の外形形状を形成する２
回目成形を行なつて半導体装置を製造する方法において
、 上記１回目の成形を、上記半導体素子を囲む曲面状のキ
ャビティ（５）と、ゲート（１３）より該キャビティに
向かうにつれて幅広となるパス（１５）とを有する形状
の金型（２）を使用し、熱膨張係数が上記熱硬化性合成
樹脂の熱膨張係数より小さいシリカ粉を高充填されたシ
リカ粉高充填熱硬化性合成樹脂を使用して行なうことを
特徴とする半導体装置の製造方法。 〔２〕キャビティ形状が円板状のものを使用した特許請
求の範囲第〔１〕項記載の半導体装置の製造方法。 〔３〕シリカ粉の含有率として７５〜９０重量部のもの
を使用した特許請求の範囲第〔１〕項又は第〔２〕項記
載の半導体装置の製造方法。[Scope of Claims] [1] Molding a semiconductor element with a thermosetting synthetic resin for the first time so as to surround the semiconductor element and wires connected thereto, and then forming the external shape of the semiconductor device.
In a method of manufacturing a semiconductor device by performing a second molding, the first molding is performed by forming a curved cavity (5) surrounding the semiconductor element and a path (13) that becomes wider from the gate (13) toward the cavity. 15) Using a mold (2) having a shape having the above, a thermosetting synthetic resin highly filled with silica powder having a coefficient of thermal expansion smaller than that of the thermosetting synthetic resin is used. 1. A method for manufacturing a semiconductor device, characterized in that the method is performed by: [2] The method for manufacturing a semiconductor device according to claim [1], in which a cavity having a disk shape is used. [3] The method for manufacturing a semiconductor device according to claim [1] or [2], wherein the content of silica powder is 75 to 90 parts by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19592386A JPS6351647A (en) | 1986-08-21 | 1986-08-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19592386A JPS6351647A (en) | 1986-08-21 | 1986-08-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6351647A true JPS6351647A (en) | 1988-03-04 |
Family
ID=16349229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19592386A Pending JPS6351647A (en) | 1986-08-21 | 1986-08-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6351647A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236710A (en) * | 1989-11-20 | 1991-10-22 | Toyosha Kk | Apparatus for arranging plant foot of reaped rush in rush harvester |
| JP2010522994A (en) * | 2007-03-29 | 2010-07-08 | アレグロ・マイクロシステムズ・インコーポレーテッド | Method and apparatus for multistage molding of integrated circuit packages |
| US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
| US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10725100B2 (en) | 2013-03-15 | 2020-07-28 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having an externally accessible coil |
-
1986
- 1986-08-21 JP JP19592386A patent/JPS6351647A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236710A (en) * | 1989-11-20 | 1991-10-22 | Toyosha Kk | Apparatus for arranging plant foot of reaped rush in rush harvester |
| JP2010522994A (en) * | 2007-03-29 | 2010-07-08 | アレグロ・マイクロシステムズ・インコーポレーテッド | Method and apparatus for multistage molding of integrated circuit packages |
| US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
| US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10230006B2 (en) | 2012-03-20 | 2019-03-12 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an electromagnetic suppressor |
| US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10916665B2 (en) | 2012-03-20 | 2021-02-09 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil |
| US11444209B2 (en) | 2012-03-20 | 2022-09-13 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil enclosed with a semiconductor die by a mold material |
| US11677032B2 (en) | 2012-03-20 | 2023-06-13 | Allegro Microsystems, Llc | Sensor integrated circuit with integrated coil and element in central region of mold material |
| US11828819B2 (en) | 2012-03-20 | 2023-11-28 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US11961920B2 (en) | 2012-03-20 | 2024-04-16 | Allegro Microsystems, Llc | Integrated circuit package with magnet having a channel |
| US10725100B2 (en) | 2013-03-15 | 2020-07-28 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having an externally accessible coil |
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