JPS6351300B2 - - Google Patents
Info
- Publication number
- JPS6351300B2 JPS6351300B2 JP58237575A JP23757583A JPS6351300B2 JP S6351300 B2 JPS6351300 B2 JP S6351300B2 JP 58237575 A JP58237575 A JP 58237575A JP 23757583 A JP23757583 A JP 23757583A JP S6351300 B2 JPS6351300 B2 JP S6351300B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- ram
- switch
- electronic circuit
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、RAMと、電気的に書換可能な不揮
発性メモリを組み合わせた不揮発性RAMに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile RAM that is a combination of a RAM and an electrically rewritable nonvolatile memory.
従来の不揮発性RAMは、RAM領域内のデー
タを不揮発性メモリ領域に転送する場合に、転送
を指令する制御信号を制御端子に印加して行なう
ため、電源電圧降下や瞬時の停電等のような電源
異常時に、RAM領域内のデータを保護すべく不
揮発性メモリ領域に転送したい場合、チツプ外部
に電源電圧の異常を検知して、転送制御信号を発
生させる回路を必要とするうえ、転送を完了する
までの期間、不揮発性RAMの内部電子回路に、
正しく転送が行なえる電力を供給し続けなければ
ならず、これらのことを実際に実現することは、
難しいという欠点があつた。 Conventional non-volatile RAM transfers data in the RAM area to the non-volatile memory area by applying a control signal that commands the transfer to the control terminal, so it is difficult to transfer data from the RAM area to the non-volatile memory area by applying a control signal to the control terminal. If you want to transfer data in the RAM area to a non-volatile memory area to protect it in the event of a power failure, you will need a circuit external to the chip that detects the power supply voltage abnormality and generates a transfer control signal, and then completes the transfer. Until the internal electronic circuit of non-volatile RAM
It is necessary to continue supplying power for proper transfer, and to actually achieve this,
It had the drawback of being difficult.
本発明は、これらの欠点を解決するため、チツ
プに内蔵されたMOSトランジスタにより構成さ
れる複数のスイツチ及び電源電圧の変化を検知す
る回路と、チツプに外付けされたコンデンサによ
り電源電圧があらかじめ定められた一定のレベル
まで降下するのを検出して、自動的にRAM領域
内のデータを不揮発性メモリ領域へ転送するもの
で、従来難しかつた電源異常時のメモリ内容の保
護が簡単に行なえるもので、以下図面に基づいて
本発明を詳細に説明する。 In order to solve these drawbacks, the present invention uses a circuit that detects changes in the power supply voltage and a plurality of switches composed of MOS transistors built into the chip, and a capacitor externally attached to the chip to predetermine the power supply voltage. The system detects when the power level drops to a certain level and automatically transfers the data in the RAM area to the non-volatile memory area, making it easy to protect the memory contents in the event of a power failure, which was previously difficult. The present invention will be explained in detail below based on the drawings.
第１図は、本発明の実施例であつて、１は電源
端子、２はRAMと不揮発性メモリ及び、それら
の周辺回路から成る内部電子回路、３は外付コン
デンサ端子であり、swaは電源端子１と外付コン
デンサ端子３間に接続されたMOSトランジスタ
によるスイツチ、swbは内部電子回路２と外付コ
ンデンサ端子３間に接続されたMOSトランジス
タによるスイツチ、swcは電源端子１と内部電子
回路２間に接続されたMOSトランジスタによる
スイツチであり、以上三つのスイツチswa，swb
とswcとを電源電圧の変化に応じて制御すること
により、RAM領域のデータを不揮発性メモリ領
域へ転送する。 FIG. 1 shows an embodiment of the present invention, in which 1 is a power supply terminal, 2 is an internal electronic circuit consisting of RAM, nonvolatile memory, and their peripheral circuits, 3 is an external capacitor terminal, and swa is a power supply terminal. A switch using a MOS transistor connected between terminal 1 and external capacitor terminal 3, swb is a switch using a MOS transistor connected between internal electronic circuit 2 and external capacitor terminal 3, and swc is a switch using a MOS transistor connected between power supply terminal 1 and internal electronic circuit 2. This is a switch using a MOS transistor connected between the three switches swa and swb.
By controlling swc and swc according to changes in the power supply voltage, data in the RAM area is transferred to the nonvolatile memory area.
第２図は、電源電圧の変化に対しての３つのス
イツチswa，swbとswcとの動作状態を示すもの
であり、まず電源を投入するとスイツチswcがオ
ンし、内部電子回路２へ電源を供給すると共に、
内部電子回路２はあらかじめ決められた初期状態
に設定される。次に電源電圧が上昇し電圧値Ej1
を越えるとスイツチswaがオンし、外付したコン
デンサ（バツクアツプ電源用コンデンサ）４へ電
荷を送り充電を開始させる。さらに電源電圧が上
昇し、正常に動作する電圧に達すると通常の
RAM動作が可能となり、この通常動作中に外付
コンデンサへの充電を完了する。その後、電源電
圧が降下し電圧値Ej1より低くなつた時点で、ス
イツチswaはオフし、コンデンサに貯えた電荷を
逃がさない様にする。さらに、電源電圧が降下し
電圧値Ej2より低くなつた時点で、スイツチswc
がオフすると共にスイツチswbがオンし、コンデ
ンサに貯えた電荷によつて内部電子回路２は
RAM領域２ａから不揮発性メモリ２ｂへのデー
タの転送を行なう。このデータの転送は、内部電
子回路自身がメモリに要求されるタイミングパル
スを発生し完了する。転送が終了するとスイツチ
swcは、再びオンする。 Figure 2 shows the operating states of three switches swa, swb, and swc in response to changes in power supply voltage.When the power is turned on, switch swc turns on and supplies power to the internal electronic circuit 2. At the same time,
The internal electronic circuit 2 is set to a predetermined initial state. Next, the power supply voltage increases and the voltage value Ej 1
When the voltage is exceeded, the switch swa is turned on, sending charge to the external capacitor (backup power supply capacitor) 4 and starting charging. The power supply voltage increases further, and when it reaches the voltage for normal operation, the normal
RAM operation is enabled, and charging of the external capacitor is completed during this normal operation. Thereafter, when the power supply voltage drops and becomes lower than the voltage value Ej1 , the switch swa is turned off to prevent the charge stored in the capacitor from escaping. Furthermore, when the power supply voltage drops and becomes lower than the voltage value Ej 2 , the switch swc
is turned off, switch swb is turned on, and the internal electronic circuit 2 is turned on by the charge stored in the capacitor.
Data is transferred from the RAM area 2a to the nonvolatile memory 2b. This data transfer is completed by the internal electronics themselves generating the required timing pulses to the memory. When the transfer is completed, switch
Turn the swc back on.
かくして、何らかの原因で電源電圧が降下した
場合、外部に何ら電子回路を付加せず、コンデン
サ端子３に規定の容量のコンデンサを接続するだ
けで、自動的にRAM領域から不揮発性メモリ領
域へのデータ転送が行なわれ、メモリの内容を消
失することが防げるという利点がある。 In this way, if the power supply voltage drops for some reason, data can be automatically transferred from the RAM area to the non-volatile memory area by simply connecting a capacitor of the specified capacity to capacitor terminal 3 without adding any external electronic circuit. There is an advantage that the transfer is performed and the contents of the memory can be prevented from being lost.
また、何らかの都合で、オートストアを行ない
たくない場合においては、オートストアを禁止す
る制御端子（図示せず）を有しておりり、この制
御端子を電源電圧の二値電位のいずれか一方に固
定しておくことにより、オートストア動作を有さ
ない不揮発性RAMと容易に置き換え可能である
という利点がある。 In addition, if for some reason you do not want to perform auto store, there is a control terminal (not shown) that prohibits auto store, and this control terminal can be set to one of the binary potentials of the power supply voltage. By keeping it fixed, there is an advantage that it can be easily replaced with a non-volatile RAM that does not have auto store operation.
さらに第１図に示した内部電子回路及びスイツ
チの接続構成においては、通常のRAM動作時は
内部電子回路２は、電源端子１からスイツチswc
を導通させて電流を供給されているが、RAMの
動作速度が速くなり、より多くの電流を内部電子
回路２が消費する様な場合、電流容量を増やすべ
くスイツチswcを構成するMOSトランジスタの
面積を大きくしなければならず、集積度を下げ不
利である。そこで、第３図に示す様に、内部電子
回路のうちオートストア動作時には電源を供給し
なくてもよい部分２′を直接電源端子１に接続し
ておくことにより、スイツチswcを小さくするこ
とができ、しかも、オートストア時には、内部電
子回路のうちオートストアに無関係な部分２′に
対し、外付のコンデンサ４に貯えた電荷を消費さ
せずに済むので、コンデンサ４の容量も小さくて
済み、回路実装上有利である。 Furthermore, in the connection configuration of the internal electronic circuit and the switch shown in FIG. 1, during normal RAM operation, the internal electronic circuit 2 is connected from the power supply terminal 1 to
However, as the operating speed of the RAM becomes faster and the internal electronic circuit 2 consumes more current, the area of the MOS transistor that makes up the switch swc should be increased to increase the current capacity. must be made large, which is disadvantageous as it reduces the degree of integration. Therefore, as shown in Fig. 3, the switch swc can be made smaller by directly connecting the part 2' of the internal electronic circuit that does not need to be supplied with power during auto-store operation to the power supply terminal 1. Furthermore, during auto-store, the charge stored in the external capacitor 4 does not need to be consumed by the portion 2' of the internal electronic circuit that is unrelated to auto-store, so the capacitance of the capacitor 4 can also be small. This is advantageous in terms of circuit implementation.
オートストアにより不揮発性メモリ内に貯えら
れたデータは、電源投入時あるいは瞬時の停電後
の回復後の回復時に、電源電圧が適正電圧値にな
るのを検出して、自動的にRAMに転送すること
により、電源異常が発生しても、電源異常以前の
データと同じものがRAMに転送されているの
で、何ら問題なくRAMの動作を続行できるとい
う効果を有する。 Data stored in non-volatile memory by auto store is automatically transferred to RAM when the power supply voltage reaches the appropriate voltage value when the power is turned on or when the system recovers after a momentary power outage. As a result, even if a power failure occurs, the same data as before the power failure has been transferred to the RAM, so the RAM can continue operating without any problems.
第１図は本発明の実施例の回路構成図、第２図
は電源電圧の変化に対する三つのスイツチの動作
を示す図、第３図は本発明の他の実施例による回
路構成図を示すものである。
１……電源端子、２……内部電子回路、２ａ…
…RAM、２ｂ……不揮発性メモリ、３……コン
デンサ端子、４……外付コンデンサ、swa，
swb，swc……スイツチ、２′……内部電子回路
の一部。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the operation of three switches in response to changes in power supply voltage, and Fig. 3 is a circuit diagram of another embodiment of the invention. It is. 1...Power terminal, 2...Internal electronic circuit, 2a...
...RAM, 2b...Nonvolatile memory, 3...Capacitor terminal, 4...External capacitor, swa,
swb, swc...switch, 2'...part of the internal electronic circuit.
Claims (1)
RAMのビツト毎に１対１で組み込まれた電気的
に書換可能な不揮発性メモリから成る集積回路に
おいて、チツプに内蔵されたMOSトランジスタ
によつて構成される第１から第３のスイツチを備
え、前記第１のスイツチは電源端子と外付コンデ
ンサ端子との間に設けられ、前記第２のスイツチ
は外付コンデンサ端子と、前記RAMと前記不揮
発性メモリとを有する電子回路との間に設けら
れ、更に前記第３のスイツチは前記電子回路と前
記電源端子との間に設けられており、電源電圧降
下あるいは電源OFF時に、前記第１から第３の
スイツチのスイツチング動作により前記外付コン
デンサに予め蓄えておいた電荷を前記第１から第
３のスイツチング動作によつて前記電子回路に供
給することを特徴とするバツクアツプ電源用コン
デンサ付不揮発性RAM。1 Within a semiconductor integrated circuit chip, RAM and the
An integrated circuit consisting of an electrically rewritable non-volatile memory incorporated one-to-one for each bit of RAM, comprising first to third switches constituted by MOS transistors built into the chip, The first switch is provided between a power supply terminal and an external capacitor terminal, and the second switch is provided between an external capacitor terminal and an electronic circuit having the RAM and the nonvolatile memory. Furthermore, the third switch is provided between the electronic circuit and the power supply terminal, and when the power supply voltage drops or the power is turned off, the external capacitor is preliminarily charged by the switching operation of the first to third switches. A non-volatile RAM with a capacitor for backup power supply, characterized in that stored charges are supplied to the electronic circuit by the first to third switching operations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58237575A JPS60128549A (en) | 1983-12-16 | 1983-12-16 | Nonvolatile raw having automatic storage function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58237575A JPS60128549A (en) | 1983-12-16 | 1983-12-16 | Nonvolatile raw having automatic storage function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60128549A JPS60128549A (en) | 1985-07-09 |
| JPS6351300B2 true JPS6351300B2 (en) | 1988-10-13 |
Family
ID=17017344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58237575A Granted JPS60128549A (en) | 1983-12-16 | 1983-12-16 | Nonvolatile raw having automatic storage function |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60128549A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6380649U (en) * | 1986-11-13 | 1988-05-27 | ||
| JPH07177776A (en) * | 1994-07-25 | 1995-07-14 | Matsushita Electric Ind Co Ltd | Parameter setting apparatus of motor controller |
-
1983
- 1983-12-16 JP JP58237575A patent/JPS60128549A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60128549A (en) | 1985-07-09 |
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