JPS6351296B2 - - Google Patents
Info
- Publication number
- JPS6351296B2 JPS6351296B2 JP58169945A JP16994583A JPS6351296B2 JP S6351296 B2 JPS6351296 B2 JP S6351296B2 JP 58169945 A JP58169945 A JP 58169945A JP 16994583 A JP16994583 A JP 16994583A JP S6351296 B2 JPS6351296 B2 JP S6351296B2
- Authority
- JP
- Japan
- Prior art keywords
- resident area
- area
- resident
- tag information
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 2
- 101100368725 Bacillus subtilis (strain 168) tagF gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はキヤツシユメモリの中を常駐領域と非
常駐領域とに分割し、しかも常駐領域は主メモリ
と１対１に対応させることによりTAG情報をも
たせることなく、非常駐領域にのみTAG情報を
もたせたキヤツシユ制御方式に関するものであ
る。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention divides a cache memory into a resident area and a non-resident area, and furthermore, the resident area is made to have a one-to-one correspondence with the main memory, thereby storing TAG information. This relates to a cache control method in which TAG information is provided only in non-resident areas, without providing TAG information.
(2) 従来技術と問題点
従来、キヤツシユメモリは主メモリに対して多
用する命令またはデータを保持しておき、主メモ
リに代り直接高送アクセスする機能をもつ。キヤ
ツシユメモリはTAG情報を用いて主メモリとの
間でデータの授受が行なわれる。キヤツシユメモ
リは、マイクロ命令の使用形態から使用頻度の高
いエリアは常にキヤツシユ上に置かないと性能低
下が大きくなつてしまう。従つてキヤツシユメモ
リを常駐領域と非常駐領域とに分割する必要が生
じる。この場合常駐領域に対してはキヤツシユメ
モリと主メモリを１対１に対応させることによ
り、TAG情報が不要となり、非常駐領域に対応
するTAG情報のみとしてハード量を減少させて
いる。しかしこの場合、主メモリから常駐領域に
対するキヤツシユメモリに初期ロードが行なわれ
たか否かを判定する手段や、ある領域を無効にし
たい場合の手段が問題となる。(2) Prior Art and Problems Conventionally, cache memory has the function of holding frequently used instructions or data in main memory, and providing direct high-speed access in place of main memory. Data is exchanged between the cache memory and the main memory using TAG information. Due to the way microinstructions are used in cache memory, if frequently used areas are not always placed on the cache, the performance will be greatly degraded. Therefore, it becomes necessary to divide the cache memory into a permanent area and a non-resident area. In this case, by providing a one-to-one correspondence between the cache memory and the main memory for the permanent area, TAG information is no longer necessary, and the amount of hardware is reduced by providing only TAG information corresponding to the non-resident area. However, in this case, the problem is how to determine whether an initial load has been performed from the main memory to the cache memory for the resident area, and how to invalidate a certain area.
(3) 発明の目的
本発明の目的は、キヤツシユメモリ中を常駐領
域と非常駐領域とに分割し、かつTAG情報を非
常駐領域に対応するもののみをもたせたキヤツシ
ユ制御方式において、常駐領域のある領域が有効
か無効かを容易に判定することのできるキヤツシ
ユ制御方式を提供することである。(3) Purpose of the Invention The purpose of the present invention is to provide a cache control method in which a cache memory is divided into a resident area and a non-resident area, and TAG information is provided only for the non-resident area. An object of the present invention is to provide a cache control method that can easily determine whether an area is valid or invalid.
(4) 発明の構成
前記目的を達成するため、本発明のキヤツシユ
制御方式はキヤツシユメモリの中を常駐領域と非
常駐領域とに分割し、かつ常駐領域のアドレス配
列を主メモリの対応する領域のアドレス配列と同
一とすることにより、常駐領域についてはTAG
情報を不要とし、非常駐領域についてのみTAG
情報をもたせたキヤツシユ制御方式において、
上記常駐領域と非常駐領域との大きさを同一と
して、両領域のアドレスの下位が等しくなるよう
にし、非常駐領域のTAG情報の中に、下位アド
レスを等しくする常駐領域の有効性を示すバリツ
ドビツトをもたせたことを特徴とするものであ
る。(4) Structure of the Invention In order to achieve the above object, the cache control method of the present invention divides the cache memory into a resident area and a non-resident area, and changes the address array of the resident area to the corresponding area of the main memory. By making it the same as the address array, TAG for the resident area
No information required, TAG only for non-resident areas
In a cache control method that has information, the sizes of the resident area and the non-resident area are made the same, the lower addresses of both areas are made equal, and the TAG information of the non-resident area includes a resident area whose lower addresses are equal. It is characterized by having a valid bit that indicates the validity of the area.
(5) 発明の実施例 第１図は本発明の原理説明図である。(5) Examples of the invention FIG. 1 is a diagram explaining the principle of the present invention.
同図は、キヤツシユメモリ２における常駐領域
２1と非常駐領域２2の配分とデータを授受（ムー
ブイン／ムーブアウト）する主メモリ１の構成
と、TAG３の構成を実例について示したもので
ある。すなわち、キヤツシユメモリ２において、
アドレス（＃８−＃15）＝0016（＃８−＃15ビツト
が16進表示でオール０を意味する）の時を常駐領
域に対応させ、≠0016の時を非常駐領域に対応さ
せ、かつ両領域の配分を等分とする。そして、16
進表示で主メモリ１のアドレス“0000〜FFFF”
の64Kバイト領域は、キヤツシユメモリ２の常駐
領域２1へ初期ロードされた後はムーブアウトさ
れず常にキヤツシユメモリ上に存在する。また主
メモリ１のアドレス10000〜FFFFFFについて
は、従来のキヤツシユ方式またはバツフア方式と
同様に制御され、非常駐領域２2で定義される
64Kバイトの領域へ各ブロツク32バイト単位でム
ーブイン／ムーブアウトされ、この場合主メモリ
１とキヤツシユメモリの間でTAGメモリ３の情
報によりアドレスの確認が行なわれる。 This figure shows an example of the allocation of the resident area 2 1 and non-resident area 2 2 in the cache memory 2, the configuration of the main memory 1 for exchanging data (move-in/move-out), and the configuration of the TAG 3. That is, in the cache memory 2,
When the address (#8-#15) = 00 16 (bits #8-#15 mean all 0 in hexadecimal notation), it corresponds to the resident area, and when ≠00 16 , it corresponds to the non-resident area, And the distribution of both areas is equally divided. And 16
Main memory 1 address “0000 to FFFF” in decimal notation
After the 64 Kbyte area is initially loaded into the resident area 21 of the cache memory 2, it is not moved out and always exists on the cache memory. Also, addresses 10000 to FFFFFF of main memory 1 are controlled in the same way as the conventional cache method or buffer method, and are defined in non-resident area 2 .
Each block is moved in/out in units of 32 bytes to an area of 64 Kbytes, and in this case, addresses are confirmed between the main memory 1 and the cache memory using the information in the TAG memory 3.
ここで、キヤツシユメモリ２の常駐領域２1に
対応するTAG情報は、キヤツシユメモリ２と主
メモリ１のアドレスブロツクが図示のごとく１対
１となつているからアクセスには必要ないが、こ
の場合たとえば、主メモリからの初期ロードが行
なわれたか否かを判定することができないという
問題点がある。このためにはロードを示すフラグ
すなわちバリツドビツトをもつ必要がある。しか
し、そのバリツドビツト１ビツトのTAGを常駐
領域用として32バイト毎に別に用意することはハ
ード量の増加となるから、本発明ではバリツドビ
ツトを常駐領域２1に対応するすなわち所定の下
位アドレスが同じ非常駐領域２2の各ブロツク用
のTAG情報内にもたせ、常駐領域アクセス時に
非常駐領域用に対応するTAG情報を見て常駐領
域アクセスであることによつて、アドレスの比較
は行なわれず、バリツドビツトのみをチエツクし
てキヤツシユメモリの一致を確認しようとするも
のである。 Here, the TAG information corresponding to the resident area 21 of the cache memory 2 is not necessary for access because the address blocks of the cache memory 2 and the main memory 1 are in a one-to-one relationship as shown in the figure. For example, there is a problem in that it is not possible to determine whether an initial load from main memory has been performed. For this purpose, it is necessary to have a flag indicating load, that is, a valid bit. However, preparing a separate 1-bit TAG for the resident area for every 32 bytes would increase the amount of hardware, so in the present invention, the valid bit is allocated to a non-resident area that corresponds to the resident area 21 , that is, has the same predetermined lower address. This is stored in the TAG information for each block in area 2 2 , and when the resident area is accessed, the TAG information corresponding to the non-resident area is checked and the address is not compared, but only the valid bits are checked. This is to check if the cache memory matches.
第２図は上述の原理に従う本発明の実施例の構
成説明図である。 FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention according to the above-described principle.
同図において、キヤツシユメモリ２は第１図で
説明したように、常駐領域２1と非常駐領域２2と
に等分割する。TAGメモリ３はキヤツシユメモ
リ２の非常駐領域２2の各ブロツクに対応する
TAG情報のみが用意される。さらにこれらの
TAG情報に加えて対応する常駐領域が有効か無
効かを示すバリツドビツトV1をもたせる。TAG
メモリ３の非常駐対応ブロツク３1にはTAG情報
（＃８−＃15）、非常駐領域のバリツドビツトV0
および本発明の常駐領域のバリツドビツトV1を
格納している。なお、P0、P1はパリテイビツト
であり、P0はアドレスの８〜15ビツトとV0のパ
リテイ、P1はV1についてのパリテイである。 In the figure, the cache memory 2 is equally divided into a permanent area 2 1 and a non-resident area 2 2 as explained in FIG. TAG memory 3 corresponds to each block in non-resident area 22 of cache memory 2.
Only TAG information is provided. Furthermore these
In addition to TAG information, a valid bit V1 indicating whether the corresponding resident area is valid or invalid is provided. TAG
The non-resident block 31 of memory 3 contains TAG information (#8-#15) and the valid bit V0 of the non-resident area.
and a valid bit V1 of the resident area of the present invention. Note that P 0 and P 1 are parity bits, P 0 is the parity of 8 to 15 bits of the address and V 0 , and P 1 is the parity of V 1 .
これらのキヤツシユメモリ２とTAG３に対し、
それぞれアドレスレジスタ１０の上位ビツト
（＃８−＃15）と下位ビツト（＃16−＃29）によ
り同時にアクセスする。すなわち、上位アドレス
（＃８−＃15）を領域判定回路１１に入れ、＝
（00）16（＃８−＃15がオール０）であれば常駐領
域と判定し、≠（00）16（＃８−＃15がオール０で
ない）ならば非常駐領域と判定する。そして下位
アドレス（＃16−＃29）の14ビツトの頭に前者に
対し“０”を付し後者に対し“１”を付して15ビ
ツトとして、キヤツシユメモリ２をアクセスす
る。先頭ビツトにより、“０”ならば上部の常駐
領域２1から、“１”ならば下部の非常駐領域２2
から所定の４バイトのリードデータを出力する。
一方、アドレスレジスタ１０からの必要なアドレ
スビツト（＃16−＃26）をTAGメモリ３に入れ、
アクセスにより読出されたブロツク３1内のバリ
ツドビツトV0が“１”でかつTAG出力（＃８−
＃15）がアドレスレジスタ１０の上位アドレス
（＃８−＃15）と一致（ヒツト）すると、非常駐
領域のキヤツシユの有効性が確認される。 For these cache memories 2 and TAG 3,
They are accessed simultaneously by the upper bits (#8-#15) and lower bits (#16-#29) of the address register 10, respectively. That is, put the upper address (#8-#15) into the area determination circuit 11, and =
If (00) 16 (#8-#15 are all 0), it is determined to be a resident area, and if ≠ (00) 16 (#8-#15 are not all 0), it is determined to be a non-resident area. Then, the cache memory 2 is accessed by adding "0" to the beginning of the 14 bits of the lower address (#16-#29) and adding "1" to the latter to make 15 bits. Depending on the first bit, if it is “0”, it starts from the upper permanent area 2 1 , and if it is “1”, it starts from the lower non-resident area 2 2
Outputs predetermined 4-byte read data from.
On the other hand, put the necessary address bits (#16-#26) from address register 10 into TAG memory 3,
Valid bit V0 in block 31 read by access is “1” and TAG output (#8-
#15) matches (hit) the upper address (#8-#15) of the address register 10, the validity of the cache in the non-resident area is confirmed.
これは通常のTAG情報の用法である。 This is the normal usage of TAG information.
本発明の用法では、前述のように常駐領域の初
期ロードを示すビツトV1を、対応する下位アド
レス（＃16−＃26）が同じ非常駐ブロツクに保持
する。たとえば、常駐領域のアドレス（00〜1F）
のバリツドビツトV1は、非常駐領域のアドレス
ブロツク０に対応するTAG３内のブロツク０用
TAG内に保持されている。従つて、バリツドビ
ツトV1が“１”を示し、かつアドレスが領域判
定回路１１により常駐領域（＝0016）と判定さ
れ、比較回路１２から一致（ヒツト）信号が得ら
れると、その非常駐ブロツク３1に対応する常駐
領域が有効であることを示している。このように
非常駐領域のブロツクに、下位アドレスビツトが
同じ常駐領域に対するフラグ、すなわちバリツド
ビツトを格納しておき、対応する常駐領域の有効
か無効かたとえば初期ロードのチエツク等に使用
できる。 In the usage of the present invention, as described above, bit V1 indicating the initial load of the resident area is held in the non-resident block whose corresponding lower address (#16-#26) is the same. For example, the address of the resident area (00-1F)
Valid bit V1 is for block 0 in TAG3, which corresponds to address block 0 in the non-resident area.
Retained within TAG. Therefore, when the valid bit V1 indicates "1" and the address is determined by the area determination circuit 11 to be a resident area (=00 16 ) and a match (hit) signal is obtained from the comparator circuit 12, the non-resident block 3 is Indicates that the resident area corresponding to 1 is valid. In this way, a flag for a resident area with the same lower address bit, ie, a valid bit, is stored in a non-resident area block, and can be used to check whether the corresponding resident area is valid or invalid, for example, during initial loading.
(6) 発明の効果
以上説明したように、本発明によれば、キヤツ
シユメモリの非常駐領域に対応するTAG情報中
に常駐領域のキヤツシユへの初期ロード情報を示
すバリツドビツトをもたせることにより、常駐領
域用としてTAG情報をもたせることなく初期ロ
ード等にも支障なくその有効性の確認を行なうこ
とができ、TAGメモリ量を減少して同等の機能
を果すことができるものである。(6) Effects of the Invention As explained above, according to the present invention, by including a valid bit in the TAG information corresponding to the non-resident area of the cache memory, which indicates the initial load information of the resident area to the cache, the permanent area It is possible to check the validity of the initial load without having to have TAG information for use, and it is possible to perform the same function while reducing the amount of TAG memory.
第１図は本発明の原理説明図、第２図は本発明
の実施例の構成説明図であり、図中、１は主メモ
リ、２はキヤツシユメモリ、２1は常駐領域、２2
は非常駐領域、３はTAGメモリ、３1はブロツク
対応領域、１０はアドレスレジスタ、１１は領域
判定回路、１２は比較回路を示す。
FIG. 1 is an explanatory diagram of the principle of the present invention, and FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention. In the figure, 1 is a main memory, 2 is a cache memory, 2 1 is a resident area, and 2 2
3 is a non-resident area, 3 is a TAG memory, 31 is a block corresponding area, 10 is an address register, 11 is an area determination circuit, and 12 is a comparison circuit.
Claims (1)
域とに分割し、かつ常駐領域のアドレス配列を主
メモリの対応する領域のアドレス配列と同一とす
ることにより、常駐領域についてはTAG情報を
不要とし、非常駐領域についてのみTAG情報を
もたせたキヤツシユ制御方式において、 上記常駐領域と非常駐領域との大きさを同一と
して、両領域のアドレスの下位が等しくなるよう
にし、非常駐領域のTAG情報の中に、下位アド
レスを等しくする常駐領域の有効性を示すバリツ
ドビツトをもたせたことを特徴とするキヤツシユ
制御方式。[Claims] 1. By dividing the cache memory into a resident area and a non-resident area, and making the address array of the resident area the same as the address array of the corresponding area of the main memory, the resident area can be In a cache control method that does not require TAG information and has TAG information only for non-resident areas, the sizes of the above-mentioned resident area and non-resident area are made the same, the lower addresses of both areas are equal, and the TAG information of the non-resident area is A cache control method characterized in that information includes a valid bit indicating the validity of a resident area that makes lower addresses equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169945A JPS6061844A (en) | 1983-09-14 | 1983-09-14 | Cache control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58169945A JPS6061844A (en) | 1983-09-14 | 1983-09-14 | Cache control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6061844A JPS6061844A (en) | 1985-04-09 |
| JPS6351296B2 true JPS6351296B2 (en) | 1988-10-13 |
Family
ID=15895795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58169945A Granted JPS6061844A (en) | 1983-09-14 | 1983-09-14 | Cache control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6061844A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173696U (en) * | 1988-05-20 | 1989-12-08 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559201A (en) * | 1978-06-30 | 1980-01-23 | Fujitsu Ltd | Buffer memory control system |
| JPS5619571A (en) * | 1979-07-23 | 1981-02-24 | Nec Corp | Buffer memory unit |
-
1983
- 1983-09-14 JP JP58169945A patent/JPS6061844A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559201A (en) * | 1978-06-30 | 1980-01-23 | Fujitsu Ltd | Buffer memory control system |
| JPS5619571A (en) * | 1979-07-23 | 1981-02-24 | Nec Corp | Buffer memory unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173696U (en) * | 1988-05-20 | 1989-12-08 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6061844A (en) | 1985-04-09 |
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