JPS635073Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a key input device for guiding the operation state of an operation key for externally controlling the operation of an electric device, for example, to an internal circuit. [Technical background of the invention and its problems] For example, in a video tape recorder, various modes such as recording, playback, fast forward, rewind, etc. are operated by operating keys provided according to these various modes. specified by. Inside the recorder, there is a so-called system controller that collectively determines the operation states of the various operation keys mentioned above and generates various timing signals and control signals to execute operations such as recording and playback according to the determination results. is provided. Since the processing content of this system controller is complex and wide-ranging, it is generally configured with a microcomputer. As a key input device for guiding key input signals of the various operation keys to an internal circuit such as a system controller, there are devices shown in FIGS. 1 to 4. First, explaining the example shown in FIG. 1, _SW1 to _SW2 are various operation keys, and 11 is a system controller consisting of a microcomputer. In this example, the system controller 11
Input ports for only operation keys SW ₁ to SW _o are set in the input port, and corresponding operation keys SW ₁ to _{SW o} are inserted between each input port and the power supply +B. However, in the case of the above configuration, operation key SW ₁
This has the drawback that the system controller 11 requires input ports equal to the number of ~ SW _o . In the example shown in FIG. 2, key input signals from operation keys SW ₁ to _{SW o} are generated as analog signals by a series circuit of resistors R ₁₁ to R _1o , and these analog signals are transmitted to a comparison circuit 12 using, for example, an operational amplifier. ₁ ～
12 _o to convert it into a digital signal and input it to the system controller 11. In addition,
The reference signals of the comparison circuits 12 ₁ to 12 _o are the resistors R ₂₁ to _{R 2 o}
generated by a series circuit of This example has a problem in that it is necessary to set input ports in the system controller 11 in the same number as the operation keys SW ₁ to SW _o , as in the example shown in FIG. 1 above. Furthermore, there is a problem that the comparator circuits 12 ₁ to 12 _o are required as many as the operation keys SW ₁ to SW _o , resulting in a plurality of configurations. Furthermore, each operation key SW ₁ ~ SW _o
Priority is assigned to these, and simultaneous operations cannot be distinguished. For example, even if the operation keys SW ₁ and SW _o are operated at the same time, only the key input signal of the operation key SW ₁ is input to the system controller 11. In the example shown in FIG. 3, the key input signals of the operation keys SW ₁ to _{SW o} are converted into binary code signals by the encoder 13 and input to the system controller 14 . In this example, the number of input ports of the system controller 14 can be significantly reduced compared to the previous examples shown in FIGS. 1 and 2. However, like the example shown in FIG. 2, this method has the disadvantage that simultaneous operations cannot be distinguished. The example shown in FIG. 4 is a key input device based on a so-called scan matrix method. In other words, the operation keys SW ₁ to
SW _o are arranged and, for example, signal lines forming a matrix are scanned using time-divided scan pulses. In the case shown in the figure, since it is a matrix of 4 rows x 4 columns, 13 to 16 operation keys at maximum can be arranged. In this example, there is an advantage that the number of input ports of the system controller 11 can be significantly reduced. However, since the scan pulse P _p is generally generated by the system controller 11, an output port for outputting the scan pulse P _p is required, and the effect of port reduction is not so great when viewed from the overall input/output ports. Here, let us consider the number of signal lines in the four examples described above. Generally, various operation keys
SW ₁ to _{SW o} and the system controller 11 are often formed on separate boards. Therefore, signals are exchanged between the board on which the various operation keys SW ₁ to SW _o are arranged (hereinafter referred to as a keyboard) and the board on which the system controller 11 is formed, via signal lines. In this case, it is important to reduce the number of signal lines from the viewpoint of manufacturing costs and the like. In the case of the example shown in FIG. 1, the number of signal lines equal to the number of operation keys SW ₁ to _{SW o} is required, which is not preferable. In the case of the example shown in FIG. 2, if the comparison circuits 12 ₁ to 12 _o and the resistors R ₂₁ to R _2o are incorporated into the board forming the system controller 11, there is an advantage that the number of signal lines can be reduced to one. In the case of the example shown in FIG. 3, as described above, the number of input ports can be significantly reduced, so if the encoder 13 is incorporated into the keyboard side, the number of signal lines can naturally be reduced significantly. In the case of the example shown in FIG. 4, the number of signal lines inevitably increases because the number of signal lines is equal to the number of input ports for key input signals and output ports for scan pulse output. As described in detail above, none of the examples shown in FIGS. 1 to 4 can satisfy all of the numbers of input/output ports, simultaneous operations, and number of signal lines of the system controller 11. [Purpose of the invention] This invention was made in order to deal with the above-mentioned circumstances.It is possible to reduce the number of input/output ports of a microcomputer, enable simultaneous operation, and further reduce the number of signal lines between boards. It is an object of the present invention to provide a key input device that can reduce the number of key inputs. [Summary of the invention] This invention connects one end of n operation keys to each output terminal of an n-ary counter that counts clock pulses, and connects the other end of these n operation keys to the transmission line of the clock pulse. Further, a means for detecting that the power supply voltage is supplied to the n-ary counter and setting it to the initial state is connected to the line for supplying the power voltage to the n-ary counter, A separating means is provided which can separate the key input signal from the composite signal of the clock pulse guided to the transmission line and the key input signal of the operation key. [Embodiment of the invention] Hereinafter, an embodiment of the invention will be described in detail with reference to the drawings. First, a key input device currently being considered to eliminate the above-mentioned conventional drawbacks will be explained using FIGS. 5 and 6. For example, Figure 5 shows
A case in which there are ten operation keys SW ₁ to _{SW 10} is shown as a representative example. One end of each of the operation keys SW ₁ to SW ₁₀ is connected to output terminals Q ₀ to _{Q 9} of the decimal counter 21, respectively. The other ends of the operation keys SW ₁ to SW ₁₀ are grounded via resistors R ₁ to R ₁₀ and connected to the anodes of diodes D ₁ to _{D 10} , respectively. The cathodes of these diodes D ₁ to _{D 10} are commonly connected, and the midpoint of the connection is grounded via a resistor R ₀ and connected to a data input terminal of the system controller 22 . This system controller 22 outputs a clock pulse _P1 for counting and a clear pulse _P2 for clearing the decimal counter 21. The operation of the above configuration will be described with reference to the signal waveform diagram in FIG. FIG. 6a shows the clear pulse _P2 , and FIG. 6b shows the clock pulse _P1 . Figure 6 c to l are decimal counters 21, respectively.
The output waveforms of output terminals Q ₀ to _{Q 9} are shown. Figure 6 m
indicates the timing of generation of key input signals by various operation keys SW ₁ to SW ₁₀ . When the clear pulse _P2 switches from "H" to "L", the decimal counter 21 goes into its initial state and can count the clock pulse _P1 . The output terminal Q0 of the decimal counter ₂₁ shown in the figure is a clear pulse _P2 which changes from “L” to “H”.
When switched to “H”, clear pulse _P2
switches from “H” to “L”, it goes “L” at the timing of the rise of the first clock pulse _P1 .
Switch to . And at this timing, “H”
The terminal that becomes is switched from output terminal Q ₀ to Q ₁ .
Thereafter, similarly, the terminals that become "H" are sequentially shifted from output terminals _Q1 to _Q9 at the rising timing of clock pulse _P1 . After that, when the clear pulse P ₂ switches from "L" to "H", the output terminal Q ₉ becomes "L" and the output terminal Q ₀ becomes "H".
becomes. Due to this operation, decimal counter 2
1, ten pulses are obtained which are time-divided by the repetition period of the clock pulse P1, as shown in FIGS. 6c- ₁ . Therefore, operation key SW ₁
The key input signal of the operation key SW 2 is obtained if it is operated before the timing T ₀ , and the key input signal of the operation key SW ₂ is obtained if it is operated between the timings T ₀ and _{T 1} . The key input signals of the other operation keys SW ₃ to _{SW 10} are obtained in the same way if they are operated when the corresponding output terminals Q ₂ to _{Q 9} are at "H". According to the above configuration, the number of time-sharing signals corresponding to the number of operation keys SW ₁ to SW ₁₀ is used to control each operation key.
This configuration generates key input signals SW ₁ to SW ₁₀ . Therefore, in the system controller 22, only one input port is required for inputting key input signals, and even if operation keys SW ₁ to _{SW 10} are operated at the same time, all operation states can be read. Can distinguish between operations. Note that in configuring the key input device, the system controller 22 requires output ports for the clock pulse P ₁ and clear pulse P ₂ in addition to the input port for the key input signal, but the number of ports is limited to three. does not change no matter how many operation keys are added. Therefore,
As the number of operation keys increases, the number of ports must increase accordingly. Compared to the previous examples of FIGS. 1 to 4, this is very advantageous when there are many operation keys. In this case, if the clock pulse P ₁ and the clear pulse P ₂ are configured in an individual circuit separate from the system controller 22, the number of ports can be reduced to one. Moreover, if the decimal counter 21, resistors _R1 to _R10 , and diodes _D1 to _D10 are incorporated into the keyboard, even if the clock pulse _P1 and clear pulse _P2 are generated by the system controller 22, the keyboard and the system controller 22 As with the input/output ports of the system controller 22, only three signal lines are required to connect the board on which the system controller 22 is formed. This number is constant regardless of the number of operation keys. In this way, by being able to reduce the number of signal lines when the keyboard and system controller boards are separate boards, it is possible to reduce the manufacturing cost of the circuit unit consisting of the operation keys SW ₁ to _{SW 10} , the system controller 22, etc. I can do it. Furthermore, the circuit of this embodiment is not simply a modification of the device shown in FIG. 4 above. That is, in the circuit shown in FIG. 4, the number of output ports of the system controller 11 can be reduced to two by using a quaternary counter, but the number of input ports cannot be reduced to one. This is because if there is only one input port and signal lines corresponding to rows are commonly connected to it, simultaneous operations cannot be distinguished. Further, since the key input device of this embodiment has a single key input signal transmission line, it can also be used as a key input device in a transmitter of a remote control device. Therefore, in the system controller 21, one input port can serve as both the input port for the key input signal from the operation keys of the device body and the key input signal from the transmitter. By the way, if you use the key input device shown in Figure 5,
If the board on which the keyboard is formed and the board on which the system controller 22 is formed are formed on separate boards, as described above, the number of signal lines connecting the boards can be significantly reduced compared to the conventional device. However, when the key input device shown in Figure 5 is applied to the transmitter of a wired remote control device, a signal line _L1 for grounding and a signal line _L2 for power supply voltage supply are required as shown in Figure 7. , there are a total of five signal lines. In FIG. 7, A indicates a keyboard in the transmitter, and B indicates a board on which the system controller 22 is formed in the main body of the device. The present invention has been developed to solve such problems, and FIG. 8 shows a circuit diagram of one embodiment. In FIG. 8, the same parts as in FIG. 7 are given the same reference numerals. Power supply +B is decimal counter 2
1, and is provided on the device main body side, for example, on the board B on which the system controller 22 is formed. This power supply +B is connected to the emitter of transistor Q ₃₁ and also to the base of transistor Q ₃₁ via resistor R ₃₁ . The base of this transistor Q ₃₁ is further connected to the control terminal (CTL OUT) of the system controller 22.
It is connected to the. The collector of transistor Q ₃₁ is the signal line for the power supply of the remote control device
It is connected to the power supply terminal _VDD of the decimal counter 21 via _L2 . The control terminal (CTL
A switching pulse _P3 that controls the on/off state of the transistor _Q31 is output to the output terminal (OUT). In keyboard A, transistor Q ₃₂ ,
The circuit consisting of Q ₃₃ , resistors R ₃₃ to R ₃₆ , and capacitors C ₃₁ and C ₃₂ is a bistable multivibrator. This bistable multivibrator obtains the power supply voltage from the signal line _L2 . The collector of transistor Q ₃₃ , which is one output terminal of this bistable multivibrator, is the clear terminal (CLEAR) of decimal counter 21.
It is connected to the. The clock terminal (CLOCK) of the system controller 22 is connected to the power supply + _B1 via a resistor _R37 , and is connected to the transistor via a resistor _R38 .
Connected to the base of the Q ₃₄ . The emitter of this transistor _Q34 is connected and the collector is a resistor
It is grounded via _R39 and connected to the clock terminal (CLOCK) of the decimal counter 21 via a signal line _L3 for transmitting the clock pulse _P1 in the remote control device. A common connection point of the cathodes of the diodes _D1 to _D10 is connected to the signal line _L3 via a resistor _R40 . Signal line L ₃ , collector of transistor Q ₃₄ , resistor R ₃₉
The connection midpoint x is connected to the negative input terminal of a comparator circuit 23 including, for example, an operational amplifier. The positive input terminal of this comparison circuit 23 is grounded via a resistor _R41 and connected to the power supply + _B2 via a resistor _R42 . The output terminal of the comparison circuit 23 is connected to the data input terminal (DATAIN) of the system controller 22. Bistable multivibrator transistor Q ₃₂
The base of is grounded through a series circuit of diode D ₃₁ and resistor R ₄₃ . Diode D ₃₁ , resistor
The connection midpoint of R ₄₃ is connected to the signal line via capacitor C ₃₃
Connected to L ₃ . A resistor _R44 is inserted between the signal lines _L2 and _L3 . The operation of the above configuration will be described with reference to the signal waveform diagrams of FIGS. 9 and 10. Figure 9a
The switching pulse _P3 shown in the figure changes from “H” to “L”.
Then, the transistor _Q31 is turned on, and the power supply voltage _Vcc shown in FIG. 9d is supplied to the decimal counter 21 from the power supply +B. In a bistable multivibrator, when the power supply current flows through the signal line L ₂ , the collector voltage of the transistor Q ₃₃ , that is, the clear pulse P ₂
is set to be "H" as shown in FIG. 9e. Thereafter, the system controller 22 outputs the clock pulse _P1 shown in FIG. 9b. This clock pulse P ₁ is inverted by transistor Q ₃₄ and guided to point x in the figure. The clock pulse _P1 at point x is shown in FIG. 9f.
At the timing of the first falling edge of the clock pulse _P1 , the potential at the point x in the figure becomes zero. This turns transistor _Q32 off and transistor _Q33 on, reversing the state of the bistable multivibrator. Therefore, the clear pulse _P2 changes from "H" to "L", and the decimal counter 21 is set to the initial state. The output terminal _Q0 of the decimal counter 21 is at "H" when the power is turned on. and decimal counter 21
Clock pulse after is set to initial state
It becomes “L” at the timing of the first clock rise of _P1 . At this time, the terminal that becomes "H" moves to the output terminal _Q1 . Below, similar to the previous figure 5,
The output terminals _Q2 to _Q9 sequentially become "H" at the rising timing of the clock pulse _P1 . Therefore, the output terminals _Q0 to _Q9 are provided with pulse signals that are time-divided at approximately the period of the clock pulse _P1 (see FIG. 9g to K). In this state, by operating the operation keys SW ₁ to SW _o , a key input signal appears at the common connection point of the cathodes of the diodes D ₁ to _{D 10} . This key input signal is resistor R ₄₀ ,
It is led to the illustrated point x via the signal line _L3 . Therefore, a composite signal of the clock signal _P1 and the key input signal is obtained at point x in the figure. Comparison circuit 23
extracts only the key input signal from this composite signal and supplies it to the data input terminal (DATA IN) of the system controller 22. Assume now that the key input signal is not guided to point x in the diagram. Figure 10a
When the clock pulse _P1 shown in FIG. 10 is "H", the transistor _Q34 is turned on, so that the potential at the point x becomes 0 as shown in FIG. 10b. On the other hand, when the clock pulse _P1 is "L", _the transistor _Q34 is turned off, so the _potential at _point The voltage will be V _a . Next, when _the key input signal shown in Figure _10c is guided to point As shown in , it is 0. On the other hand, clock pulse _P1 is “L”
When , transistor _Q34 is turned off, so
By appropriately setting the value of resistor R ₄₀ ,
The potential at the point can be set to _Vb , which is higher than _Va . The comparison circuit 23 is set with a reference voltage V _c having an intermediate value between the voltages V _a and V _b , and is
The key input signal is extracted from the composite signal of the points as shown in FIG. 10e and is supplied to the system controller 22. Due to this behavior, each operation key
The reading timing of SW ₁ to SW ₁₀ is 9th.
The result is something like the one shown in Figure c. In this case, the reading period for each operation key SW ₁ to _{SW 10} is the same as the previous 5th one.
Compared to the one shown in the figure, only the "L" period of the clock pulse _P1 is shorter. Note that the reference voltage V _c of the comparison circuit 23 is set by resistors R ₄₁ and R ₄₂ . As described in detail above, in this embodiment, a bistable multivibrator is connected to the line for supplying the power supply voltage to the decimal counter 21, and when it is detected that the power supply voltage is supplied to the decimal counter 21, 2
1 is set as the initial state. Therefore, a clear pulse transmission line is not required. In addition, the cathodes of diodes D ₁ to _{D 10} are commonly connected to the clock pulse transmission line, and the potential at the connection point is different between when a key input signal is generated and when it is not generated. When an input signal is generated, the comparator circuit 23 separates the key input signal from the composite signal of the connection section. Therefore, the line can be used both as a key input signal transmission line and a clock pulse transmission line. From the above, according to this embodiment, when applied to a key input device in a transmitter of a wired remote control device, three signal lines are connected between the keyboard of the transmitter and the board on which the system controller 22 of the main body of the device is formed. It can be made into a book. FIG. 11 is a circuit diagram showing another embodiment of this invention. This embodiment uses a differentiating circuit consisting of a capacitor C ₃₄ , a resistor R ₄₅ , and a diode D ₃₂ instead of a bistable multivibrator, and uses a decimal counter 2.
1 is set as the initial state. That is,
By differentiating the power supply voltage, the differentiating circuit outputs a differential pulse having a positive polarity at the rising edge thereof. Ten
The advance counter 21 is set to an initial state using this trigger pulse-like differential pulse as a clear pulse. [Effects of the invention] As described above, according to this invention, the number of input/output ports of a microcomputer can be reduced, simultaneous operation is possible, and the number of signal lines between boards can be reduced. equipment can be provided.

[Brief explanation of the drawing]

Figures 1 to 4 are circuit diagrams showing different examples of conventional key input devices, Figure 5 is a circuit diagram showing a currently considered key input device, and Figure 6 explains the operation of Figure 5. 7 is a circuit diagram for explaining the problem of FIG. 6, FIG. 8 is a circuit diagram showing an embodiment of this invention, and FIGS. FIG. 11 is a signal waveform diagram for explaining the operation shown in the figure, and FIG. 11 is a circuit diagram showing another embodiment of this invention. 21... Decimal counter, 22... System controller, 23... Comparison circuit, SW ₁ to _{SW 10} ...
Operation keys, _R0 , _R1 to _R10 , _R31 to _R45 ...Resistance, _D1
~ _D10 , _D31 , _D32 ...Diode, _C31 ~ _C34 ...
Capacitor, Q ₃₁ ~ Q ₃₄ ...transistor.

Claims (1)

[Scope of utility model registration request] a clock pulse generating means for generating clock pulses; an n-ary counter for counting the clock pulses output from the clock pulse generating means; one end thereof is connected to the corresponding output end of the n-ary counter, and the other end is commonly used for transmitting the clock pulses. n number of operation keys connected to the line and a line for supplying the power supply voltage of the n-ary counter, detecting that the power supply voltage is supplied to the n-ary counter and setting this to the initial state. a state setting means, and a key input for separating the key input signal from a composite signal of the clock pulse and the key input signal, which is derived to a connection between the clock pulse transmission line and the other end of the n operation keys. A key input device comprising signal separation means.