JPS6215888B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides a switch signal detection method, and more specifically, a switch signal detection method that digitally detects a switch signal operated by inputting a sensing signal through a plurality of switches to a logic circuit (for example, a CPU) that can perform logic discrimination. Regarding the method. Conventionally, precision equipment and electronic equipment are equipped with a large number of operation switches and input switches, and it is necessary to detect which one of these switches has been operated and input the input information to a processing circuit.
In order to easily configure the circuit, it is necessary to process the circuit using as few wires as possible. Generally, switch detection is performed analog or digitally, but in the case of an analog method, a comparator or window comparator is required on the circuit side that receives the switch signal, whereas in the conventional digital method for detecting a switch signal, two It was possible to detect only one type of switch signal with one electric wire, three types with three electric wires, and seven types with four electric wires, and it was not possible to detect many switch signals with a small number of wires. SUMMARY OF THE INVENTION Therefore, the present invention has been devised in view of this point, and it is an object of the present invention to provide a digital switch signal detection system capable of detecting a large number of switches with a small number of lines. In general, switch detection using a digital method involves two methods: determining the switch input signal corresponding to the scanning (sensing) signal obtained from the output port of a logic circuit (for example, a CPU), and configuring a matrix on the switch side and detecting a digital signal corresponding to each switch. There is a method of inputting coded signals. The present invention follows the former method, and divides the "H" and "L" output signals on the sensing side by resistance and reads them from the two input ports of the CPU to determine the levels of the "H" and "L" outputs. The input data is detected as a digital code obtained from the above two inputs by comparing it with the threshold voltage of the CPU. In this case, in one embodiment of the present invention, input data corresponding to the "H" level of the sensing signal is sent to the CPU.
The input data corresponding to the next sensing signal "L" is stored in the lower two bits of an internal register provided inside the sensor, and the switch input is determined as a total of four bits of data. In this case, the threshold voltage of the CPU is such that when all switches are off, the inputs corresponding to the 1st and 3rd bit positions of the internal register are at the "H" level, and the inputs corresponding to the 0th and 2nd bit positions are at the "L" level. is set to be. In addition, the switch configuration includes, for example, three switches, and one end of each switch is commonly connected to the sensing output, while the other end of the first switch is connected directly, the other end of the second switch is connected through a forward diode, or The other ends of the third switches are connected to respective resistor voltage divider circuits via reverse diodes. With this configuration, the present invention has the advantage that a large number of switch signals can be detected with a small number of lines, the circuit configuration is simple, and switch signals can be detected reliably. Next, one embodiment of the present invention will be described in detail with reference to the accompanying drawings. In FIG. 1, a CPU is a central processing circuit (for example, a one-chip microcomputer) provided in a precision device or an electronic device, and is connected between a power supply terminal Vcc and ground. The output terminal or output port OUT of the CPU generates a scanning signal or sensing signal of a predetermined frequency for detecting the switch signal. This output terminal OUT is connected to the base of the transistor Tr via a resistor R2. The emitter of the transistor Tr is connected to ground, and the collector is connected to the power supply terminal Vcc via a resistor R1. The resistors R1 and R2 and the transistor Tr function as a voltage amplification circuit for the signal appearing at the output terminal OUT of the CPU. Collector side A of transistor Tr is switch SW
It is connected to terminal X of a switch box or remote box SB equipped with SW1 to SW3. One terminal of the switches SW1 to SW3 is commonly connected to this terminal X. On the other hand, the other terminal of switch SW1 is connected directly to terminal Y of the switch box, and
The other terminal of SW2 is connected to Y through a forward diode D1, and the other terminal of SW3 is connected to terminal Y through a reverse diode D2 having a polarity opposite to that of diode D1. Terminal Y of switch box SB is resistor R3, R
4 connection point B, and switches SW1 to SW
The switch signal that has passed through step 3 is voltage-divided at a predetermined ratio and passes through resistor R5 to the CPU, which detects the level of the input signal.
is input to one input terminal INa. On the other hand, resistance R
A voltage divider consisting of resistors R6 and R7 is further connected to the side C passing through the circuit 5, and its voltage dividing point D is connected to the other detection input terminal INb of the CPU. This input terminal
The data input from INa and INb are sent to the CPU respectively.
It is stored in an internal register provided inside. In that case, the switch signal data corresponding to the high level signal of the sensing signal A is stored in the upper two bits of the register, and the switch signal data corresponding to the low level signal is stored in the lower two bits of the register. Input terminal for 3 bits
INa and the 0 and 2 bits of the internal register are respectively stored through the input terminal INb. Further, in the circuit shown in FIG. 1, the resistors R3 and R4 are set to have substantially equal values, and the resistor R1 is set to a sufficiently small value (1/10 or less) compared to R4. Furthermore, R5 to R7 are switches when the threshold voltage is V _T.
When all of SW1 to SW3 are off, selection is made so that a high level signal is input to the input INa and a low level signal is input to the input INb. Next, the operation of the switch signal detection method of the present invention constructed as described above will be explained with reference to the waveform diagram of FIG. Now, set the power supply voltage (Vcc) of the circuit in Figure 1 to 5V,
Also, set the CPU threshold voltage to approximately 1V. Since the power supply voltage is 5V, the sensing signal appearing at point A is a rectangular wave varying from 5V to 0V with a predetermined frequency, as shown in Figure 2a. If all switches SW1 to SW3 are now off (period T1), sensing signal A does not reach point B, and the voltage at point B becomes a value (approximately 2.5V) divided by resistors R3 and R4. On the other hand, point C is the voltage obtained by dividing the voltage at point B by the voltage division ratio of R5 and R6 + R7, and in this case, it is set to a value higher than the threshold voltage (1V) of the CPU, so
The input signal input to the CPU input INa is “H”.
(high)'', and the voltage at point D is a value obtained by dividing the voltage at point C by resistors R6 and R7. Resistance R
6. The value of R7 is selected so that its divided voltage is lower than the threshold voltage, so the input
The input signal input to INb becomes "L (low)". Therefore, the signals read into inputs INa and INb at the timing of "H" of sensing signal A are "1",
The signal becomes "0", while the signals read at the timing of "L" become "1" and "0". Therefore, when all switches are off, the data stored in the internal register is "1010", that is, "A" in hexadecimal code. Next, when switch SW1 is on (period T2), points A and B are in a shorted state,
Since the resistance value of R1 is smaller than R3 and R4, the voltage at point B is almost the same as that at point A. Therefore, when point A is at "H" level, the voltage at points C and D is greater than the threshold voltage, and the signal input to input INa becomes "1", and vice versa when point A is at "L" level. A signal input to input INb that is smaller than the threshold voltage becomes "0". Therefore, the signal stored in the register is "1100", that is, 16
The hex code is "C". Next, when switch SW1 is on (period T3), the diode is connected in the forward direction with respect to point B, so when point A is at "H" level, point B is also at "H" level, and the slave Therefore, the voltage appearing at points C and D is higher than the threshold voltage and becomes "H".
level. On the other hand, when point A is at the "L" level, the current flowing into transistor Tr is cut off by diode D1, so the voltage at point B is lower than Vcc.
3, the voltage is divided by R4, and the point C is higher than the threshold voltage, and the point D is lower than that. Therefore, the data stored in the register becomes "1110" and becomes "E" in hexadecimal code. On the other hand, when switch SW3 is on (period T4), the diode is inserted in the opposite direction to point B. Therefore, when point A is at "H" level, from point A to B
Since no current flows into the point, the voltage at point B is R
3. The voltage at point C is greater than the threshold voltage, and the voltage at point D is smaller. On the other hand, when point A is at "L" level, the current flowing through R3 flows through diode D2 to Tr, so point B becomes "L".
The voltages at points C and D also become smaller than the threshold voltage, and the data stored in the register becomes "1000", that is, "8". The above is summarized in a table as follows.

[Table] In the above, the number of switches was three, but if you want to increase the number of switches (that is, gradually increase the number of switch boxes or remote boxes equipped with up to three switches), how to increase the number of CPU input ports. Then, an analog multiplexer is connected to both the C and D lines, and terminals Y of multiple switchboxes are sequentially connected to point B via the analog multiplexer using a synchronization signal obtained from the CPU, and discrimination is made by the two inputs INa and INb. There is. In any case, three types of switching states can be detected by a switch box (there are three switches) with two electric wires (X, Y),
In addition, by providing two switch boxes (the number of switches is 6) and making the X terminal common (that is, 3 lines), six types of switching states can be identified. By providing three switches (the number of switches is nine) and sharing each X terminal, nine types of switching states can be identified, and a large number of switching states can be detected with a small number of wires.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an outline of the apparatus of the present invention, and FIG. 2 is a signal waveform diagram showing waveforms appearing in each part of the circuit shown in FIG. CPU... Central processing unit, SB... Switch box, SW1 to SW3... Switch, T1... Period when all switches are off, T2... Period when switch SW1 is on, T3... Period when switch SW2 is on, T
4...Period when switch SW3 is on.

Claims (1)

[Claims] 1. A switch signal that can digitally detect a switch signal operated by inputting a sensing signal that alternately repeats high and low levels through a plurality of switches to a logic circuit capable of logical discrimination. In the detection method, two sensing signals having at least a level difference are formed by dividing the sensing signal through the operation switch, and each sensing signal is inputted to the related input, respectively, and the high level and low level of the sensing signal are divided. The switch signal detection method detects the operation switch signal as a digital code of the signal obtained from the two inputs by comparing the level of the input sensing signal at the time with the threshold voltage of the logic circuit. 2 The plurality of switches are composed of three switches, one end of each switch is commonly connected to the switch signal output, the other end of the first switch is directly connected, and the other end of the second switch is connected to the forward direction. 2. The switch signal detection method according to claim 1, wherein the other end of the third switch is connected to a voltage dividing circuit through a reverse diode to divide the voltage of the sensing signal. 3. When the sensing signal is at a high level, the switch signals input to the two inputs are input to predetermined bit positions of the internal register of the logic circuit, and when the sensing signal is at a low level, the switch signals input to the two inputs are input to the other registers. Claims 1 or 2 wherein the switch signals are stored in predetermined bit positions and detected as a 4-bit digital code.
The switch signal detection method described in .