JPS6350123A - High speed gray code/binary code converting circuit - Google Patents

High speed gray code/binary code converting circuit

Info

Publication number
JPS6350123A
JPS6350123A JP19278586A JP19278586A JPS6350123A JP S6350123 A JPS6350123 A JP S6350123A JP 19278586 A JP19278586 A JP 19278586A JP 19278586 A JP19278586 A JP 19278586A JP S6350123 A JPS6350123 A JP S6350123A
Authority
JP
Japan
Prior art keywords
code
eor
binary code
gray code
high speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19278586A
Other languages
Japanese (ja)
Inventor
Kohei Hasegawa
長谷川　公平
Tetsuya Okamura
哲也 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Heavy Industries Ltd
Original Assignee
Sumitomo Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Heavy Industries Ltd filed Critical Sumitomo Heavy Industries Ltd
Priority to JP19278586A priority Critical patent/JPS6350123A/en
Publication of JPS6350123A publication Critical patent/JPS6350123A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the conversion time by using a carry look-ahead system. CONSTITUTION:A converting circuit which uses a carry look-ahead system for converting the gray codes of 6 bits of Cn+1-Cn-5 to binary codes of Bn-Bn-5 can be formed by using only a 2-input exclusive OR (EOR) and a 3-input exclusive OR (EOR). In such a state, Cn+1 is inputted to EORs 3, 4, 5, 8, 9, and 10, Cn is inputted to EORs 1, 2 and 3, and Cn-1 and Cn-2 are inputted to the EORs 1, 2, and the EOR 2, respectively. Also, outputs of the EOR 1 and the EOR 2 are inputted to the EOR 4 and the EOR 5, respectively, and outputs of the EORs 3, 4 and 5 are obtained as Bn, Bn-1 and Bn-2, respectively. In such a way, by using the carry look-ahead system, the conversion time is shortened, and the gray code can be converted to the binary code at a high speed.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明はグレイコードをバイナリコードに変換する変
換回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a conversion circuit that converts a Gray code into a binary code.

（従来技術） 従来から、アブソリュートエンコーダの検出精度を高め
、また誤動作を防止するためにグレイコードで検出値を
出力し、これをバイナリコードに変換して用いることが
行われている。(Prior Art) Conventionally, in order to improve the detection accuracy of an absolute encoder and prevent malfunctions, detection values have been output in Gray code, and this has been converted into binary code for use.

（この発明が解決すべき問題点） こうした従来型のグレイコードからバイナリコードへの
変換回路は第２図に示した様に最下位のビットＧｏが変
換終了するには最上位のビットＧやが変化してからｎ段
の排他ＯＲゲートを経由する必要があった。このため、
変換時間Ｔは１段当りのゲート遅延時間を△ｔとすると
Ｔ＝ｎ△ｔ となりビット長が長くなるにつれて変換時間は比例して
増大する。(Problems to be Solved by the Invention) As shown in Figure 2, in this conventional Gray code to binary code conversion circuit, it takes until the most significant bit G to complete the conversion of the lowest bit Go. After the change, it was necessary to pass through an n-stage exclusive OR gate. For this reason,
The conversion time T is expressed as T=nΔt, where Δt is the gate delay time per stage, and as the bit length becomes longer, the conversion time increases in proportion.

そこで、この発明は前記の様な従来型グレイコード・バ
イナリコード変換回路の変換時間を短縮するグレイコー
ド・バイナリコード高速化変換回路を提供することを目
的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a high-speed Gray code/binary code conversion circuit that shortens the conversion time of the conventional Gray code/binary code conversion circuit as described above.

（発明の構成） この発明によるグレイコード・バイナリコード高速化変
換回路はキャリールックアヘッド方式を用いて変換時間
の短縮を図る点に特徴がある。(Structure of the Invention) The Gray code/binary code high-speed conversion circuit according to the present invention is characterized in that it uses a carry look-ahead method to reduce conversion time.

（実　施　例） 以下、図示するこの発明の実施例により説明する。第１
図に、この発明の実施例のブロック図を示したが、２人
力排他的ＯＲ（ＥＯＲ）及び３人力排他的ＯＲ（ＥＯＲ
）だけを用いてＧＡ／Ｉ−１〜Ｇヘーｔまでの６ビツト
のグレイコードをＢ７〜Ｂ、ＰＬ−ｒＯ）バイナリコー
ドに変換するキャリールックアヘッド方式を用いた変換
回路を容易に形成できる。(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
A block diagram of an embodiment of the present invention is shown in FIG.
), it is possible to easily form a conversion circuit using the carry look-ahead method that converts the 6-bit Gray code from GA/I-1 to G-hat to B7-B, PL-rO) binary code.

ここで、Ｇへ令１はＥＯＲ３，４，５，８，９゜１０に
入力され、Ｇ〜はＦＯＲ１，２，３に入力され、Ｇ、ｅ
、−１はＥＯＲ１、２、Ｇ、、−＞はＥＯＲ２に入力さ
れる。さらに、ＥＯＲ１及びＥ０１？　２の出力はＥＯ
Ｉ？　４及びＥＯＲ５に各々入力され、ＥＯＲ３，４，
５の出力が各々ＢＱＶ、Ｂ、ノ、Ｂ−一、として得られ
る。（以下、省略する） 一般に、ｎ入力までの排他的ＯＲを用いてｎ・（ｎ−１
）ビットまでのキャリールックアヘッド方式を用いた変
換回路を形成する゛ことができる。Here, G order 1 is input to EOR3, 4, 5, 8, 9°10, G~ is input to FOR1, 2, 3, G, e
, -1 is input to EOR1, 2, G, , -> is input to EOR2. Furthermore, EOR1 and E01? The output of 2 is EO
I? 4 and EOR5, respectively, and EOR3, 4,
5 outputs are obtained as BQV, B, ノ, and B-1, respectively. (Hereinafter omitted) Generally, using exclusive OR up to n inputs, n・(n-1
) It is possible to form a conversion circuit using the carry lookahead method up to bits.

この変換回路での変換時間はＢ、−３で２ゲート。The conversion time in this conversion circuit is B, -3 and 2 gates.

Ｂ＊−ｔで３ゲートを経由しており、第２図の従来方式
の各々３ゲート、５ゲートの経由に比べて格段に速くな
る。B*-t passes through three gates, which is much faster than the conventional system shown in FIG. 2, which passes through three gates and five gates.

（発明の効果） この発明によるグレイコード・バイナリコード高速化変
換回路の実施例は以上の通りであり、次に述べる効果を
挙げることができる。(Effects of the Invention) The embodiments of the Gray code/binary code high-speed conversion circuit according to the present invention are as described above, and the following effects can be achieved.

キャリールックアヘッド方式を用いることで変換時間を
短縮化し、グレイコードを高速でバイナリコードに変換
することができる。By using the carry lookahead method, conversion time can be shortened and Gray code can be converted into binary code at high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は実施例の回路ブロック図、第２図は従来例のブ
ロック図である。 Ｇ柑ｌ〜Ｇボ・・・グレイコード＋８４ｙ〜Ｂへ寸・　
・　・バイナリコード。FIG. 1 is a circuit block diagram of an embodiment, and FIG. 2 is a block diagram of a conventional example. G Kanl~G Bo...Gray code +84y~B to size・
・ ・Binary code.

Claims (1)

【特許請求の範囲】 グレイコードからバイナリコードにコード変換する変換
回路において、 キャリールックアヘッド方式を用いたことを特徴とする
グレイコード・バイナリコード高速化変換回路。[Claims] A high-speed Gray code/binary code conversion circuit, characterized in that the conversion circuit converts a code from a Gray code to a binary code, using a carry look-ahead method.
JP19278586A 1986-08-20 1986-08-20 High speed gray code/binary code converting circuit Pending JPS6350123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19278586A JPS6350123A (en) 1986-08-20 1986-08-20 High speed gray code/binary code converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19278586A JPS6350123A (en) 1986-08-20 1986-08-20 High speed gray code/binary code converting circuit

Publications (1)

Publication Number Publication Date
JPS6350123A true JPS6350123A (en) 1988-03-03

Family

ID=16296956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19278586A Pending JPS6350123A (en) 1986-08-20 1986-08-20 High speed gray code/binary code converting circuit

Country Status (1)

Country Link
JP (1) JPS6350123A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126831A (en) * 1987-11-12 1989-05-18 Matsushita Electric Ind Co Ltd Code conversion logic circuit
KR20200028885A (en) 2017-07-11 2020-03-17 사노 인더스트리얼 캄파니 리미티드 Gripping device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126831A (en) * 1987-11-12 1989-05-18 Matsushita Electric Ind Co Ltd Code conversion logic circuit
KR20200028885A (en) 2017-07-11 2020-03-17 사노 인더스트리얼 캄파니 리미티드 Gripping device

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