JPH0458322A - Preceding '1' detecting circuit - Google Patents

Abstract

PURPOSE:To improve the operating speed when the preceding '1 bit' exists in a lower place by detecting the data obtained by dividing the binary data, including '1' and positioned in the highest place through a 1st preceding 1-position detecting part and at the same time detecting the preceding 1-positions of the divided data through plural 2nd preceding 1-position detecting part independently of each other. CONSTITUTION:The presence or absence of the bit '1' is detected after an OR is secured among the divided binary data. Then a 1st preceding 1-position detecting part 20 detects the preceding '1 bit', and the divided data of the highest place is specified among those divided data including the bit '1' respectively. At the same time, the preceding '1 bit' is detected with a small number of bits after the divided data are inputted to the divided 2nd preceding 1-position detecting parts 21 - 28 respectively. Then the preceding '1 bit' of the binary data is detected by the outputs of the parts 21 - 28 and the output of the part 20. Thus the operating speed is improved when the preceding '1 bit' exists in a lower place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a leading 1m output circuit for detecting the number of consecutive zeros from the most significant bit (MSB) of binary data.

[Prior Art] Systems that perform floating point operations generally use a standardized data format (IEEE754). This data format is such that the MSB of the mantissa is always "1", and conversion to this data format is called normalization. In order to perform this normalization, conventionally M
A leading 1 detection circuit is used which determines the number of data shifts by detecting the number of consecutive "0"s from the SB and encoding the detection result.

FIG. 7 is a block diagram showing the configuration of a conventional 8-bit advance 1 detection circuit.

This leading 1 detection circuit detects 8-bit binary data D1+D
21... Latch circuit 1 that latches +Ds, respectively;
Only the bit that is set to "1" first (hereinafter referred to as the leading 1 bit) from the MSB of the binary data latched in this latch circuit 1 is outputted as "1", and the other bits are "0".
``'' (hereinafter referred to as the preceding 1 position data), and the preceding 1 position data output from the preceding 1 position detecting section 2 are encoded,
It is composed of an encoder 3 that calculates the number of data shifts, and a path buffer 7 that drives a data bus 27 based on the output of the encoder 3.

The latch circuit 1 receives a control signal C that provides latch timing.
8, binary data D+ (i is 1°2,...,8
; the same applies hereinafter)) is incorporated into the clocked inverter 1.
1. and a 1-bit latch 12 that holds the data Dr'lr taken in by this clocked inverter IL.
．． And this 1 bit latch 12. Data D held in
Inverter 13 which inverts and outputs I. It is made up of.

Further, the preceding first position detection section 2 is configured as follows. That is, the carry line 16 carries binary data D1 to
8 transfer gates 14□, each corresponding to D8
~148 are inserted in series. On the other hand, latch circuit 1
The output of 15. is supplied to the gate of transfer gate 14+, and the output of is input to one input end of the . This NOR gate 15. A signal from the carry line 16 is input to the other input terminal of the carry line 16 .

Further, a P-channel transistor 17 for precharging the carry line 16 is connected between the carry line 6 and the power supply terminal, which is controlled by the clock signal CLK. In addition, the carry line 16 is
The end on the SB side is grounded via a carry buffer consisting of an N-channel transistor 18.

A control signal C2 for manual carry is supplied to the gate of this N-channel transistor 18.

The encoder 3 includes a plurality of dynamic lines 22, . 2
2°, 223, and these dynamic lines 22. ~
P-channel transistor 21.223 for precharging according to clock signal CLK. ．． 21□, 213
is selectively connected between the dynamic lines 221 to 223 and the ground terminal, and is controlled on/off by the output of the preceding 1 position detection section 2 to connect the dynamic line 2
A plurality of N-channel transistors 2 on 21 to 223 generate a 3-bit encoded output of the preceding 1 position data.
3. ~231°.

Further, the pass buffer 7 includes a clocked inverter 24 . ．． 24°, 243 and 1 bit latch 25. ．． 2
5□, 253 and 1 bit latch 25□ to 25 inserted between each bit line of the data bus 27 and the ground terminal.
3 and pass buffers 26□, 26□, and 263 driven by the bus output control signal BOC.

Next, in the preceding 1 detection circuit configured in this way,
Now, the input binary data D1 to D8 is “00011”.
The operation when the value is 000'' will be explained.

When the data is latched into the latch circuit 1 in synchronization with the control signal C8, the output of the latch circuit 1 becomes “11100111.
”, so the transfer gates 141 to 143,1
4e to 148 are on, transfer gates 144, 14
5 is off. Further, the carry line 16 is precharged by P channel transistors 17□-178.

Here, when the control signal C2 becomes H level, the N-channel transistor 18 is turned on, so a carry is input, and the carry line 16 up to the stage before the transfer gate 144 changes to L level. However, since the transfer gate 144 is in the off state, the carry line 16 at the stage subsequent to the transfer gate 144 maintains the H level. Therefore, only the output of the NOR gate 154 becomes "1", and the output of the other NOR gates 151 to 153 becomes "1".
．． All outputs from 158 to 158 become "0".

Then, the output of this preceding 1 position detection section 2 is transmitted to the encoder 3.
The encoder 3 outputs 3-bit data indicating the number of shifts. This 3-bit data is
It is latched by 1-bit latches 251 to 253 and output to data bus 27 when bus output control signal BOC becomes active.

[Problems to be Solved by the Invention] However, in the conventional leading 1 detection circuit described above, there is a problem that the lower the leading 1 bit is, the heavier the load on the carry line becomes, and the longer it takes for the carry to propagate. There is.

In other words, near the most significant bit of binary data, for example, MS
When "1" appears in B-1, the N-channel transistor E8 serving as a carry buffer only needs to drive the carry line 16 by one bit corresponding to the MSB. When "1" appears in , all the transfer gates from MSB to MSB-6 are in the on state, which causes a problem that the load on the carry line to be driven increases and the operating speed decreases. This tendency becomes more noticeable as the number of register bits increases.

The present invention has been made in view of such problems, and includes:
To provide a leading 1 detection circuit which can prevent a carry propagation speed from decreasing even when a leading 1 bit exists in a lower order, and can greatly improve operating speed.

[Means for Solving the Problems] A leading 1 detection circuit according to the present invention inputs binary data and outputs leading 1 position data indicating the position of the first bit set to 1 when viewed from the most significant bit side. A leading 1 position detecting means and an encoder that encodes the output of the leading 1 position detecting means are developed, and the leading 1 position detecting means is connected to a carry line and serially connected to the carry line in correspondence with the binary data. a plurality of carry dividing means for selectively dividing the carry line in a portion where the bit value of the binary data is 1; a means for precharging the carry line; and a plurality of carry dividing means provided at one end of the carry line. a carry buffer that drives the carry line and propagates the carry from the most significant bit side of the binary data to each of the carry dividing means; A leading 1 detection circuit is provided with means for outputting a logic value of the input binary data and a logical operation result of the input binary data. and a first preceding 1 position detection unit that outputs data indicating the position of the bit where 1 is set first as viewed from the most significant bit side of the output of the OR means, The preceding one position detecting means is divided into a plurality of second preceding one position detecting sections each inputting the divided data, and the output of each of the second preceding one position detecting sections is equal to the first preceding one position detecting section. It is characterized in that it is controlled by the output of the preceding one position detection section.

[Operation] In the present invention, by dividing binary data and calculating the logical sum of these divided data, it is detected whether or not a bit "1" exists in each divided data. and,
By detecting the leading 1 bit in the first leading 1 position detection section for the logical sum result, it is possible to specify the most significant divided data among the divided data containing bit "1".

On the other hand, in the present invention, the preceding one position detecting means is divided into a plurality of second preceding one position detecting sections, and the divided data is inputted to each of these second preceding one position detecting sections. In the leading 1 position detection section 2, the leading 1 bit is detected using a small number of bits. Then, the outputs of these second preceding 1 position detectors and the first preceding 1
The leading one bit of the binary data is detected by the output of the position detection section.

According to the present invention, since the preceding one position detecting means is divided into a plurality of second preceding one position detecting sections, the maximum number of carry propagation bits can be reduced. In other words, when the binary data is, for example, 64 bits, conventionally it was necessary to drive a carry line with a maximum length of 64 bits using one carry buffer, but according to the present invention, this can be increased to, for example, 8 bits. By dividing each bit into eight groups, one carry buffer can drive a carry line with a maximum length of eight bits.

Therefore, according to the present invention, even when the leading bit is present in the lower order, the carry propagation time can be sufficiently shortened, and the operating speed can be significantly improved.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a 64-bit leading 1 detection circuit according to a first embodiment of the present invention.

In Figure 1, 64-bit binary data is 8 bits)
Divided into f parts, 8 latch circuits 11゜1□,...
, 18. These latch circuits II~1
8 outputs are respectively from the preceding 1 position detection section 21 + 22 +
. . , 28, and the preceding 1 position is detected here. The preceding 1 position data output from the preceding work position detection units 21 to 28 is further transmitted to an encoder 3I,
3□, . . . , 38 and encoded into a 3-bit code.

Encoder 3. 38 are output to the data bus 6 via the bus buffer 7.

On the other hand, each 8-bit divided data from latch circuits L to 18 is sent to OR gates 48, 42 . ...It is input in 48. Each OR gate4. ~48 output signals S1+S2+ . . . +S8 as the results of the logical sum operation of each divided data. This logical sum signal S.

~S8 is connected to the preceding 1 position detector 2 via the buffer circuit 5.
It is entered in ゜. The leading 1 position detection unit 2o detects the leading 1 bit of the OR signals S, to S8, and outputs the leading 1 position data to the bus control signal BC.

~B Output to the path buffer 7 as Ca. The pass buffer 7 transfers the output signals to the data bus 6 based on the output control signals BC to BCs of the encoders 3s to 38.

FIG. 2 is a circuit diagram showing the detailed configuration of the buffer circuit 5 and the preceding one position detecting section 2° in FIG. 1.

The buffer circuit 5 includes a two-stage inverter circuit 31 . to which the OR signal Sl is input. ．． 32. It consists of

The leading 1 position detection unit 2° is a conventional leading 1 position detector shown in FIG.
It has the same configuration as the position detection section 2.

Therefore, we omit the details.

Although not shown in FIG. 1, a latch circuit 8 is provided at the output stage of the first position detection section 2°.

This latch circuit 8 is connected to a clocked inverter 33 . and a 1-bit latch 34 provided at its output. It is composed of.

FIG. 3 shows the latch circuit 18 and the preceding 1 position detection section 2 in FIG. 3 is a circuit diagram showing details of the encoder 3 and the portion corresponding to the upper 8 bits of the path buffer 7. FIG. In the circuit of FIG. 3, the same parts as those of the conventional circuit shown in FIG. 7 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

The circuit shown in FIG. 3 differs from the conventional circuit shown in FIG. 7 in the path buffers 2B, 2E3.

This is a signal for activating H.263. In this embodiment, the bus output control signal BOC and the preceding 1 position detection section 2
An AND gate 28 is provided which inputs bus control signals BC, from
I am trying to drive 3.

Moreover, in this circuit, latch circuit 1. The l-bit latches 121 to 128 are supplied to the OR gate 4I in FIG.

Note that the other preceding 1 position detection units 2□-28, encoders 3□-38, and portions corresponding to the lower 56 bits of the bus buffer 7 also have the same configuration as in FIG.

Next, the operation of the preceding 1 detection circuit according to this embodiment configured as described above will be explained.

FIG. 4 is a timing diagram showing the operation of this preceding 1 detection circuit.

First, at the rising edge of the clock signal CLK, the control signal C1
becomes active, and 64-bit binary data is latched into latch circuits 11-18, 8 bits at a time. Subsequently, the control signal C2 becomes active at the falling edge of the clock signal CLK, thereby performing the preceding 1 detection.

Now, for example, the checked 64-bit binary data is
Assuming that this is data in which "1" is set for the first time in the 32nd bit of MSB when viewed from the MSB, the preceding 1st position detection unit 2. ~
24, the leading 1 bit is not detected, and the leading 1 bit is detected at the MSB position by the leading 1 position detecting section 25. Further, in the preceding 1 position detection units 26 to 28, if the input divided data includes bit “1”,
One leading bit is detected.

On the other hand, at this time, all of the logical sum signals S I"'' S4 from the OR gates 41 to 44 are "O", and the logical sum signal S
5 is “1”, OR signal 86 to S8 is “0” or “1”
Therefore, the leading 1 position detection unit 2° detects 5 from the MSB.
The leading 1 bit is detected at the bit. Therefore, among the bus output control signals BC, to BC8, only the control signal BC5 becomes "1"', and the others become "O".

As a result, among the path buffers 7, three path buffers 26. .

Only portions 26□ and 263 become active. As a result, the output of the encoder 36 is output to the data bus 27 when the bus output control signal BOC becomes active.

In this embodiment, even if the leading 1 bit is located at the 33rd bit of the 64-bit binary data,
Preceding 1 position detection section 2. Since this leading one bit is located at the most significant bit, the carry propagation is for one bit. Furthermore, since the leading 1 bit detected by the leading 1 position detection unit 2° is the 5th bit counting from the most significant bit, the carry propagation here is for 5 bits.

As described above, according to this embodiment, 64-bit binary data is divided into 8 bits each, and each 8-bit divided data is sent to eight preceding one-position detectors 2. ~28 and detect it, and from the logical sum signals 81~S8 of each divided data,
Since it is detected which output of the preceding one position detecting sections 21 to 28 is valid, carry propagation is 8 bits at most. Therefore, compared to the conventional
Its operating speed can be significantly improved.

FIG. 5 is a circuit diagram showing the preceding 1 position detecting section 2° and its surroundings in a 64-bit preceding 1 detecting circuit according to the second embodiment of the present invention, and FIG. 6 is a circuit diagram showing the preceding 1 position detecting section 2.
FIG.

The difference between the circuit shown in Fig. 5 and the circuit shown in Fig. 2 is as follows.
In place of the latch circuit 8, an inverter 35. ~35. This is the point where l was inserted.

The circuit shown in FIG. 8 differs from the circuit shown in FIG. 3 in that the bus control signal BC,
3, a 1-bit latch 41. ~41□
The point is that the latch operation of the latches is controlled. Therefore,
In this embodiment, one of the inverters connected in antiparallel that constitute the 1-bit latches 251 to 253 in the pass buffer 7 in FIG. A bus control signal BC is input to one input.

In this embodiment, the bus control signal BC1 obtained from the detection result at the preceding 1 position detection section 2° is used to detect the preceding 1 position data indicating the preceding 1 bit detected by the preceding 1 position detection sections 21 to 28, respectively. Among them, the encode output of the data located at the uppermost side is latched in the path buffer 7, and the other encode outputs are not latched, so 64
Only the leading one bit of the binary data of bits can be detected.

In this case as well, the carry propagation is 8 bits at most, making high-speed operation possible.

[Effects of the Invention] As explained above, according to the present invention, binary data is divided, and among these divided data, the divided data containing "1" and located at the highest position is the first divided data. preceding 1
In addition to the detection by the position detector, the leading 1 position of each divided data is independently detected by the plurality of second leading 1 position detectors, thereby reducing the maximum number of carry propagation bits. be able to.

Therefore, according to the present invention, even when the leading bit is present in the lower order, the carry propagation time can be sufficiently shortened, and the operating speed can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first preceding detection circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram of a first preceding first detection circuit in the same detection circuit.
A circuit diagram showing a position detection section and its peripheral circuit; FIG. 3 is a circuit diagram showing a second preceding one position detection section and its peripheral circuit in the detection circuit; FIG. 4 is a timing diagram showing the operation of the circuit; FIG. 5 is a circuit diagram showing a first preceding 1 position detecting section and its peripheral circuit in a preceding 1 detecting circuit according to a second embodiment of the present invention, and FIG. 6 is a circuit diagram showing a second preceding 1 position detecting section in the same detecting circuit. FIG. 7 is a circuit diagram showing a detection section and its peripheral circuit. FIG. 7 is a circuit diagram of a conventional preceding 1 detection circuit. 1.1o-ig, 8; latch circuit, 2, 2o-28; preceding 1 position detection unit, 3, 31-38; encoder, 4. ~
4a; OR gate, 6: Buffer circuit, 6.27; Data bus, 11. ~118°24□~248; Clocked inverter, 12□~128,25. ~253,34
1-34a, 411-413; 1 bit latch, 141
~148; Transfer gate, 15□~15. ;NO
R gate, 16; carry line, 17. ~178゜2
1□~213; P channel transistor, 18°231
~231□; N-channel transistor, 28; AND
Gate

Claims (1)

[Claims] (1) Leading 1 position detection means for inputting binary data and outputting leading 1 position data indicating the position of the first bit set to 1 when viewed from the most significant bit side; and an encoder for encoding, and the preceding 1 position detecting means includes a carry line and a portion inserted in series in the carry line in correspondence with the binary data so that the bit value of the binary data is 1. a plurality of carry dividing means for selectively dividing the carry line; a means for precharging the carry line; a carry buffer that propagates a carry from the side to each of the carry dividing means, and a logical operation result between the logical value on the carry line appearing by driving the carry buffer after dividing the carry line and the input binary data. a plurality of OR means for inputting a plurality of divided data obtained by dividing the input binary data and outputting a logical sum thereof; and an output of the logical sum means. a first preceding 1 position detection unit that outputs data indicating the position of the bit where 1 is set first when viewed from the most significant bit side of , and the output of each second preceding one position detecting section is controlled by the output of the first preceding one position detecting section. A leading 1 detection circuit characterized by: