JPS6348116B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a halftone dot ROM control device for halftone dot generation used in an image reading and recording device that photoelectrically scans a continuous tone image and converts it into a black and white binary halftone dot image. It is related to.

Conventional Structure and Problems Conventionally, most of the so-called "shading" operations for expressing halftone densities in photographs using black and white binary values have been performed optically using a contact clean.
In recent years, in order to easily perform image processing such as changing the density of an input photographic image or obtaining a recorded image that emphasizes the outline of the image, new binary halftone dots have been developed while scanning and decomposing the image. Electronic shading devices for composing images have been developed.

Conventionally, in order to convert a photograph into a black-and-white binary halftone dot image in this electronic halftone device, a method of generating a halftone dot generation table corresponding to the type of halftone dot shape and halftone dot period by a computer, or a method in which a halftone dot generation table corresponding to the halftone dot shape type and halftone dot period is generated in advance, or A method using a dot ROM in which dot tables and the like are written is adopted.

However, in order to generate the former halftone dot table by computer, it takes time to calculate the halftone dot pattern, and it is necessary to scan and decompose the input photographic image.
It has the disadvantage that the throughput of the entire system cannot be improved in the continuous operation of creating halftone images of values.

On the other hand, one of the latter methods is to fix the halftone ROM to the control board inside the device and treat it as normal computer memory, but the ROM has a limited capacity and can accommodate many halftone tables. I can't.

Furthermore, when reading data from a large memory, a sequence of giving the memory address and reading its contents each time is required, and in particular it is difficult to replace any halftone ROM while the device is operating. However, it has the disadvantage that it is not possible to do so, and there are restrictions on the use of the device.

Purpose of the Invention The basic object of the present invention is to easily change the halftone ROM in which the halftone table has been written by using the operation check display means while the device is in operation. The purpose is to provide flexibility in handling and operation. Even if such a halftone ROM changing device were to be created, a means would be developed that would allow the contents of the data to be continuously read out by simply setting the address where the halftone table attached to the halftone ROM is written. By configuring, you can improve the speed of halftone table reading and
This simplifies the control operations within the computer.

Structure of the Invention In order to achieve the above object, the present invention provides halftone dots.
an address register for controlling the address of read data of the ROM, a data register for controlling the read data of the halftone ROM, a specifying means for automatically specifying an address for reading the halftone ROM by the data register, and the network point rom
The energization control means is provided with a display means for indicating whether or not power is being supplied to the halftone dot ROM for the energization control means.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of the electronic netting device will be briefly explained using FIG.

FIG. 1 shows the configuration of an electronic netting device to which an embodiment of the present invention is applied. In the same figure, 1
2 is an image reading unit that reads an image; 2 is a halftone data forming unit that forms halftone dot data according to information sent from the image reading unit 1; and 3 is a halftone data forming unit that is sent from the halftone data forming unit 2. An image recording section 4 records information, and an operation control section 4 controls the operation of the halftone data forming section 2 . In the above configuration, the halftone data forming section 2 converts the input document image data sent from the image reading section 1 into binary black and white data every time it obtains the input document image data during image scanning. The operation control section 4 determines in advance what shape of halftone dots will be generated before scanning the image, and controls the halftone dot data forming section 2. That is, a halftone ROM control device (not shown) provided inside the operation control section 4 controls the halftone data forming section 2 to form desired halftone image data.

Hereinafter, the halftone dots described above with reference to Fig. 2 will be explained.
The configuration of the ROM control device will be explained.

FIG. 2 shows halftone dots in one embodiment of the present invention.
This shows the configuration of the ROM control device. In the same figure, 13 is an address decoder, and address 1
0 address information 10a, data read/write information 11a of the data read/write line 11,
The data transfer clock information 12a of the data transfer clock line 12 is input, and the address counter signal 16a is input via the address counter load line 16, the address counter increment signal 15a is input via the address counter increment line 15, and the halftone ROM energizing clock line 20 is input. The energizing clock signal 20a is outputted via the energizing clock line 20a, and the reset signal 19a is outputted via the reset signal line 19. In the address decoder 13, an I/O address address for the address register 131 and an I/O address address for the data register 132 are set.

Also, when the address register 131 in the address decoder 13 is selected, the address counter load line 16 is selected, while when the data register 132 is selected, the address counter increment line 1
5, a clock signal similar to data transfer clock information 12 is output. 14 is a data backer which inputs the data information 18a on the data bus 18 and inputs the data information 25 via the data line 25.
Let a be the output. A data buffer 17 inputs data information 27a via a data line 27 and outputs data information 18a via a data bus 18. To read and write this data, the data buffers 14 and 17 are switched by the information 11a of the data read/write line 11.

21 is a data latch, and the halftone dot is activated by the halftone dot ROM energizing clock signal 20a and the reset signal 19a.
A halftone dot ROM energization control signal 29a is outputted via the ROM energization control signal line 29. 22, 23, 24
is an address counter which inputs the data information 25a of the data image 25, the address counter signal 16a of the address counter load line 16, and the address counter increment signal 15a of the address counter increment line 15, and outputs the counter signal via the counter output line. 26 is connected to the address line of the halftone dot ROM 28.

For example, if the capacity of the halftone dot ROM 28 used is 4 kilobytes, there will be 12 address lines to control the halftone dot ROM 28, and three ordinary 4-bit address counters will be required.

Therefore, the address counter signal 26 of the address counters 22, 23, 24 to the halftone ROM 28 is also
There are 12 pieces. These address counters 22-2
4 are connected in cascade, the contents indicated by the address counters 22, 23, 24 are changed to the halftone dot ROM 2 by the address increment signal 15a.
It will control 8 addresses.

This embodiment shows an example of the above case.

Further, the halftone dot ROM 28 has written therein contents such as types of halftone dot shapes, halftone dot synchronization intervals, and a halftone dot generation table. The effective address in the ROM where the halftone dot generation table is written is stored as header information in the head area of the halftone ROM 28, and the halftone dot type and halftone period to be used are selected from the header information. By doing this, the structure is such that the start address of the table is uniquely read out for the required network.

In addition, a power supply 3 is connected to the outside of the halftone dot ROM 28 via a halftone dot ROM energization control signal 29a and a relay section 30.
2 is connected and its read data information 2
7a is read via the data line 27.
31 is a light emitting diode (LED) connected to the relay unit 20 via a resistor 31a, and 33 is an AND circuit whose output is connected to the base of a transistor 34. 35 is an inverter.

The operation of the apparatus configured as described above will be explained below.

First, when reading data in the dot ROM 28, data transfer clock information 12a, address information 10
a and data read/write information 11a,
The address decoder 13 is selected and the data latch 21 is controlled to be "ON" by the ROM energization clock signal 20a. At this time, the ROM energization signal 29a
becomes the logical state “H”, the relay unit 30 operates, and the LED 31 is turned “ON” as a ROM operation confirmation display.
indicate. Since this signal 29a is connected to the power input terminal side of the halftone dot ROM 28, the halftone dot ROM
28 is now operational. In this state,
First, check the type of halftone table you need and the synchronization.
A ROM that reads out the head information stored in the ROM 28 and stores the halftone table.
Extract the start address of. Then, the I/O address of the address register 131 in the address decoder 13 is selected based on the data transfer clock information 12a, the address information 10a, and the data read/write information 11a, and the address counter signal 16a and the information 25a of the data backup 14 are input to the address counter. 22, 23, and 24. If the initial setting data is "O", the contents of the output lines 26 of the counters 22, 23, and 24 are stored in the halftone dot ROM 28.
is set to address "O".

In this way, the areas where the head information is written are checked one after another, and the storage address of the required dot table is found.

Next, the I/O address of the address register 131 is selected by the same method as above, and the address counter signal 16a and the information 25 of the data buffer 14 are
a to the address counters 22, 23, and 24. For example, if the start address of the halftone table is ×100 (hexadecimal), the data buffer 14
The value is sent to the address counter 22,
23 and 24, and is given as the start address of the read address of the halftone dot ROM 28.

Next, when reading the data in the dot ROM 28, the I/O address of the address register 132 in the address decoder 13 is selected using the address information 10a, the data read/write information 11a, and the data transfer clock signal 12a, and the data buffer 1
7, the contents of the halftone ROM 28 are transferred to the data line 27.
read via . At this time, the data to be read is the ROM data indicated by the address counters 22, 23, 24, and after reading the data, the address counters 22, 23, 24 read the I/O of the data register 132 in the address data 13.
By setting the content of the dot ROM 28 at the address to be read, the address increment signal 15a sent from the data register 132 along with a reading instruction from the MPU (not shown) automatically sets the address to 1.
will be counted up. Therefore, if the reading start address is initially set in the address counters 22, 23, and 24 via the address counter load line 16, it is possible to read the contents of the halftone dot ROM 28 continuously every time data is read. In addition, data can be read from any ROM start address. Further, the ROM power supply control signal 29a is applied to the reset terminals of the counters 22, 23, and 24, so that when the power is turned on for ROM reading,
Operates synchronously like OFF control. Note that the data buffers 14 and 17 shown in this embodiment are
When giving the address of the halftone dot ROM 28 using the buffer connected to the data bus 18 of the MPU (not shown), open the data buffer 14 so as to give the start address, and register the address counters 22, 2.
3, 24, and halftone dots.
When erasing the data stored at the address written in the ROM 28, the data buffer 17 is opened and the data is taken into the MPU.

When the contents of the halftone dot ROM 28 have been read, the address information 10a and the data read/write information 11 are
A reset signal 19a is output via the address decoder 13 to reset the data latch 21. At this time, the ROM energization control signal 29a becomes logic "L", the relay section 30 opens, and the LED 31 indicating operation confirmation turns OFF and goes out. Therefore, the halftone dot ROM 28 can be used to write other halftone dot shapes, etc.
When replacing the ROM, it is only necessary to look at the operation confirmation display LED 31 and turn it on when the display is in the OFF state, and there is no need to disconnect the power supply 22 of the device, making the operation extremely simple.

FIG. 3 shows a perspective view of a halftone dot ROM control device in an electronic halftone screen device. In the same figure, 40 is a halftone dot.
The ROM corresponds to 28 in FIG. Reference numeral 41 denotes a display section such as an LED for operation confirmation, which corresponds to the LED 31 in FIG. 42 is a board, and 43 is a connector.

In the above configuration, by installing a dot ROM control device configured as shown in the figure in the control frame of the apparatus, handling such as replacement of the dot ROM 40 as described above becomes easy.

Effects of the Invention As described above, the present invention allows the halftone ROM in which the halftone table is written to be easily changed and installed by using the operation check display means even when the device is in operation, and the device can be handled easily. , and operational flexibility can be provided, and the halftone dots in continuous scanning of the input photographic image can be
When reading the ROM, by simply setting the address where the halftone table has been written once, the contents of that data can be read out continuously, improving the speed of halftone table reading and controlling operations within the computer. can be accelerated.

[Brief explanation of drawings]

FIG. 1 shows a halftone ROM in one embodiment of the present invention.
A block wiring diagram of an electronic meshing device applied to a control device, FIG. 2 shows halftone dots in an embodiment of the present invention.
FIG. 3 is a block diagram of the ROM control device, and is a perspective view of the main parts of the device. 13...address decoder, 131...address register, 132...data register, 22,
23, 24...address counter, 21...data latch, 28...halftone ROM, 30...relay section, 31...LED.

Claims (1)

[Claims] 1. An address register for controlling the address of read data of the halftone dot ROM, a data register for controlling the read data of the halftone dot ROM, and a specifying means for automatically specifying an address for reading of the halftone dot ROM by the data register. and energization control means for controlling the energization for reading the halftone dot ROM, the energization control means having display means for indicating whether or not power is being supplied to the halftone dot ROM. Point ROM controller.