JPS5975762A - Picture processor - Google Patents

Abstract

PURPOSE:To set the sort of a dot shape and dot pitch optionally by setting up previously a several kinds of threshold table which differ in dot shape and dot pitch for newspaper photographs, print pictures, facsimile pictures, etc., and selecting an optional dot shape and dot pitch therein and generating a recording signal. CONSTITUTION:Picture data is outputted from a picture read part and inputted to a latch circuit 6. The 8-bit output data of the latch circuit 6 is compared a size with 8-bit threshold data read out of a storage device 9 by a comparator 10. In a figure, 40 is a data file containing several kinds of threshold data and 41 is an operation commanding table operating by an opertor and an indication is sent to an arithmetic circuit 42 to output the contents of the data file through an interface circuit 43. For example, data #1 threshold window size in the data file 40 is taken out and written in a register or output said data to a signal line 16. The arithmetic circuit 42 also controls the operation of the whole dot signal generating circuit for write clock pulses of a signal line 20, a write mode signal of a signal line 15, etc., by the indication of the operation command table 41.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image processing device used in a general image scanning/recording device, etc. that expresses halftone density in black and white binary in newspaper photographs, printed images, facsimile images, etc. Regarding.

Conventional Structures and Problems Conventionally, many of the so-called "tethering" operations for expressing halftone densities of photographs in black and white binary values have been performed photographically optically using contact screens. In recent years, in order to easily perform image processing such as changing the density of the original image or obtaining a recorded image that emphasizes the contours of the image, new binary halftone dots have been developed while scanning and decomposing the image. Devices for electronic shading that compose images have been developed.

Furthermore, recently there has been a demand for the development of a device that can arbitrarily set the type of halftone dot shape and the interval of the halftone dot period in a device for forming the halftone dots forming the above-mentioned halftone dot image.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned needs, and it is an object of the present invention to provide an image processing apparatus that can arbitrarily set the type of halftone dot shape and the interval between halftone dot periods.

Structure of the Invention The basic structure of the present invention includes a storage device in which threshold data for binarizing an input image signal can be written and read, a selector for switching the writing and reading mode, and an address for specifying the address of the device. It consists of a counter, a register that specifies the repetition period of the address counter, a comparator that compares the contents of the address counter with the contents of the register, and a comparator that compares the input image signal and threshold data. It is divided into a counter that counts pixel clock pulses and a counter that counts main scanning synchronization pulses, and includes a read address counter that specifies the address of the storage device based on the count results of both, and a counter dedicated to write address specification. It is something that

Description of examples Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C are diagrams illustrating a method of converting original image data into binary data. 3A shows original image data, FIG. 2B shows threshold data, and FIG. 1C shows binarized data. The original picture gator Dij is compared in size with the corresponding threshold gator S1, and depending on whether it is larger or not, it is converted into black or white (1 or 0) binary data Pi.

In addition, 1. J is a natural number. Here, threshold data S1
The shape of the binarized halftone dots can be changed in various ways depending on the setting method. In the same figure (13), it is depicted that one threshold value data S1 is prepared in the same number as the original gators Dij, but in the actual device, one threshold value window consisting of a small number of gators is repeatedly expanded and used. are doing. The size of the window is arbitrary, but for example, 4X4, 8X
The size is approximately 8°16x16. Furthermore, the gap between the halftone dot periods can be changed depending on how the threshold value data Sij is set and the size of the window.

In FIG. 2, the shaded area indicates the configuration of an apparatus to which the present invention is applied. In the figure, 1 is an image reading section, 2 is a halftone data forming section, 3 is an image recording section, and 4 is an operation control section. Since the image reading section 1 and the image recording section 3 are similar to a general image scanning/recording device, the halftone data forming section 2 and the operation control section 4, which are related to the present invention, will be explained in detail below. .

The halftone data forming section 2 is a section that converts original image data into binary data each time it is obtained during image scanning, and the operation control section 4
This is the process of preparing what shape of halftone dots will be generated before scanning the image. Since these two circuits are functionally different as described above, they are shown separately in FIG. 2, but since they have many common parts in terms of circuitry, the two circuits will be described together as a halftone signal generation circuit hereinafter.

FIG. 3 is a block diagram showing one embodiment of this halftone signal generating circuit. The 8-bit digital image data that has been converted from the image signal input terminal to the image shown in FIG. This is done by a latch pulse on a signal line 8 output from a generating circuit 7. The 8-bit output gater of the latch circuit 6 is compared in magnitude with 8-bit threshold data read from a storage device 9 by a comparator 1o.

The comparator 10 outputs 1 if the output data of the latch circuit 6 is the same as or thicker than one threshold value data! If it is smaller, a one-hit signal of O is output. The latch circuit 11 takes in the output of the ratio I articulator 10 at the timing of the pixel clock pulse of the signal line 12 output from the timing signal generation circuit 7, and outputs a 1-bit image via the output terminal 13 to the image recording section 3 shown in FIG. Output as a recording signal.

Since the other parts in FIG. 3 are circuits related to threshold data control of the storage device 9, the storage format of one threshold data will be explained first.

FIGS. 4(A) to 4(C) show the configuration of threshold data on the storage device. FIG. 3A shows a threshold window, with the main scanning direction on the right and the sub-scanning direction on the bottom. In this example, it is possible to have a window with a maximum size of 16×16. One threshold value Sij of this window is arranged on the storage device as shown in FIG. The storage device uses an 8 pino) x 256 1 (AM (random access memory). be. In the same figure (C), select the address of the storage device 8
In the bit selector, the lower 4 bits operate independently as a counter for the main scanning pixel clock, and the upper 4 bits operate independently as a counter for the sub-scanning pixel clock. Therefore, if the contents of (C) in the figure are the address of (B) in the figure, and the contents of that address are one threshold value, the threshold pattern of the window in (A) of the figure will be developed over the entire screen.

The write mode signal on the signal line 15 from the generation circuit-r is 1.
8, which is also output from the timing signal generation circuit 7 when
The signal on the bit signal line 16 (one threshold value data) is passed through as is and applied to the storage device 9.

When the write mode signal is Q, the output of the sofa 14 is open. The write mode signal on the signal line 15 still drives the storage device 9, and switches it to the data write state when it is 1 and to the data read state when it is ○, and also drives the selector 17 to 1, and when it is 1, it switches to the data read state. address counter 1
The output of 8 is selected and used as the write address data of the storage device 9, and when the output is ◯, the 8-bit signal of the signal line 19 is selected and used as the read address data. A write clock pulse for the storage device 9 is output from a signal line 20 connected to the timing signal generation circuit 7, and a write end pulse is output from a signal line 21, which serves as a clock pulse for the counter 18. A signal that clears the counter 18 is output from the signal line 22 at the same time as the write mode is entered.

A 4-bit pixel clock pulse counter 23 counts the pixel clock pulses on the signal line 12.

The output of the counter 23 becomes a signal of the lower 4 bits of the read address on the signal line 19. The comparator 24 compares the 4-bit signal on the signal line 25 output from the timing signal generator 7 with the 4-bit signal output from the counter 23.
If the output of
Clear 3.

The signal on the signal line 25 specifies how many pixels to repeat in the main scanning direction using a one-threshold window shown in FIG. 4(A). For example, if 8 is to be repeated, 7 is specified. 27 is a 4-bit main scanning synchronizing pulse counter that counts main scanning synchronizing pulses on the signal line 28. The output of the counter 27 becomes a signal of the upper 4 bits of the read address on the signal line 19. Comparator 29 compares the 4-bit signal on signal line 3o output from timing signal generator 7 with the 4-bit signal output from counter 27, and if the output from counter 27 is thicker, clears counter 27 via OR gate 31. The signal on the signal line 30 is as shown in Figure 4 (
For the threshold value in A), e specifies how many pixels to repeat in the sub-scanning direction. For example, if 8 is to be repeated, 7 is specified.

The main scanning synchronizing pulse on the signal line 28 which generates a timing signal and comes out from the path 7 clears the counter 23 via the OR gate 33 and the OR gate 26. This is to synchronize the reading position of threshold data at the beginning of main scanning. Signal line 3
2 or gate 33 and or gate 2 at the signal
The counter 23 is cleared through the gate 6, and the counter 27 is cleared through the OR gate 31.

In FIG. 6, the timing signal generation circuit 7 of FIG.
It explains the main points.

In FIG. 5, reference numeral 34 denotes a reference clock pulse generation circuit, whose output pulse is frequency-divided by a frequency dividing circuit 35 and outputted to the signal line 28 as a main scanning synchronizing pulse. The main scanning synchronizing pulse is inverted by the input gate 36, the reference clock pulse is gated by the AND gate 37, and input to the signal line 8 +l! i
ii & Outputs the latch pulse of the signal. The latch pulse on the signal line 8 is delayed by about the remaining period of the reference clock pulse in the delay circuit 38, and the pixel clock pulse is outputted on the signal line 12. 39 is a register, the upper 4 bits are the sub-scanning direction threshold window size of the signal line 30, and the lower 4 bits are the signal line 2.
The main scanning direction threshold window size is 5. Note that the contents of the register are set externally.

In FIG. 6, 4o is a data file containing several types of threshold data. Reference numeral 41 denotes an operation command table operated by the operator, which instructs the arithmetic circuit 42 to output the contents of the data file through the interface circuit 43.

For example, by extracting data with a threshold window size of ≠11 from the data file 40 and writing it to the register 39 in FIG.
The threshold window data is output to the signal line 16 in FIG. The arithmetic circuit 42 in FIG. 6 also controls the operation of the entire halftone dot signal generation circuit shown in FIG. 3, such as the write clock pulse on the signal line 2o in FIG. The control is performed based on instructions from the operation command table 41.

Effects of the Invention As described above, according to the present invention, several types of threshold tables with different halftone dot shapes and halftone dot periods obtained by using different threshold window data and threshold window sizes are prepared in advance. It becomes possible to create a recording signal by selecting an arbitrary halftone dot shape or period.

Note that it passes if the threshold window size is set to 1×1.

[Brief explanation of the drawing]

Figures 1 (A) to (C') are diagrams explaining a method of converting original image data into binary data; Figure 2 is a block diagram showing an embodiment in which the present invention is applied to an apparatus; The figure is a configuration diagram of the halftone signal generation circuit of the same embodiment, Figures 4 (A) to (C) are diagrams showing the configuration of threshold data on the storage device, and Figures 5 and 6 are timing signal generation circuits. It is a diagram for explaining the main parts inside. 1...1-side r-elephant reading section, 2...halftone data forming section, 3...image recording section, 4...
...Operation side - control section, 5... Image signal input terminal,
6... Latch circuit, 7... Timing signal generation circuit, 8... Latch pulse signal line,
9...Storage device, 10...Comparator, 1
1... Launch circuit, 12... Pixel clock pulse signal line, 13... Squad recording signal output terminal, 14... 3-state buffer 16 ...
...Write mode signal signal line, 16...Threshold data signal line, 17...Selector, 18...
...8-bit counter, 19...8 bit signal line, 20...Write clock pulse signal line, 21...Write end pulse Signal line, 2
2...--Clear pulse signal line, 23...
4-bit counter, 24... Comparator, 25...
...Main scanning direction threshold window size signal line, 26...
...OR gate, 27...4 bit counter,
28... Main scanning synchronization pulse signal line, 29...
... Comparator, 30 ... Sub-scanning direction threshold window size signal line, 31 ... OR gate, 32 ...
... Counter clear signal line, 33 ... OR gate, 34 ... Reference clock, clock pulse generation circuit,
35... Frequency divider circuit, 36... Inverter, 37... AND gate, 38... Delay circuit, 39... 8-bit register. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure (A+ <BrrL) 2nd upper 2nd part Figure 5 Figure 6

Claims (1)

[Claims] a storage device for storing threshold data for obtaining a binary dot recording signal from an input image signal; an address counter for writing the threshold data at a predetermined position in the storage device; and a main scanning of the threshold data. a register that stores data indicating the window size in the direction and sub-scanning direction; a selector that switches between a write address and a read address of the storage device; and a pixel clock that determines the lower bit or upper bit of the read address of the storage device. a pulse counter; a comparator to compare the contents of the pixel clock pulse counter with data indicating the window size in the main scanning direction of the threshold data; and a comparator to determine the upper bit or lower bit of the read address of the storage device. a comparator that compares the contents of the main scanning synchronizing pulse counter with data indicating the size of a window in the sub-scanning direction of the threshold data, and inputting the threshold data read from the storage device. An image processing device comprising: a comparator for comparing image data.