JPS6347974A - Hetero junction bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce the negative differential collector resistance of a hetero junction bipolar transistor thereby to improve characteristics by providing a lower impurity concentration region than an emitter side at the collector side of a base region having a graded base structure. CONSTITUTION:An emitter region 5 is composed of a semiconductor material having larger band gap than a base region 4, and the composition of a semiconductor material is so varied as to gradually reduce a band gap from the emitter 5 to a collector 3 in the region 4. A region having a smaller impurity concentration than the emitter 5 is provided at the collector 3 in the region 4 in such a hetero junction bipolar transistor. For example, an n<+> type GaAs layer 2, an n-type GaAs layer 3, a p<-> type AlxGa1-xAs layer 41, p<+> type AlxGa1-xAs layer 42, an n-type (AlGa)As layer 5 and an n<+> type GaAs layer 6 are provided on a semi-insulating GaAs substrate 1. The layers 41, 42 are gradually varied in the composition ratio (x) of aluminum from 0 to 0.1 from below to upward.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a heterojunction bipolar transistor using a semiconductor material having a larger bandgap in the emitter region than in the base region.

(Prior Art) It is known that a heterojunction bipolar transistor whose emitter region is made of a semiconductor material with a larger bandgap than a base region has 111 points, which is more than a homojunction bipolar transistor. These advantages are summarized as follows.

■ Even if the ratio of the impurity concentration in the emitter region to the impurity concentration in the base region is small, high emitter injection efficiency can be obtained due to the difference in band gap.

(2) As a result of (2), the impurity concentration in the base region can be increased, and the base resistance can therefore be lowered.

■ Since the impurity concentration in the emitter region can be lowered, the emitter junction capacitance can be reduced.

Because of these advantages, heterojunction bipolar transistors have excellent high frequency characteristics and switching characteristics, and are expected to be used as microwave transistors and high-speed logic transistors.

Furthermore, as a means to improve the performance of transistors, the composition ratio of the semiconductor material is changed so that the bandgap gradually decreases from the emitter region side of the base region to the collector side, and the semiconductor material is injected from the emitter region to the base region. So-called graded base structures are known which provide a built-in accelerating electric field for the carriers. Using this structure provides the following advantages:

(a) The carriers are accelerated in the base region by the built-in electric field, resulting in a velocity greater than the diffusion-limited velocity, reducing the base transit time of the carriers.

(b) Lateral diffusion of carriers in the base region, which becomes a problem when devices are miniaturized, is suppressed, and a decrease in current gain due to miniaturization is prevented.

Because of these effects, the graded base structure is an extremely useful technique for obtaining small transistors that operate at high speed.

FIG. 4 shows a conventional graded base structure.
AI! 1 is a cross-sectional view showing an example of a betero junction transistor using a GaAs/GaAs system.

This is an n0-type GaAs layer 13 which will become a collector region on a semi-insulating GaAs substrate 12. n-type GaAs layer 14,
p medium size A, f? which will be the base region? GaAs
It is constructed using a wafer on which a layer 15 □, an n-type (A, 117Ga) As layer 16 serving as an emitter region, and an n+ type GaAs layer 17 serving as an emitter/cap layer are sequentially epitaxially grown. 152
is a p-type layer which becomes an external base region and is formed by, for example, ion implantation to take out the base electrode. 1
8 is an emitter electrode, 19 is a base electrode, 20 is a collector electrode, 21, . 212 is an insulating layer formed by ion implantation, and 22 is an insulating film such as a 5i02 film. The base region is a p-type A-GaAs layer 151X.
l-x is set so that the impurity l1 degree is uniform and the AJ composition ratio X is zero on the collector side and gradually increases toward the emitter side.

FIG. 5 shows a typical emic ground current-voltage characteristic of a conventional heterojunction transistor having such a graded base structure. As is clear from the figure, there is a strong tendency for the negative differential resistance to increase as the collector current increases, that is, as the current level increases, there is a strong tendency for the collector current to decrease as the collector-emitter bias voltage cε increases. Such a phenomenon makes circuit design difficult when incorporating a petrojunction transistor into an actual circuit. Furthermore, when used as a power transistor, it becomes difficult to obtain sufficient power.

(Problems to be Solved by the Invention) As mentioned above, the conventional heterojunction with a graded base structure has the problem of not being able to obtain sufficient current and power due to the negative differential collector resistance. Ta.

In view of the above points, it is an object of the present invention to provide a heterojunction bipolar transistor whose characteristics are improved by reducing the negative differential collector resistance.

[Configuration of the Invention (Means for Solving Problems) The heterojunction bipolar transistor according to the present invention includes:
It has a graded base structure, and is characterized in that in the base region, a region with a lower impurity concentration is provided on the collector side than on the emitter side.

(Function) With the structure of the present invention, the negative differential collector resistance phenomenon that appears significantly in a heterojunction transistor with a graded base structure can be effectively alleviated. The principle is n
A detailed explanation will be given using a pn transistor as an example.

In a heterojunction transistor with a graded base structure, the base transit time of carriers is significantly reduced. This is because, as mentioned above, a built-in accelerating electric field is created in the base region. At this time, the electrons in the base region, which is about 1000 times thinner, become so-called hot electrons, and the electron temperature in the base region is much higher than the lattice temperature. Not only that, the average velocity of the electronic system can exceed the saturation velocity obtained from the steady state velocity-electric field characteristics.

Next, consider the common emitter current-voltage characteristics of a heterojunction transistor with a graded base structure. Increasing current levels consume more power and generate heat, but the associated increase in transistor temperature increases phonon scattering of electrons. In materials such as compound semiconductors in which polar optical phonon scattering is dominant, electron energy loss due to phonon scattering is large. Therefore,
As the temperature rises, electrons that are hot due to the grated base structure undergo frequent phonon scattering, which causes them to cool down.

This increases the base transit time of electrons, making it easier for electrons and holes to recombine in the base region.

This eventually leads to an increase in the base current, and considering that the common emitter current-voltage characteristic draws a current IC-voltage VCE curve with a constant base current, the base-emitter bias voltage VBE for the same base current becomes smaller, and therefore Collector current becomes smaller. This is the mechanism of negative differential collector resistance. In order to suppress this phenomenon, the early effect can be actively used.

The early effect refers to a phenomenon in which the effective base width becomes narrower due to an increase in VCH, that is, an increase in VBC.

Decreasing the base width with increasing VCE improves base transport efficiency and reduces recombination current in the base region. Therefore, the negative differential collector resistance can be alleviated by compensating for the decrease in the electron velocity in the base due to the temperature increase associated with the increase in the current level by the decrease in the base width due to the increase in VCE. In order to facilitate the Early effect, the impurity concentration on the collector region side of the base region can be set low, but the impurity concentration on the emitter region side of the base region must be kept sufficiently high in order not to increase the base resistance. be. Therefore, by providing an impurity concentration distribution in the base region as in the present invention, the phenomenon of negative differential collector resistance can be effectively alleviated without increasing the base resistance.

(Example) The present invention will be explained in detail below.

FIG. 1 is a sectional view showing a heterojunction transistor according to an embodiment of the present invention using an AlGaAs/GaAs system. To manufacture this transistor, it is first necessary to sequentially epitaxially grow semiconductor layers on the semi-insulating GaAs substrate 1. This epitaxial growth method includes molecular beam epitaxial method (MBE).
method) or metal organic chemical vapor deposition method (MOCVD method). To explain the specific manufacturing conditions in the order of steps, first, on the substrate 1, an n+ type GaAs layer 2, an n type GaAs layer 3, which will become the collector region, and a p- type Ai G layer, which will become the base region.
a As layer 41. p÷ type A no G a 1-xx
1-x
The xAs layer 42 is an n-type (A
) An epitaxial wafer as shown in FIG. 2 is formed, in which a Ga)As layer 5 and an n-sized GaAs layer 6 serving as an emitter cap layer are successively grown. In this embodiment, Be is used as an n-type impurity and a 5tSp-type impurity. For example, the n-type GaAs layer 2 has an impurity concentration of 2x
1018/+1', thickness 5000, n-type Ga
The As layer 3 has an impurity concentration of 5 x 10"/atr' and a thickness of 3,000 layers. The p- layer on the collector side of the base region
Type A J2 Ga t As layer 41 has an impurity concentration of 5
×1017/cIn3° thickness is 300 layers, and the p-type A, GaAs layer 42 on the emitter side has an impurity concentration of 5.
X1018°-x Thickness: 800 people. That is, a region in which the impurity concentration changes stepwise is provided in the base region.

On the other hand, the AlGaAs layer which becomes the base region is 41°x
1-x 42, the Al composition ratio X is gradually changed from 0 to 0.1 from the bottom to the top.

As shown in detail in FIG. 2, the n-type AJGaAs layer 5 serving as the emitter region is composed of an n-type AGa1- or XAs layer 51. Af Ga As layer 52 and 0.3
It consists of 53 layers of 0.7 Af Ga As.

1-x Af Ga As layer 5□ is the base of the heterojunction interface
The l-X band gap changes smoothly, and the composition ratio X increases from 0.1 to 0.
．． It is gradually changing up to 3.

A, &GaAs layer 53 was provided for the same purpose.
l−X, and the composition is changed so that X becomes smaller as it goes up. For example, the thickness is A, ff Ga
300 people have Asl 5+.

X 1-X Af, Ga, As layer 52 has 1500 people.

0.3 0.7 A. CGa As layer: 53 or 500 people.

X]-X Further, the impurity concentration of these three layers is 3X1017/cm3. The n-type GaAs layer 6, which is a cap layer, has an impurity concentration of 2×10”/an3 and a thickness of 1000.

Next, using the epitaxial wafer thus formed, Be+ ion implantation is performed to form a p<0> type layer 43 which becomes an external base region and has a depth that reaches the n<0> type GaAs layer 2 inside the transistor. Next, an insulating layer 10 for element isolation reaching the substrate 1 is formed by H+ ion implantation, and an insulating layer 102 for electrode isolation reaching the n+ type GaAs layer 2 inside the transistor is formed by B+ ion implantation. After locating the emitter, a CV D Si O2 film 11 is formed on the entire surface. After this, in order to make an electrode contact in the collector region, etching is performed from the wafer surface to a depth that reaches the n+ type GaAs layer 2, a thin AuGe layer is formed in this area, and an Au layer is formed on top of this, and the collector region is etched. This is referred to as electrode 9. Furthermore, contact holes are made in the emitter region and base region,
An emitter electrode hr 7 + base electrode 8 is formed by an A u G e layer.

FIG. 3 shows the common emitter current-voltage characteristics of the Peter junction transistor according to this embodiment. As is clear from the figure, the negative differential collector resistance seen in the simple graded base structure is absent, indicating good transistor characteristics.

In the example below, A J Ga As / G
Although a betero junction transistor using an a As system has been described, the present invention can be similarly applied to a case where a combination of other semiconductor materials is used. In addition, in the example,
Although one region in which the impurity concentration changes in a step-like manner is provided in the base region, it is also possible to provide a plurality of regions in which the impurity concentration changes in a step-like manner, or a region in which the impurity concentration changes smoothly. good. Furthermore, the present invention can also be applied to collector top type transistors.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by providing a region on the collector region side of the base region with a lower impurity concentration than the emitter region, the negative differential of a heterojunction transistor with a graded base structure can be reduced. The phenomenon of collector resistance can be alleviated, and good transistor characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a heterojunction transistor according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of its epitaxial wafer, and FIG. 3 is a diagram showing the emitter common current-voltage characteristics. Figure 4 is a cross-sectional view of a conventional heterojunction transistor, and Figure 5 shows its emitter ground current -
FIG. 3 is a diagram showing voltage characteristics. 1...Semi-insulating GaAs substrate, 2...n medium-sized Ga
As layer, 3-n medium GaAs layer (collector region), 4.
・p-type A, II' Ga As layer (base region), 42...p small AJ2 Ga As layer x
1-X (base region), 43...p ten type layer (external base layer), 5-n type (A, f?Ga) As layer (emitter region)
, 6. n+ type GaAs layer (cap layer), 7... emitter electrode, 8... base electrode, 9... collector electrode, 10. ．． 102...Insulating layer, 11...CVD
SiO2 film. Applicant's agent Patent attorney Suzu J. Takehiko No. 1@2 Figure 3

Claims (3)

[Claims] (1) A heterojunction in which the emitter region is made of a semiconductor material with a larger bandgap than the base region, and the composition of the semiconductor material changes such that the bandgap gradually decreases from the emitter side to the collector side within the base region. 1. A heterojunction bipolar transistor, characterized in that a region having a lower impurity concentration on a collector side in the base region than on an emitter side is provided in the bipolar transistor. (2) The heterojunction bipolar transistor according to claim 1, wherein the base region has at least one region in which the impurity concentration decreases stepwise from the emitter side to the collector side. (3) The heterojunction bipolar transistor according to claim 1, wherein the base region has a region where the impurity concentration decreases smoothly from the emitter side to the collector side.