JPS6347262B2 - - Google Patents
Info
- Publication number
- JPS6347262B2 JPS6347262B2 JP56212872A JP21287281A JPS6347262B2 JP S6347262 B2 JPS6347262 B2 JP S6347262B2 JP 56212872 A JP56212872 A JP 56212872A JP 21287281 A JP21287281 A JP 21287281A JP S6347262 B2 JPS6347262 B2 JP S6347262B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- window
- external circuit
- semiconductor element
- photoresist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000000919 ceramic Substances 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子の接続方法に関するもの
で、半導体素子と外部回路基板の電極を、金属線
などからなるリードをブリツジをもたせず高密度
に接続し、信頼性の向上と生産性の向上を目的と
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for connecting semiconductor elements, and improves reliability by connecting leads made of metal wires or the like between semiconductor elements and electrodes of an external circuit board with high density without any bridges. and to improve productivity.
従来の接続方法として、第１図に示すように、
ベース６の上に半導体素子１と外部回路基板２を
固定し、半導体素子１の電極５と外部回路基板２
の電極導体４を、金線又はアルミ線等の金属線７
により、１本１本熱圧着又は超音波接合して行く
方法や、第２図に示すように、金属箔より形成さ
れた電極導体７′を一度で熱圧着する方法や、第
３図に示すように、耐熱性フイルム８により支持
された微細な金属箔電極導体７″を一度の熱圧着
により複数個同時に接続する方法がある。 As a conventional connection method, as shown in Figure 1,
The semiconductor element 1 and the external circuit board 2 are fixed on the base 6, and the electrode 5 of the semiconductor element 1 and the external circuit board 2 are fixed on the base 6.
The electrode conductor 4 is connected to a metal wire 7 such as a gold wire or an aluminum wire.
There are two methods: thermo-compression bonding or ultrasonic bonding one by one, as shown in FIG. There is a method of simultaneously connecting a plurality of fine metal foil electrode conductors 7'' supported by a heat-resistant film 8 by one thermocompression bonding.
上記した３つの従来の接続方法は、いずれも高
密度な接続が可能であるが、半導体素子の電極５
と外部回路基板の電極導体４との間に、金属線又
は金属箔からなるブリツジ状リード７，７′，
７″を持ち、このブリツジ状リードの機械的強度
不足により、第４図に示すようにブリツジ状リー
ド７が破断し、それにより導通不良が発生した
り、また第５図に示すようにブリツジ状リード７
の曲りにより短絡が発生し、接続後の信頼性に欠
け、取扱いに非常に注意をはらわねばならなかつ
た。また、生産性については、１つの接続又は半
導体素子１個に費す接続時間が決るので、半導体
素子が複数個になればその個数分だけ長く接続時
間がかかり、量産によるメリツトが出にくかつ
た。さらに、接続時に熱圧着するため、局部的で
はあるが200℃以上の高温を半導体素子が受ける
ため、熱に敏感な素子では特性に影響を及ぼす事
があつた。またさらに、熱圧着する治具の大きさ
や、金属箔の微細電極導体を形成する都合上、高
密度（６〜20本／mm）な電極接続を行う事は、困
難であつた。 The three conventional connection methods described above are all capable of high-density connection, but
Bridge-shaped leads 7, 7', made of metal wire or metal foil are connected between the electrode conductor 4 of the external circuit board and the electrode conductor 4 of the external circuit board.
7'', and due to insufficient mechanical strength of this bridge-shaped lead, the bridge-shaped lead 7 may break as shown in FIG. lead 7
Short circuits occurred due to bending of the wires, resulting in a lack of reliability after connection, and great care had to be taken when handling the wires. Regarding productivity, the connection time required for one connection or one semiconductor element is determined, so if there are multiple semiconductor elements, the connection time will be longer for the number of semiconductor elements, making it difficult to realize the benefits of mass production. Ta. Furthermore, since thermocompression bonding is used during connection, semiconductor elements are exposed to localized high temperatures of 200°C or more, which can affect the characteristics of heat-sensitive elements. Furthermore, it has been difficult to perform high-density electrode connections (6 to 20 wires/mm) due to the size of the jig for thermocompression bonding and the convenience of forming fine electrode conductors of metal foil.
本発明は、以上の問題点を解決するためになさ
れたもので、半導体素子と外部回路基板の電極接
続部上に、フオトレジスト膜による窓部を形成
し、その窓部に導電性ペーストを形成する事によ
り、従来のような中間のブリツジ状リードを廃
し、信頼性のある半導体素子の接続が容易に得ら
れる半導体素子の接続方法を提供することを目的
とする。 The present invention has been made to solve the above problems, and involves forming a window section using a photoresist film on the electrode connection section between a semiconductor element and an external circuit board, and forming a conductive paste on the window section. It is an object of the present invention to provide a method for connecting semiconductor elements, which eliminates the need for a conventional intermediate bridge-like lead and allows reliable semiconductor element connections to be easily obtained.
以下、本発明を、LEDアレイ素子の接続に適
用した実施例に基いて、図面を参照しながら説明
する。 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on an embodiment in which the present invention is applied to connection of LED array elements.
第６図ａ〜ｃは本発明の一実施例を示す工程図
である。まず、第６図ａに示すように、中央に発
光部１０を持つLEDアレイ素子である半導体素
子１の端面１′と多層セラミツク基板である外部
回路基板２の端面２′を密着させ、半導体電極５
と外部回路基板の電極導体４の位置を合せて、ベ
ース６に接着剤９により固定する。次に第６図ｂ
に示すように、フオトレジスト膜１１を半導体素
子１上および外部回路基板２上にわたつて全面に
形成し、半導体素子１の電極５と外部回路基板２
の電極導体４との接続部上のフオトレジスト膜１
１に窓部１２を形成する。その後、窓部１２に導
電性ペースト３を塗布し、フオトレジスト膜１１
表面についた余分な導電ペーストを取り除いた
後、導電ペースト３を硬化し、フオトレジスト膜
１１を剥離することにより、第６図ｃに示すよう
に、導電性ペースト３で半導体素子１の電極５と
外部回路基板２の電極導体４を接続する。 FIGS. 6a to 6c are process diagrams showing one embodiment of the present invention. First, as shown in FIG. 6a, the end surface 1' of the semiconductor element 1, which is an LED array element having a light emitting part 10 in the center, and the end surface 2' of the external circuit board 2, which is a multilayer ceramic substrate, are brought into close contact with each other, and the semiconductor electrode 5
and the electrode conductor 4 of the external circuit board are aligned and fixed to the base 6 with adhesive 9. Next, Figure 6b
As shown in FIG. 2, a photoresist film 11 is formed over the entire surface of the semiconductor element 1 and the external circuit board 2, and the electrodes 5 of the semiconductor element 1 and the external circuit board 2 are covered with a photoresist film 11.
photoresist film 1 on the connection part with the electrode conductor 4 of
A window portion 12 is formed in 1. After that, the conductive paste 3 is applied to the window portion 12, and the photoresist film 11 is coated with the conductive paste 3.
After removing the excess conductive paste on the surface, the conductive paste 3 is cured and the photoresist film 11 is peeled off, thereby bonding the conductive paste 3 to the electrodes 5 of the semiconductor element 1, as shown in FIG. Connect the electrode conductor 4 of the external circuit board 2.
第７図ａ〜ｃは本発明の他の実施例を示す工程
図である。まず、第７図ａに示すように、中央部
に発光部１０を持つLEDアレイ素子である半導
体素子１上に、電極５の端部に一端開口の窓部１
２′を有するフオトレジスト膜１３を形成し、多
層セラミツク基板である外部回路基板２上に、電
極導体４の端部に一端開口の窓部１２″を有する
フオトレジスト膜１４を形成する。次に第７図ｂ
に示すように、半導体素子１と外部回路基板２
の、それぞれの対応する電極５，４の位置合せを
行ない、ベース６上に接着剤９により素子１と基
板２とを固定することにより、半導体素子１上の
フオトレジスト膜１３の窓部１２′と外部回路基
板２上のフオトレジスト膜１４の窓部１２″によ
り、半導体素子１上の電極５と外部回路基板２上
の電極導体４の接続部上に窓部１２を形成する。
その後、窓部１２に導電性ペースト３を塗布し、
フオトレジスト膜１３，１４の表面についた余分
な導電性ペーストを取り除いた後、導電性ペース
ト３を硬化し、フオトレジスト膜１３，１４を剥
離することにより、第７図ｃに示すように、導電
性ペースト３で半導体素子１の電極５と外部回路
基板２の電極導体４を接続する。 FIGS. 7a to 7c are process diagrams showing another embodiment of the present invention. First, as shown in FIG. 7a, a window 1 having one end open at the end of the electrode 5 is placed on the semiconductor element 1 which is an LED array element having a light emitting part 10 in the center.
A photoresist film 13 having a diameter 2' is formed, and a photoresist film 14 having a window 12" with one end open at the end of the electrode conductor 4 is formed on the external circuit board 2, which is a multilayer ceramic substrate. Figure 7b
As shown in FIG.
By aligning the corresponding electrodes 5 and 4 and fixing the element 1 and the substrate 2 on the base 6 with adhesive 9, the window 12' of the photoresist film 13 on the semiconductor element 1 is formed. A window 12 is formed on the connection portion between the electrode 5 on the semiconductor element 1 and the electrode conductor 4 on the external circuit board 2 by the window 12'' of the photoresist film 14 on the external circuit board 2.
After that, a conductive paste 3 is applied to the window portion 12,
After removing the excess conductive paste attached to the surfaces of the photoresist films 13 and 14, the conductive paste 3 is cured and the photoresist films 13 and 14 are peeled off to form a conductive paste as shown in FIG. 7c. The electrode 5 of the semiconductor element 1 and the electrode conductor 4 of the external circuit board 2 are connected using the adhesive paste 3.
以上説明したように、本発明は、半導体素子と
外部回路基板の電極の接続部上に、フオトレジス
ト膜による窓部を形成し、その窓部に導電性ペー
ストを形成することにより、従来のような中間の
ブリツジ状リードを廃した半導体素子の接続方法
であり、導電性ペーストによる接続であるため、
従来接続方法でみられたブリツジ状リードの機械
的強度不足から生ずる破断や短絡などの接続不良
がなくなり、信頼性の高い接続が得られる。生産
性については、個数に関係なく一度の処理で接続
できるので、１素子の場合と複数個の場合とで接
続に費やす時間に大きな差はなく、量産によるメ
リツトが出やすい。又、熱圧着接続に比べ、導電
性ペースト硬化温度は150℃〜180℃程度であり、
熱による素子への影響が少なくなる。さらに、従
来の接続方法では限界とみられていた10本／mm程
度の微細電極接続も、本発明によれば、フオトレ
ジスト膜に窓部を形成しての接続であるので比較
的容易であり、より高密度な電極の接続も実施す
る事が出来る。 As explained above, the present invention forms a window section using a photoresist film on the connecting part between a semiconductor element and an electrode of an external circuit board, and forms a conductive paste on the window section, thereby making it possible to use the conventional method. This is a method of connecting semiconductor devices that eliminates the need for intermediate bridge-like leads, and since the connection is made using conductive paste,
Connection failures such as breakage and short circuits caused by insufficient mechanical strength of bridge-shaped leads, which were observed in conventional connection methods, are eliminated, and a highly reliable connection can be obtained. In terms of productivity, since connections can be made in one process regardless of the number of devices, there is no big difference in the time required for connection between one device and multiple devices, making it easier to benefit from mass production. In addition, compared to thermocompression bonding, the conductive paste curing temperature is about 150℃ to 180℃,
The effect of heat on the element is reduced. Furthermore, according to the present invention, it is relatively easy to connect fine electrodes of about 10 electrodes/mm, which was considered to be the limit with conventional connection methods, because the connections are made by forming windows in the photoresist film. It is also possible to connect electrodes with higher density.
第１図〜第３図は従来の半導体素子の接続方法
を示す斜視図、第４図および第５図は従来の半導
体素子の接続方法の欠点を説明するための図、第
６図ａ〜ｃは本発明の半導体素子の接続方法の一
実施例を示す工程図、第７図ａ〜ｃは本発明の半
導体素子の接続方法の他の実施例を示す工程図で
ある。
１…半導体素子、２…外部回路基板、３…導電
ペースト、４…電極導体、５…電極、６…ベー
ス、７，７′７″…中間ブリツジ状リード部、８…
耐熱性フイルム、９…接着剤、１０…発光部、１
１…フオトレジスト膜、１２，１２′，１２″…窓
部、１３，１４…フオトレジスト膜。
1 to 3 are perspective views showing a conventional method for connecting semiconductor elements, FIGS. 4 and 5 are diagrams for explaining the drawbacks of the conventional method for connecting semiconductor elements, and FIGS. 6 a to c 7A to 7C are process diagrams showing one embodiment of the method for connecting semiconductor elements according to the present invention, and FIGS. 7A to 7C are process diagrams showing other embodiments of the method for connecting semiconductor elements according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... External circuit board, 3... Conductive paste, 4... Electrode conductor, 5... Electrode, 6... Base, 7,7'7''... Intermediate bridge-shaped lead part, 8...
Heat-resistant film, 9...Adhesive, 10...Light emitting part, 1
1... Photoresist film, 12, 12', 12''... Window portion, 13, 14... Photoresist film.
Claims (1)
と、表面に複数の電極導体を有する外部回路基板
の端面とを、対応する前記電極および前記電極導
体の位置を合わせて密着し、その後前記半導体素
子表面および前記外部回路基板表面にフオトレジ
スト膜を形成し、その後前記電極および前記電極
導体の接続部上のフオトレジスト膜に窓部を形成
し、その後前記窓部に導電性ペーストを形成する
ことを特徴とする半導体素子の接続方法。 ２ 電極の端部に一端開口の窓部を有するように
フオトレジスト膜が表面に形成された半導体素子
と、前記電極と対応する電極導体の端部に一端開
口の窓部を有するようにフオトレジスト膜が表面
に形成された外部回路基板とを、それぞれの前記
窓部の開口を対向させて密着し、その後導電性ペ
ーストを前記半導体素子の窓部と前記外部回路基
板の窓部に形成することを特徴とする半導体素子
の接続方法。[Claims] 1. An end face of a semiconductor element having a plurality of electrodes on its surface and an end face of an external circuit board having a plurality of electrode conductors on its surface are brought into close contact by aligning the positions of the corresponding electrodes and the electrode conductors. After that, a photoresist film is formed on the surface of the semiconductor element and the surface of the external circuit board, and then a window is formed in the photoresist film on the connection portion of the electrode and the electrode conductor, and then a conductive film is formed on the window. A method for connecting semiconductor elements, the method comprising forming a paste. 2. A semiconductor element having a photoresist film formed on its surface so as to have a window with one end open at the end of the electrode, and a photoresist film having a window with one end open at the end of the electrode conductor corresponding to the electrode. An external circuit board having a film formed on its surface is brought into close contact with the openings of the respective windows facing each other, and then a conductive paste is formed on the window of the semiconductor element and the window of the external circuit board. A method for connecting semiconductor elements, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212872A JPS58116744A (en) | 1981-12-29 | 1981-12-29 | Connecting method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56212872A JPS58116744A (en) | 1981-12-29 | 1981-12-29 | Connecting method for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116744A JPS58116744A (en) | 1983-07-12 |
| JPS6347262B2 true JPS6347262B2 (en) | 1988-09-21 |
Family
ID=16629666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56212872A Granted JPS58116744A (en) | 1981-12-29 | 1981-12-29 | Connecting method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58116744A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07244006A (en) * | 1994-03-01 | 1995-09-19 | Tiger Mach Seisakusho:Kk | Moisture regulating-electrode device for rotary drum type concrete mixer |
-
1981
- 1981-12-29 JP JP56212872A patent/JPS58116744A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07244006A (en) * | 1994-03-01 | 1995-09-19 | Tiger Mach Seisakusho:Kk | Moisture regulating-electrode device for rotary drum type concrete mixer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58116744A (en) | 1983-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5519936A (en) | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US5773884A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US5633533A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| JPH0357618B2 (en) | ||
| JPH06302653A (en) | Semiconductor device | |
| JPS6347262B2 (en) | ||
| JP3508478B2 (en) | Method for manufacturing semiconductor device | |
| JPH11176849A (en) | Manufacture of semiconductor device | |
| JPS62260343A (en) | Semiconductor device | |
| WO2017066896A1 (en) | Electrical connection structure between the front and rear of a chip, and manufacturing method therefor | |
| JP3896333B2 (en) | Thick film multilayer wiring board | |
| JP3021508B2 (en) | Method of forming conductive protrusions | |
| JPS5969937A (en) | Connecting method for semiconductor element | |
| JPH0131690B2 (en) | ||
| JPS6029228B2 (en) | Tape for connecting semiconductor devices | |
| JPH021961A (en) | Manufacture of semiconductor device | |
| JPH05102223A (en) | Manufacture of semiconductor device | |
| JP2774180B2 (en) | Mounting board | |
| JP3854206B2 (en) | Semiconductor device | |
| JPH01313948A (en) | Thin film circuit board and manufacture thereof | |
| JPS6331127A (en) | Insulating substrate for semiconductor device | |
| JPH07263487A (en) | Manufacture of semiconductor device | |
| JPS6349454A (en) | Thermal head | |
| JPS5969938A (en) | Connecting method for semiconductor element | |
| JP2002134646A (en) | Manufacturing method of wiring board |