JPS6346847B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to clock synchronization schemes between devices operating at different cycle times. Technical background The operating clock frequencies of computer components, such as the CPU and channels, may differ, and even if the difference is an integer multiple,
If it is a non-integral multiple, there will be a problem with signal transmission and reception at the interface. Prior Art and Problems To explain this with a diagram, in FIG. 1, A and B are one and the other devices operating at different cycle times, and ITF is an interface provided in one device A. L1 to L10 are clocked with latches.
CLK, it takes in the transmitted and received data, temporarily stores it, and then sends it out. The clock of device A is CLKA, the clock of device B is CLKB, and the clock of the interface section is CLKI. When clocks A and B are integer multiples, for example, the period of clock A is 20nS, and the period of clock B is 60nS.
In this case, the period of clock I in the interface section should be set to the period of clock B of 60 ns, and when data is transmitted from device B to A as shown in Fig. 2, the period between B and I is 60 ns, and the period between I and A is 60 ns. 20nS between
Data is successively captured and transmitted to each latch with a time delay of . Furthermore, when data is transmitted from device A to device B, the data is latched and transmitted with a time delay of 20 to 60 nS as shown by the dotted line. On the other hand, the clock period of device A is 20 nS, the clock period of device B is 70 nS, that is, the ratio of the two is a non-integer of 70/20, and the period of the interface clock is the same as that of clock B. As shown in , in the data transfer between B and A, the data transfer between I and A is
It becomes 10nS. Similarly, when data is transferred from A to B, there is a portion where the time is only 10 nS, as shown by the dotted line.
The hardware of device A, which uses a clock with a period of 20 ns, is designed using logic circuit elements suitable for operation at 20 ns, and if it has to operate in half that time, it will be difficult to design logic or implementation design. This is a serious problem because it increases constraints and may not be possible. OBJECTS OF THE INVENTION The present invention aims to prevent the occurrence of abnormally short cycles by modifying the clock frequency of the interface section, thereby making it easier to implement the circuit. Structure of the Invention The present invention provides an apparatus A that operates at a cycle time _T1 .
and cycle time nT ₁ /2 (here n is 3, 5,
In the clock synchronization method with device B operating at 7, 9, etc., the cycle time of the interface between device A and device B is calculated as (n-1)T ₁ /2 and ( n+1) T ₁ /2, which will now be described in detail with reference to embodiments shown in the drawings. Embodiment of the invention FIG. 4 shows an embodiment of the invention. In this example, the period of clocks CLKA and B of devices A and B is 20 nS,
70nS, whereas the interface ITF
Switch the clock period between 60nS and 80nS alternately.
In this way, data transmission between devices B and A will be
60nS (or 70nS) and 20nS, and also devices A and B
Data transmission between 20nS (or 40, 60, 80nS)
Performed in 80nS (or 70nS), minimum 20nS
Yes, and does not require particularly high-speed operation. The clock in the interface section is not much different from the longer clock cycle, and in two cycles it coincides with the long cycle clock, and in the first cycle after the coincidence, it arrives earlier than the long cycle clock and at the same time as the short cycle clock. selected to do so. In other words, every other clock in the interface section is 1/2 of the short-cycle clock.
Shift the period before or after the long period clock. This relationship is as follows: T ₁ is the shorter clock period, T ₂ is the longer clock period, and T ₂ = nT ₁ /2 (n is 3, 5, 7, etc.), and the clock period of the interface section is T ₃ is (n-1) T ₁ /2 and (n+1)
This is satisfied by alternating T ₁ /2.
If the clock of the interface section is configured in this manner, it will be out of synchronization with the long-period side clock every other period, but this deviation is relatively small at 0.5/3.5 of the period of clock B, making it easy to implement the circuit. There can be various cycle times for devices A and B, but the important thing is whether the operation is fast or slow, so at the design stage, we do not choose a cycle time ratio that will result in a fraction of many digits, but rather keep it as simple as possible. It should be something that is comparable. In the method of the present invention, T ₁ = 20 nS and n =
3, 5, 7,... then T ₂ = 30, 50, 70,... T ₃ is 20
and 40, 40 and 60, 60 and 80, etc., and by combining this with integer multiples that require simple processing, it is possible to correspond to a considerable cycle time ratio. Next, FIGS. 2, 3, and 4 collectively show the relationship between the clock period and the allowable delay between latches as cases 1, 2, and 3.

【table】

[Table] Figure 5 shows a circuit that generates clocks B and I with a longer cycle than clock A with a short cycle. In this figure, the dotted line frame 10 is a multiplier circuit that receives clock A and doubles the frequency, which is 1/2 the period, 10nS clock 2.
This is a circuit for making A, and a specific example is shown in FIG. In FIG. 6, 12 is a delay circuit consisting of three inverters and a delay line connected in series, and creates a delay clock DCLKA of clock A which is inverted by the first stage inverter. 12 is a NOR gate (called chopper CPR) that connects the inverted output of the first stage inverter - CLKA and the delay clock.
Take the NOR with DCLKA and reduce the pulse width. This is not necessarily a necessary process. 13
is a delay circuit consisting of four inverters and a delay line in series, giving a delay of 10nS. 14 is an OR gate that takes the OR between the chopper CPR output clock CCLKA with a period of 20 nS and the clock delayed by 10 nS.
Outputs clock CLK2A with a period of 10 ns. 8th
The figure shows the relationship of the clocks in each part. Returning to Figure 5 again, 20 is the double frequency clock.
The count value is 0 in the hexadecimal counter that counts CLK2A,
1, 2...6 produces an output on the line or terminal C0, C1...C6. 21 is an OR gate that receives the C0 output and C6 output, 22 is set by the C0 output,
Flip-flop reset by C2 output, 2
3 is an inverter, and 24 is a NOR gate. 7th
The figure shows the time chart of this circuit. That is, the input clock of this circuit is CLKA with a period of 20 nS, and the multiplier circuit 10 generates a double frequency clock CLK2A. The counter 20 counts this and sequentially produces outputs C0, C1, . . . C6, C0, C1 . OR gate 21 produces an inverted output -EBLT running from output C6 to C0, and NOR gate 24 produces clock A
The inverted clock -CLKA by the inverter 23 is passed only while -EBLI is generated, so that the period of the clock CLKI output from the NOR gate 24 is alternately 60 nS and 80 nS as shown in FIG.
Since the flip-flop 22 is set and reset at C0 and C2 in synchronization with the clock 2A, its output becomes the clock CLKB having a pulse width of 20 ns and a period of 70 ns. In this way, clock A of device A with a period of 20 ns
The clock CLKI of the interface section has a period of 60/80 ns and the clock CLKB of device B has a period of 70 ns.
is made. By making the clock phases different on the sending and receiving sides of the interface section, the signal propagation time between device B and interface ITF is
It can be operated even when the cycle time is longer than the cycle time of . Figure 9 is an example of this, where the clock on the sending side of the interface ITF is IO, the clock on the receiving side is II,
These clocks are connected together as shown in Figure 11.
They have a period of 60nS and 80nS, but the phases are different.
Even when compared with Figure 4, the clock IO advances by 20nS,
Clock II has a 20nS delay. In this way, it takes 90nS or 100nS for transmission from interface ITF to device B, and 80nS or 100nS for transmission from device B to interface ITF.
It can take 90nS. A circuit for creating such a clock is shown in FIG. In FIG. 10, the same parts as in FIG.
C1 and C of the counter 20 at the OR gate that outputs
2. Receives C4 and C5 outputs. These enable outputs EBLI, O are as shown in FIG. 11, and now clock A is gated and clocks II, IO are as shown in FIG. The counter 20 can be configured with a register or the like, and the first
Examples are shown in FIG. 2 and FIG. 13. 3 in Figure 12
1 and 32 are registers, 33 is a comparator, 34 is a selector, 35 is a decoder, and 36 is a +1 circuit.
To make this circuit an n-ary counter, n-1 is set in the register 32, and the register 31 is set to 0. Comparator 33 therefore produces a mismatch output, and selector 34 passes output 1 of +1 circuit 36, which is set in register 31. In the next cycle, n-1 of the register 32 (here n=7) is compared with 1 of the register 31, the comparator 33 again produces a mismatch output, and the selector 34 passes the 1+1=2 of the +1 circuit 36. , which is set in register 31. Similarly, the contents of the register 31 will eventually become 6, the comparator 33 will produce a matching output, and in response, the selector 34 will pass 0 to the register 31.
Return to 0. Repeat this and register 31
The content of is 0, 1, 2...6, 0, 1, 2...repeat. The decoder 35 decodes this and the output terminal C
0, C1...C6 produce sequential outputs. The method shown in FIG. 10 can be generalized and expressed as follows. That is, from clock A with cycle time t1 to clock 2 with cycle time t2 = t1/2.
A is made and device A is operated by clock A. In addition, a counter 20 that repeatedly counts from 0 to n-1 is provided, and this is operated by the clock 2A so that the value of the counter is k (here, k is either 0, 1...n-1, and the 10th In the figure, when the clock is 0), clock B is sent to device B, and the counter value is l (here, l
is one of 0, 1,...n-1, and in Fig. 10, it is 4) and the next value l+1, and when clock A is input, the clock IO for sending to device B is sent to the interface part, and the counter is The value m (here m is 0, 1...n-1, 1 in Figure 10) and the next value m
+1 and when clock A is input, the receiving clock II from device B is sent to the interface section. The values of k, l, m, and n can be changed, and clock A may be made from clock 2A. FIG. 13 shows an example in which a counter-down method is used, and the (n-1) register 32 is set to n-1, which is 6 in this example. The initial contents of the register 31 may or may not be 0, but if it is 0, the 0 detection circuit 38 operates and causes the selector 34 to output the contents of the register 32. This is loaded into register 31, so the contents of the register are n
-1 In this example, it becomes 6. Therefore, the 0 detection circuit 38 does not operate, and the selector 34 passes the output of the -1 circuit 37. Therefore, the contents of the register 31 change every cycle by 6, 5, 4...0, 6, 5..., and the decoder 35 sequentially produces an output at one of the output terminals C0, C1...C6. FIG. 14 shows an example of making the generation timing of the enable signal variable. 41 is a group of OR gates that receive two outputs C0 to C6 from the counter 20 or decoder 35; 21 in FIG. 5 and 2 in FIG. 10;
It corresponds to 5,26. Therefore, the OR gate group 41 at the top of the diagram generates an enable signal between the outputs C0 and C1, and the second stage generates an enable signal between the outputs C1 and C2, which are selected by the NOR gate 42. NOR gate 42 receives the output of register 43 at one input terminal, and only one is selected. That is, register 4
3 has the same number of bits as Noah gate 42, and 1
Data is input in which only one is 0 and the rest are 1, so only one of the outputs SEL01 to SEL60 is 0 and the others are 1, and that 0 opens one of the gates 42. 44 is the or gate. FIG. 15 shows an example of a circuit in which the generation timings of the set clock SC and reset clock of the flip-flop 22 of FIG. 5 are made variable. 49,
Reference numeral 50 denotes a register, which is of the same type as the register 43 in FIG. In other words, only one register 49 is 0.
and others are loaded with data that is 1, producing outputs SELS0-SELS7 which open one of the NOR gates 45. The register 50 is similar, but the position of 0 is shifted by the pulse width W compared to that of the register 49. The output of this register 50 SELR0~
SELR 7 opens only one NOR gate 47 and generates the reset clock RC of flip-flop 22 through OR gate 48. The set clock SC generates an OR gate 46. FIG. 16 shows a circuit that uses a hexadecimal counter to generate clocks B, II, and IO. In FIGS. 5 and 10, a hexadecimal counter is used and the output of the hexadecimal counter is ANDed with clock A to create the interface clock CLKI. However, in this example, a hexadecimal counter 51 is used and the OR gates 25 and 26 are used. A gate open signal is issued twice in each cycle and ANDed with the double frequency clock 2A to obtain the interface section clocks II and IO. A time chart for explaining the operation is shown in FIG. In this case, the output of the counter 51 may be selected in accordance with the change ratio of the interface section clock cycle which changes alternately. For example, in this example, CLKI is 60nS and 80nS, that is, 3 to 4, so
It is sufficient to input the third counter output C2 and the sixth counter output C8 to the OR gate 25.
CLKII is obtained. CLKIO is an output shifted from the counter output C2 according to the desired phase difference. In this example, C4 (therefore, the desired phase difference is 20 nS) and the eighth output C12 can be input to the OR gate 26. Output of the gate and CLK2
Noah with A gives CLKIO. CLKB is also generated by using the output of the counter 51 to set and reset the flip-flop 22 twice in each cycle. 52 and 53 are OR gates for that purpose. The method shown in FIG. 16 can be generalized and expressed as follows. That is, clock A with cycle time t1
A clock 2A with a cycle time t2 = t1/2 is created from , device A is operated with clock A, and a counter 51 that repeats from 0 to 2n-1 is provided, and this counter is operated with clock 2A, and the value of the counter is When k (here, it is one of 0, 1,...n-1, 0 in Figure 16) and k+n (7 in Figure 16), clock B is sent to device B, and the counter value is l. (Here, l is 0, 2, 4...n-1
In Fig. 16, either 4) or l+n
When clock 2A occurs at +1 (12 in Figure 16) or l+n-1, the clock IO for sending to device B is sent to the interface section, and the counter value is m (here, m is 0, 2, 4). ...When clock 2A occurs at either n-1 (2 in FIG. 16) and m+n-1 (8 in FIG. 16) or m+n+1, the receiving clock II from device B is sent to the interface section. do. These k, l,
m and n can be changed, and clock A may be made from clock 2A. FIG. 18 shows a clock generation circuit. In the examples up to the previous figure, clock A was used as a base, and clock B, etc. were created from this, but in this circuit, clock 2A is used as the basic clock, and clock A, and although not shown, clock B and clock I are created from this. 5
4 is a flip-flop, and in this example, the period T ₁ is
It takes in its own output which has been inverted by the inverter 54 using the 10nS clock CLK2. As a result, the output of the flip-flop 54 is CLK1 with a period _T2 which is twice _the period T1 of the clock CLK2, as shown in FIG.
becomes. CLK1 is the aforementioned clock A, and CLK2
corresponds to clock 2A. This circuit is of course CLK
2 can also operate with a period other than 10 nS, and the output CLK1 is 1/2 the frequency. Effects of the Invention As explained above, according to the present invention, clock synchronization can be achieved between devices having cycle times that are not integer ratios. Clock ratio is 1.5, 2.5, 3.5...
However, the circuit configuration for synchronization becomes simpler, and the ratio of each cycle time of the CPU and channel can be freed from the restriction of an integer ratio, greatly increasing the degree of freedom in design.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of data transmission between two devices, FIGS. 2 and 3 are waveform diagrams for explaining the conventional method, and FIG. 4 is a waveform diagram for explaining the method of the present invention.
FIG. 5 is a block diagram of a circuit that implements the method shown in FIG. 4, and FIG. 6 is a circuit diagram showing details of a part of FIG. 5.
7 and 8 are waveform diagrams for explaining the operation, FIG. 9 is a block diagram of a different embodiment of the present invention, FIG. 10 is a circuit diagram realizing the method shown in FIG. 9, and FIG. 11 is an explanation of the operation. 12 and 13 are circuit diagrams showing other examples of the counter, FIG. 14 is an enable signal generation circuit with variable timing, and FIG. 15 is a flip-flop set and reset signal with variable timing. FIG. 16 is a circuit diagram showing an example of a clock generator, FIG. 16 is a circuit diagram showing an example in which a counter with double capacity is used, FIG. 17 is an explanatory diagram of its operation, and FIG. FIG. 2 is a circuit diagram and a waveform diagram showing an example of FIG. In the drawing, rectangular frame A is device A, rectangular frame B is device B,
ITF is the interface, CLKA, B is equipment A, B
The clocks CLKI, CLKIO, and CLKII are the interface clocks, transmitting clock, and receiving clock.

Claims (1)

[Claims] 1. Device A operates at cycle time T ₁ and cycle time nT ₁ /2 (where n is 3, 5, 7, 9).
In the clock synchronization method with device B operating in _any one of the A clock synchronization method characterized by alternating between ₁ and 2. 2. An interface part is placed in device A, and the clock of the interface part has the same frequency but different phases for transmission to device B and for reception from device B. Clock synchronization method described in scope 1.