JPS6346618B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for transmitting information signals, such as synchronization signals or control signals, during which the encoding section and the decoding section of a PCM terminal device are assigned to transmit and receive information signals to and from a relay transmission path outside of the transmission time. This invention relates to a continuous monitoring method for PCM terminal equipment that monitors these asynchronous encoders and decoders in the time slot.

Conventionally, the monitoring method of this type of PCM terminal station is to return the decoded output sample corresponding to the monitoring digital signal input to the encoder once, and the digital signal obtained at the output of the encoder is predetermined. The device is configured to generate an alarm when the digital value (reference value) exceeds the specified value. In this method, since the encoder and decoder generally operate in different bit synchronization systems or frame synchronization systems, the generated alarm is not caused by an abnormality in the encoder or decoder being monitored. Or bit synchronization system,
Or, it cannot be determined whether this is due to a difference in the phase or frequency of the frame synchronization system. In order to eliminate these inconveniences, the amount of frequency or phase difference of each bit synchronization system or frame synchronization system must be constantly measured in advance.
There was a flaw in the system in that it was necessary to adjust the time for sending the test signal or the time for sending the test signal from the decoder to the encoder.

An object of the present invention is to solve the above-mentioned problems, and to provide a simplified configuration that eliminates the need to adjust the timing of transmitting a test signal according to changes in the period and phase difference between the transmitted pulse and the received pulse, as in the conventional method. Economical PCM
The purpose of the present invention is to provide a continuous monitoring method for terminal equipment.

According to the present invention, the encoding section and the decoding section of the PCM terminal device can use the time slot of the synchronization signal or the control signal assigned to transmit/receive to/from the relay transmission path, the sampling period of the encoding section. A monitoring digital signal whose polarity is alternately inverted with at least twice the period is applied to the decoding section, and after the output of the decoding section is expanded, sampled and held, a synchronization signal and a control signal from the encoding section are sent. A plurality of output samples obtained by gate control using a transmission control pulse generated in accordance with the transmission time of the encoder are returned to the encoder, and the output samples reproduced by the encoder are compared with the predetermined output samples. A continuous monitoring system for a PCM terminal device is obtained, characterized in that the encoder and decoder are monitored using at least three consecutive reproduced output samples by comparing the reference value with a reference value.

First, in order to facilitate comparison with the present invention, a conventional PCM terminal station monitoring system will be explained with reference to the block diagram in Fig. 1, the time chart in Fig. 2, and the frame configuration diagram in Fig. 5. do. In the conventional example shown in Fig. 1, the amount of phase difference between the encoding section and the decoding section is constantly measured, and as a result, a time-adjusted digital test signal is sent from the decoding section to the encoding section in sequence. The test signal obtained from the encoder is compared with a predetermined value (reference value) and monitored.

The PCM terminal device to which the present invention is applied performs transmission and reception using the frame structure shown in FIG. 5a. One frame has time slots TS0 to TS31, and one time slot is composed of 8 bits. Time slot TS0 indicates the time slot for the frame synchronization signal, and time slot TS1
6 indicates a time slot for exchange control signals. Also, time slots TS1 to TS15 and TS17
~TS31 is a time slot for audio information.
Here, as shown in FIG. 5b, the above-mentioned frame structure is represented by signal times (time slots) tr ₁ , tr ₃ , ... for the portion corresponding to time slot TS0, and for the portion corresponding to time slot TS16. The signal time (time slot) is indicated by tr ₂ , tr ₄ ....

Here, with reference to Figures 1 and 2, receive
PCM signal A was received through the relay transmission line
The signal is a PCM signal, and has signal times tr ₁ , tr ₂ , tr ₃ . . . as shown in waveform A in FIG. 2a.
As mentioned above, the signal times tr ₁ , tr ₃ , tr ₅ , tr ₇ ,...
is the frame synchronization signal transmission time, and the signal times tr ₂ , tr ₄ , tr ₆ . . . existing in the middle represent, for example, the control signal transmission time from the exchange. It is assumed that multiplexed PCM signals such as audio are included in the locations indicated by the airspace before and after the test signal generation circuit 4 (omitted in FIG. 2).
In the example shown in Fig. 2a, the digital test signal (monitoring digital signal) T outputted from the test signal T has its polarity alternately inverted at the same period as the frame synchronization signal, and each signal has a period of time equal to the frame synchronization signal. It is an 8-bit wide code string. Note that among these 8 bits, the most significant bit indicates polarity.

Now, the synchronization signals tr ₁ , tr ₃ ,
The digital test signal T from the test signal generation circuit 4 is applied to the OR circuit 9 during the signal times tr ₅ , . . . . The output from the OR circuit 9 is applied to the decoding section 2 and converted into an analog signal PAM-R. The converted analog signal PAM-R is led to the sample-and-hold circuit 5, and is converted into a second signal by a signal from the test signal generation circuit 4, which is added separately.
As shown in Figure a, it is held only for analog test signals and outputs a hold signal H. On the other hand, the transmission control pulse C _t having the same period as the frame synchronization signal of the transmission PCM signal B having the same configuration as the reception PCM signal A is transmitted to the gate circuit 6 by ts ₁ , ts ₂ , ts ₃ , . This controls the gate circuit 6 which receives the hold signal H from the sample-and-hold circuit 5, that is, the hold signal H is sampled to extract the gate output indicated by the signal D. . And this signal D is transmitted PAM
It is added to the encoder 1 together with the signal. Among the output signals encoded by the encoder 1, a test signal digitally converted from the input signal D is output.
selected from the PCM signal B and compared with a predetermined digital value (reference value) in the comparator circuit 7,
When the reference value is exceeded, the alarm circuit 8 is driven to generate an alarm.

However, in general, the received PCM signal and the transmitted PCM signal have different periodic phases, so
The relationship shown in FIG. 2a is not always the same; for example, the relationship between the received PCM signal A tr ₁ and the transmission control pulse C _t
When ts ₁ of The decryption unit cannot be monitored. For this purpose, the phases of the transmission control pulse C _t and the reception control pulse C _r are compared in advance by the phase comparator circuit 3, and if tr ₁ and ts ₁ become close to each other, the time chart shown in Fig. 2b As shown, the signal generation time of the digital test signal T generated from the test signal generation circuit 4 is changed from the signal time of the frame synchronization signal tr ₁ , tr ₃ , tr ₅ , . . . to the signal time of the control signal tr ₂ , tr ₄ , etc. tr ₆ , . . . and at the same time, the sampling time in the sample-and-hold circuit 5 is also changed. Such a signal control adjustment procedure is followed by signal tr ₂ and
If ts ₂ approaches again, the same procedure must be repeated.

Next, a continuous monitoring system for a PCM terminal station according to the present invention will be explained with reference to the block diagram of FIG. 3 showing the configuration of the embodiment and the time chart of FIG. 4 showing the operating waveforms of the main parts. Note that the frame configuration in this case is the same as that shown in FIG.

The digital test signal (monitoring digital signal) T' from the test signal generation circuit 11 is synchronized with one of the signal transmission times (time slots) of the frame synchronization signals tr ₁ , tr ₃ , tr ₅ , . . . of the received PCM signal. Moreover, it occurs at a period that is a predetermined times the time slot of the frame synchronization signal. That is, in the case of Fig. 4 a and b,
A digital test signal T' is generated at twice the period of the time slot of the frame synchronization signal, is combined with the received PCM signal A via an OR circuit 12, and is sent to the decoder 2.
After being converted into an analog test signal PAM-R' by the expansion sample and hold circuit 13, the analog test signal PAM-R' is held as shown by waveform H'. This hold signal H′ is
The gate circuit 14 is made conductive by the transmission control pulse C _t ' generated in accordance with the frame synchronization signal of the PCM signal and the control signal transmission time, and the hold signal is
H' is sampled to extract the gate output D' shown in FIGS. 4a and 4b. This gate output D′ is transmitted
It is multiplexed with the PAM signal and digitally converted in the encoding section 1. Among the digitized output signals, the above-mentioned digital trial signal is selected from the output PCM signal and compared with a predetermined reference value by the comparator circuit 15, and if it exceeds this reference value, alarm information is issued. The signal is sent to the alarm circuit 16, and the alarm circuit generates an alarm.

FIGS. 4a and 4b are time charts showing cases in which the phase difference between the transmission control pulse C _t ' and the reception control pulse C _r ' is different. In these time charts, tr ₁ , tr 2 , tr ₂ ,
tr ₃ , tr ₄ ... indicate the time (time slot) allocated to the frame synchronization signal on the receiving side and the exchange control signal in between, and ts ₁ , ts _{2 ,} ts 2 of the transmission control pulse C _t ' ts ₃ , ts ₄ . . . respectively indicate times allocated corresponding to a frame synchronization signal and a control signal (both not shown) on the transmitting side. Now, let tr ₁ , tr ₃ , tr ₅ , ... be the time of frame synchronization signal reception, and the absolute value is the same at the time of every other frame synchronization signal, that is, at twice the cycle of the frame synchronization signal. If a digital test signal T' whose polarity is alternately inverted is generated, the analog test signal PAM-R' shown in FIG. has the waveform shown in FIG. 4a. In this waveform diagram (Fig. 4a), the output waveform of the sample-and-hold circuit 13 is sufficiently stable with respect to the transmission control pulse C _t ' during the time when the gate circuit 14 is made conductive; The output signal D' of 13 is an analog PAM that corresponds exactly to the digital test signal.
It becomes a signal. However, in this case, although the test signal generation interval and the sampling interval in the gate circuit 14 are in a ratio of 1:4, no problem occurs because the test signal does not include any error. On the other hand, Fig. 4b
, the output waveform H' of the sample-and-hold circuit 13 is not stable enough with respect to the transmission control pulse C _t ' to make the gate circuit 14 conductive, and the output signal of the gate circuit 14 is
D' includes an error in one sampled signal out of four consecutively sampled signals.
Therefore, even if encoder 1 and decoder 2 are operating normally, the comparator circuit will send alarm information to the alarm circuit by mistake, but the gated signal by the remaining three samplings will be detected correctly. be done.
Therefore, if three of the four consecutive sampling signals in the comparison circuit 15 are normal and do not exceed the reference value, the signal is determined to be normal. That is, a majority decision is made. This allows normal monitoring.

Furthermore, if an abnormality occurs in the operation of the encoder 1 and the decoder 2, in the case of the phase relationship shown in FIG. In order to obtain the test signal shown in FIG.
An alarm is sent to the alarm circuit 16. Note that the digital test signal described above may be generated in synchronization with any of the time slots of the control signals tr ₂ , tr ₄ , tr ₆ .

As can be seen from the description of the above embodiment, the hold signal is sampled four times or more while the digital test signal is sent to the decoding section once, and the test signal is sent as a gate output to the encoding section. When monitoring the test signal digitized by the encoder, the possibility that the hold signal will be sampled at the change point of the test signal is at most 1 out of 4 times due to the frequency and phase difference of the transmitted and received PCM signals, and the remaining A test signal that has been sampled three or more times does not include errors at changing points and can be successfully demodulated. On the other hand, if a failure occurs in the encoding section or the decoding section, and the test signal is sampled at the change point of the test signal, the error signal component will be superimposed, and the comparison circuit will mistakenly judge the monitored section as normal. The possibility is at most 1 out of 4.
The remaining three or more times can be determined to be abnormal. That is, in the time slot of the frame synchronization signal or control signal, the monitoring digital signal may be sent out at a cycle that is at least twice as long as the sampling cycle of the encoder.

As is clear from the above description, according to the present invention, the digital test signal is transmitted at a predetermined point in time regardless of changes in the period or phase difference between the synchronization transmission pulse and reception pulse of the PCM signal. The monitoring function can be simplified, such as by eliminating the phase comparator circuit that was required in the past, since all you have to do is send out the signal.
It has great effects not only in terms of performance but also in terms of economy.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional PCM terminal station monitoring system, and Fig. 2 a and b show operations when the phase difference between the transmission control pulse and the reception control pulse is different in the conventional example shown in Fig. 1. A time chart showing waveforms; FIG. 3 is a block diagram showing the configuration of an embodiment of the PCM terminal station continuous monitoring system according to the present invention;
4a and 4b are time charts showing operating waveforms when the phase difference between the transmission control pulse and the reception control pulse is different in the embodiment of FIG. 3;
FIGS. 5a and 5b are diagrams schematically showing the frame structure and frame structure of the PCM terminal equipment, respectively. 1 is an encoding section, 2 is a decoding section, 3 is a phase comparison circuit, 4 and 11 are test signal generation circuits, 5 is a single sample and hold circuit, 6 and 14 are gate circuits, 7
is a comparison circuit, 8 and 16 are alarm circuits, 9 and 12 are OR circuits, 13 is an expansion sample/hold circuit, 1
5 is a majority comparison circuit.

Claims (1)

[Claims] 1 In the monitoring method of the encoding unit and decoding unit of the PCM terminal device, the decoding unit receives
A monitoring digital signal whose polarity is alternately inverted with a cycle that is at least twice the interval between two successive decoder synchronization signals or two successive control signals in the PCM signal is used as the decoder synchronization signal or control signal. In addition to the decoding unit in synchronization with the signal, the output of the decoding unit is expanded, sampled and held, and then the communication control signal is generated in synchronization with the transmission time of the synchronization signal and control signal from the encoding unit. A plurality of output samples obtained by pulse gate control are added back to the encoding section, and the output samples reproduced by the encoding section are compared with a predetermined reference value, and at least three consecutive A continuous monitoring method for a PCM terminal device, characterized in that the encoder and decoder are monitored using the reproduced output sample.