JPS6346606B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device (CTD), such as a BBD.
Regarding the transversal filter using the present invention, good characteristics can be obtained especially when a band elimination filter is configured.

The BBD is generally configured as shown in FIG.
In the figure, an input terminal 1 is connected to the base of an npn type transistor 2, a collector of this transistor 2 is connected to a power supply terminal 4, and an emitter is grounded through a constant current source 3. This transistor 2
The emitter of the capacitor C ₀ is connected to one end of the capacitor C ₀ through the reverse diode 5.
It is connected to the clock terminal 6 through. Also, one end of the capacitor _C0 is connected to the emitter of an npn type transistor _Q1 , the collector of this transistor _Q1 is connected to the emitter of the next stage npn type transistor _Q2 , and so on _{. Qo}
(n is a positive integer) collectors and emitters are connected in sequence. A capacitor is connected between the collector and base of these transistors Q ₁ to _{Q o-1,} respectively.
C ₁ to _{C o-1} are connected. Note that the capacitor C ₁ −
The capacitance value of C _o-1 is all equal to the capacitor C ₀ and is assumed to be C. Furthermore, odd-numbered transistors Q ₁ , Q ₃ ...
The bases of the even-numbered transistors Q ₂ , Q ₄ . . . are connected to the drive circuit 8 through the clock terminal 6.

The clock terminals 6 and 7 each have a second
As shown in Figures A and B, clock signals φ ₁ and φ ₂ are supplied which have potentials of V _DC and V _DC +V _P , have a duty ratio of 50%, and have opposite polarities. Furthermore, the voltage
V _P is set to be V _CC >V _DC +2V _P with respect to the power supply voltage V _CC supplied to power supply terminal 4 .

Furthermore, the voltage of the input signal supplied to input terminal 1
V _S is in the range of V _DC +V _P ≦V _S ≦V _DC +2V _P.

In this device, in the initial state, the capacitor
All terminal voltages of C ₀ to _{C o-1} are charged to V _P . Furthermore, if the voltage V _S of the input signal is divided into a DC component V _SDC and an AC component V _SAC , in the initial state, the AC component
Only V _SAC is 0.

_{Therefore ,} in the initial state _, the hot ends of the even-numbered capacitors C ₀ , C _{2 .}
After rising to +2V _P , it becomes V _SDC , and the signal φ ₂
During the period of V _DC +V _P , it once drops to V _SDC -V _P and then becomes V _DC +V _P. Also the odd numbered capacitor
As shown in FIG _. 2D, the hot end _side of C ₁ , _{C 3 .}
After falling to V _P , it becomes V _DC +V _P , and the signal _φ2
During the period of V _DC +V _P , it once rises to V _DC +2V _P and then becomes V _SDC .

Then, during the period when the first signal φ ₁ is V _DC +V _P immediately after the input signal is supplied, if the voltage of the input signal at this time is V _S = V _S1 , the potential on the hot end side of the capacitor C ₀ is temporarily set to V _DC After rising to +2V _P , it becomes V _S1 . That is, the capacitor C ₀ is discharged and stores the charge of {V _S1 −(V _DC +V _P )}C. At this time, transistor _Q1 is off, so the capacitor
There is no change in C ₁ , C ₂ ....

Next, during the period when the following signal φ ₂ is V _DC +V _P ,
First, the potential of signal _φ1 becomes V _DC , so the capacitor
The potential on the hot end side of _C0 is V _S1 − (V _DC + V _P ) +
V _DC =V _S1 −V _P. Then, since the transistor Q ₁ is turned on, the potential on the hot end side of the capacitor C ₀ eventually rises to the base potential (V _DC +V _P ) of the transistor Q ₁ . At this time, transistor Q ₁ is operating in the active region, so charging of capacitor Co is as follows: terminal 7 → capacitor C ₁ → collector/emitter of transistor Q ₁ → capacitor C ₀
This is done through the following route. Then, the potential on the hot end side of capacitor C ₀ changes from V _S1 -V _P to V _DC +V _P , so the transfer of charge from the hot end side of capacitor C ₁ to the hot end side of capacitor C ₀ is as follows: {(V _DC +V _P ) − V _S1 )}C=(V _DC +2V _P −V _S1 )C. On the other hand, since the capacitor _C1 initially stored a charge of V _P・C, the final charge amount of the capacitor _C1 is V _P・C−(V _DC +2V _P −V _S1 )C={V _S1 −(V _DC +V
_P )}C. In other words, if the capacitor C ₀ was at V _S1 − (V _DC + V _P ) during the period when the signal φ ₁ was at V _DC + V _P ,
Signal φ ₂ moves to capacitor C ₁ during V _DC +V _P , and capacitor C ₀ returns to V _DC +V _P. Note that since capacitor Q ₂ is off, capacitors C ₂ , C ₃ ...
There is no change in .

Furthermore, in the period when the next signal φ ₁ is V _DC +V _P , if the input signal voltage is V _S = V _S2 , the capacitor Co is charged to V _S2 − (V _DC + V _P ), and the capacitor C ₁ is charged to V _DC +V _P and capacitor C ₂ is V _S1
-(V _DC +V _P ). Note that the transistor
Since Q ₃ is off, capacitor C ₃ and subsequent capacitors do not change.

The above operation is repeated, and the signal is moved from left to right in the drawing in synchronization with the signals φ ₁ and φ ₂ .

To configure a cyclic transversal filter using BBD in this way, proceed as follows.
For example, FIG. 3 shows a case where a filter circuit for trapping 4.5 MHz is configured in processing a composite color video signal.

In the figure, a first BBD (BBDa) consisting of seven transistors Q _a1 to _{Q a7} and a second BBD (BBDb) consisting of six transistors Q _b1 to Q _b6 are provided. This BBDa capacitor C _a3 , C _a5
are divided into C _a3 ′, C _a3 ″, C _a5 ′, and C _a5 ″, respectively, and these capacitance values are respectively a ₃ C,
(1-a ₃ )C, a ₅ C, (1-a ₅ )C. The cold end sides of one of these divided capacitors C _a3 ′ and C _a5 ′ are connected to each other, and the cold end sides of the other capacitor C _a3 ″ and C _a5 ″ are connected to the terminal 7 .

In addition, complementary transistor 11
The emitters of a and 12a are connected to each other, and this connection point is connected to the connection point of capacitors C _a3 ′ and C _a5 ′. Further, the bases of transistors 11a and 12a are connected to each other, and this contact is connected to an oscillator 38 through a terminal 37. In this oscillator 38, in the same phase as the signal φ ₂ , V _DC −V _BE and V _DC +V _P +V _BE
(where V _BE is the voltage between the base and emitter of the transistor), a signal φ ₂ ' is formed that takes the potential at terminal 3.
7. and pnp type transistor 1
The collector of transistor 2a is grounded, and the collector of npn transistor 11a is connected to current mirror circuit _M1a.
A PNP type transistor 13a on the input side that constitutes
The emitter of the transistor 13a is connected to the power supply terminal 4.

The bases of the output side pnp type transistors 14a, 14a' constituting the current mirror circuit _M1a are connected to the base of the transistor 13a, and the emitters of the transistors 14a, 14a' are connected to the power supply terminal 4.
connected to. and transistors 14a, 14
The collector of a′ is connected to the hot end side of capacitor C _a1 in the previous stage.

Further, the DC component V _SDC in the input signal is supplied through the terminal 21 to the base of the npn type transistor 22a. The emitter of this transistor 22a is grounded through a constant current source 23a, and the collector is connected to the power supply terminal 4. Furthermore, the transistor 22a
The emitter of is connected through the diode 24a in the opposite direction.
It is connected to the emitter of an npn type transistor 25a, its collector is connected to the power supply terminal 4, and its base is connected to the clock terminal 7. This diode 24a and transistor 2
A connection point 5a is connected to one end of a capacitor 26a. The capacitance value of this capacitor 26a is m _a C=(a ₃ +a ₅ )C. The other end of this capacitor 26a is connected to a connection point between the emitters of complementary transistors 15a and 16a. Further, the bases of transistors 15a and 16a are connected to each other, and this connection point is connected to an oscillator 38 through a terminal 36. This oscillator 38 generates a signal φ _{1 '} having potentials of V _DC −V _BE and V _DC +V _P +V _BE in the same phase as the signal φ 1 and is supplied to the terminal 36. and
The collector of the npn type transistor 15a is connected to the power supply terminal 4, and the collector of the pnp type transistor 16a is connected to the collector and base of the input side npn type transistor 17a constituting the current mirror circuit _M2a . The emitter is grounded. Furthermore, the current mirror circuit
Output side transistor 18a, 1 forming M _2a
The base of transistor 8a' is connected to the base of transistor 17a, the emitters of transistors 18a and 18a' are grounded, and the collectors are connected to the hot end side of capacitor C _a1 .

Furthermore, the capacitors C _a2 , C _a4 , and C _a6 of BBDa are divided into C _a2 ′, C _a2 ″, C _a4 ′, C _a4 ″, respectively.
C _a6 ′, C _a6 ″, and their capacitance values are a ₂ C, (1−a ₂ )C, a ₄ C, (1−a ₄ )C, respectively.
a ₆ C, (1-a ₆ )C. The cold ends of these capacitors C _a2 ″, C _a4 ″, and C _a6 ″ are connected to terminal 6.
connected to.

Further, circuits [transistors 11b to 18b] equivalent to the transistors 11a to 18a are provided, and the connection point of the bases of the transistors 11b and 12b is connected to the terminal 37, and the transistor 1
The connection point of the bases of 5b and 16b is connected to the terminal 36.

The cold ends of capacitors C _a2 ′, C _a4 ′, and C _a6 ′ are connected to the connection point of the emitters of transistors 15b and 16b.

Furthermore, the capacitors C _b2 and C _b4 of BBDb are divided into C _b2 ′, C _b2 ″, C _b4 ′, and C _b4 ″, respectively, and their capacitance values are respectively b ₂ C and (1−b ₂ ).
C, b ₄ C, (1-b ₄ )C. The cold end sides of these capacitors C _b2 ″ and C _b4 ″ are connected to the terminal 7, and the cold end sides of the capacitors C _b2 ′ and C _b4 ′ are connected to the connection point of the emitters of the transistors 11b and 12b.

In addition, a circuit equivalent to the transistor 22a to capacitor 26a [transistor 22b to capacitor 2
6b] is provided, and the base of the transistor 22b is connected to the terminal 21, and the transistor 25
The base of b is connected to terminal 7. Further, the capacitance value of the capacitor 26b is set as m _b C={1+(b ₂ +b ₄ )−(a ₂ +a ₄ +a ₅ )}C. The other end of this capacitor 26b is connected to a connection point between the emitters of transistors 15b and 16b.

And transistors _14b , 14b', 18b, 18 on the output side of current mirror circuits M 1b, M _2b
The connection point of the collector of b′ is connected to the hot end side of capacitor C _b0 .

Furthermore, the capacitors C _b1 , C _b3 , and C _b5 of BBDb are divided into C _b1 ′, C _b1 ″, C _b3 ′, C _b3 ″, respectively.
C _b5 ′, C _b5 ″, and their capacitance values are b ₁ C, (1−b ₁ )C, b ₃ C, (1−b ₃ )C, respectively.
b ₅ C, (1-b ₅ )C. The cold ends of these capacitors C _b1 ″, C _b3 ″, and C _b5 ″ are connected to terminal 6.
connected to.

Further, circuits [transistors 11c to 18c] equivalent to the transistors 11a to 18a are provided, and the connection point of the bases of the transistors 11c and 12c is connected to the terminal 37, and the transistor 1
The connection points of the bases of 5c and 16c are connected to the terminal 36.

The cold ends of the capacitors C _b1 ′, C _b3 ′, and C _b5 ′ are connected to the connection point of the emitters of the transistors 15c and 16c.

In addition, a circuit equivalent to the transistor 22a to capacitor 26a [transistor 22c to capacitor 2
6c], and the transistor 22c
The base of transistor 2 is connected to terminal 21, and
The base of 5c is connected to terminal 6. Further, the capacitance value of the capacitor 26c is m _c C={(b ₁ +b ₃ +b ₅ )−1}C. The other end of this capacitor 26c is connected to a connection point between the emitters of transistors 11c and 12c.

And transistors _14c , 14c', 18c, 18 on the output side of current mirror circuits M1C, _M2C
An output terminal 41 is led out from the connection point of the collector of c'.

In this circuit, when no input signal is supplied, the voltage at all terminals of the capacitor is V _P.

On the other hand, in the period when the signal φ ₁ is V _DC +V _P immediately after the input signal is supplied, if the voltage of the signal supplied during this period is V _S = V _S1 , then the capacitor
The terminal voltage of _C0 is changed from V _P to V _S1 − (V _DC + V _P ). Furthermore, after one clock period τ (= 1/f _c : f _c is the clock frequency), the terminal voltage of capacitor C ₂ changes from V P to V _S1 − (V _DC + V _{P )} during the period when signal φ ₁ is V _DC +V _P
changed to.

Then, during the period when the signal φ ₂ after 1.5τ is V _DC +V _P , the terminal voltages of capacitors C ₃ ′ and C ₃ ″ both change from V _P to V _S1 − (V _DC + V _P ), and during this period, the capacitor C ₃ ′ to a ₃ CV _P −a ₃ C {V _S1 − (V _DC +V _P )}=a ₃ C
The charge of {(V _DC +2V _P )−V _S1 } is transferred to transistor 11.
is discharged through the collector of a.

After another 2.5τ, the capacitor C ₅ ' is discharged during the period when the signal φ ₂ is V _DC +V _P , and the discharged charge at this time is
a ₅ CV _P −a ₅ C{V _S1 −(V _DC +V _P )}=a ₅ C{(V _DC +
2V _P )−V _S1 }, and this charge is transferred to transistor 1.
It is discharged through the collector of 1a.

Since all of these discharged charges flow through the collector of the transistor 11a, the amount of charge X flowing through the collector of the transistor 11a is as follows.

X={(V _DC +2V _P )−V _S }C(a ₃ Z ^-1.5 + a ₅ Z ^-2.5 ) However, Z=e ^s 〓 S=jω=2πf: f is the frequency of the input signal, that is, the collector of transistor 11 are the input signal delayed by 1.5τ and the signal delayed by 2.5τ, respectively.
Weighting is performed by a ₃ and a ₅ , and a charge corresponding to the sum of these weights is flown.

The average value of current I _AV due to this charge flow is I _AV =X/τ=X·f _C. And this current I _AV is the transistor 13
By flowing through a, twice this current is caused to flow through transistors 14a, 14a'.

Furthermore, the signal V _S that constitutes the amount of charge X includes a DC component V _SDC in addition to the AC component V _SAC . Therefore, if we calculate the DC component X _DC of the amount of charge X, we get V _S =
Assuming that V _SDC and Z=1, X _DC =2.{(V _DC +2V _P )−V _SDC }C(a ₃ +a ₅ ).

On the other hand, the circuit of the transistor 22a to the capacitor 26a has the same configuration as the first stage of the BBD. Therefore, the signal φ ₁ is applied to the capacitor 26a at V _DC +V _P
During the period, _{through the} transistor 15a: { ₍ V _DC +2V _P ) _{−V SDC} }
A charge of C(a ₃ +a ₅ ) is discharged. During the period when the signal φ ₂ is V _DC +V _P , charges equal to this are applied to the transistors 16a and 1.
7a, and twice this charge is passed through transistors 18a, 18a'. Therefore, the DC component X _DC of the amount of charge X described above is canceled out.

The canceled charge of this DC component X _DC is then supplied to the capacitor C _a1 . For this capacitor
The charge from the transistor Q _a2 and the above-mentioned charge amount X are supplied to C _a1 , and the transistor
The charge from Q _a2 is reduced by the amount of charge X. That is, negative feedback is applied by the amount of charge X.

Similarly, during the period when the signal φ ₂ is V _DC +V _P , the charges from the capacitors C _a2 ′, C _a4 ′, and C _a6 ′ are taken out through the transistor 16b. Also capacitor
Charges from C _b2 ′ and C _b4 ′ are taken out through transistor 11b. The difference between these charges is then supplied to the capacitor C _b0 . Furthermore, by supplying the charge from the capacitor 26b, DC fluctuations in the charge supplied to the capacitor C _b0 are removed, and a DC bias of (V _DC +2V _P -V _SDC ) is provided.

Also, when the signal _φ2 is V _DC +V _P , the capacitor
Charges from C _b1 ′, C _b3 ′, and C _b5 ′ are transferred to transistor 16
It is taken out through c. This amount of charge is output to the output terminal 41. Furthermore, by supplying the charge from the capacitor 26c, DC fluctuations in the charge output to the output terminal 41 are removed, and
A DC bias of (V _DC +2V _P -V _SDC ) is applied. The signal from this output terminal 41 is then supplied to a subsequent stage, for example, BBDc forming a YC separation circuit.

Furthermore, FIG. 4 is a schematic block diagram of the above-described circuit. In the figure, Z ^-1 indicates a unit delay circuit, which corresponds to two transistors in the circuit described above. Also, A and B are weighting coefficients that are twice the values of a and b in the above circuit (A ₂ = 2a ₂ ..., B ₁ = 2b ₁ ...)
shall be.

In other words, in the figure, the signal from input terminal 1 is
The signal is supplied to a synthesizer 52 through a Z ^-1/2 delay circuit 51, and the signal from this synthesizer 52 is supplied to a series circuit of Z ^- delay circuits 53, 54, and 55 forming BBDa. The outputs of the delay circuits 53 and 54 are weighted by weighting circuits 56 and 57 with coefficients A ₃ and A ₅ respectively.
The signal is supplied to the synthesizer 52 through the signal line and subtracted from the original signal. Further, the outputs of the delay circuits 53, 54, and 55 are applied to the weighting circuit 58 with coefficients A ₂ , A ₄ , and A _{6 ,} respectively.
The signals are supplied to the combiner 61 through 59 and 60 and added together. Signal BBDb from this synthesizer 61
The signal is supplied to a series circuit of delay circuits 62, 63, and 64 of Z ^-1 . The outputs of the delay circuits 62 and 63 are used as weighting circuits 65 and 65 with coefficients B ₂ and B ₄ , respectively.
66 to the combiner 61, and is subtracted from the above-mentioned addition signal. In addition, delay circuits 62, 63,
The outputs of 64 are supplied to a combiner 70 through weighting circuits 67, 68, and 69 of coefficients B ₁ , B ₃ , and B _{5 ,} respectively, and are added together. The signal from the synthesizer 70 is output to the output terminal 41. Further, each of the combiners 52, 61, and 70 has a DC correction circuit 7.
DC correction signals from 1, 72, and 73 are supplied.

Therefore, in this circuit, the transfer function H(z) from input terminal 1 to output terminal 41 is H(z)=A ₂ +A ₄ Z ^-1 +A ₆ Z ^-2 /1+A ₃ Z ^-1 +A ₅ Z
^-2・B ₁ +B ₃ Z ^-1 +B ₅ Z ^-2 /1+B ₂ Z ^-1 +B ₄ Z ^-2・Z ^--5/2 , where each coefficient A ₂ ~ A ₆ , B ₁ ~ B ₅ If we define as follows, this circuit becomes a 4.5MHz trap circuit.

A ₂ =0.856977 B ₁ =0.973363 A ₃ =0.559214 B ₂ =0.871633 A ₄ =0.673626 B ₃ =0.765112 A ₅ =0.828366 B ₄ =0.840204 A ₆ =0.856977 B ₅ =0. 973363 And the frequency at output terminal 41 of this circuit The characteristics are shown by solid line A in FIG.

However, in this circuit, the frequency characteristics up to the output side of the synthesizer 52 are as shown by the broken line B in FIG. Further, the frequency characteristics up to the output side of the synthesizer 60 are as shown by the dashed-dotted line C in FIG.
In other words, in these parts, peaking occurs in the high range from around 3MHz.

Therefore, when a signal is supplied to such a circuit,
Saturation may occur in areas where peaking occurs. Particularly in the case of composite color video signals, saturation occurs near the color subcarrier frequency of 3.58MHz. Furthermore, if the signal level is set so that it is 0 dB at the peaking part, the S/N of the entire signal will deteriorate.

Furthermore, since a direct current correction circuit is provided for each combiner, there is a drawback that the configuration thereof becomes complicated.

In view of these points, the present invention aims to provide a circuit that has a simple configuration and is free from saturation due to peaking. An embodiment of the present invention will be described below with reference to the drawings.

That is, in the present invention, the charge transfer element constituting the transversal filter is divided into a plurality of parts, each charge transfer element is configured as a filter, and these are arranged in descending order of frequency characteristic peaking within a desired band. In addition, these are connected in cascade.

In FIG. 6, five transistors Q _d1 ~
A first BBD, BBDd consisting of Q _d5 , and a second BBD, BBDe consisting of six transistors Q _e1 to Q _e6 .
and a third BBD, BBDf. this
BBDd capacitors C _d0 , C _d2 , C _d4 are divided,
C _d0 ′, C _d0 ″, C _d2 ′, C _d2 ″, C _d4 ′, C _d4 ″, respectively, and these capacitance values are d ₀ C,
(1-d ₀ )C, d ₂ C, (1-d ₂ )C, d ₄ C, (1-
d ₄ ) C. The cold end sides of one of these divided capacitors C _d0 ′, C _d2 ′, C _d4 ′ are connected to each other, and the other capacitors C _d0 ″, C _d2 ″,
The cold end side of C _d4 ″ is connected to terminal 6.

Further, circuits [transistors 11d to 18d] equivalent to the transistors 11a to 18a are provided, and the connection point of the bases of the transistors 11d and 12d is connected to the terminal 37, and the transistor 1
The connection points of the bases of 5d and 16d are connected to the terminal 36.

The cold end sides of the transistors C _d0 ′, C _d2 ′, and C _d4 ′ are connected to the connection point of the emitters of the transistors 15d and 16d.

Furthermore, the capacitors C _e2 and C _e4 of BBDe are divided into C _e2 ′, C _e2 ″, C _e4 ′, and C _e4 ″, respectively, and their capacitance values are e ₂ C, (1−e ₂ ), respectively.
C, e ₄ C, (1-e ₄ )C. The cold ends of these divided capacitors C _e2 ′ and C _e4 ′ are connected to each other, and this connection point is connected to the connection point of the emitters of transistors 11d and 12d. Further, the cold end sides of the other capacitors C _e2 ″ and C _e4 ″ are connected to the terminal 7 . And transistor 1 on the output side of current mirror circuits M _1d and M _2d
The connection points of the collectors 4d, 14d', 18d, and 18d' are connected to the hot end side of the capacitor C _e0 .

In addition, the capacitors C _e1 , C _e3 , and C _e5 of BBDe are divided into C _e1 ′, C _e1 ″, C _e3 ′, C _e3 ″, C _e5 ′, respectively.
C _e5 ″ and these capacitance values are respectively
e ₁ C, (1-e ₁ ) C, e ₃ C, (1-e ₃ ) C, e ₅ C, (1
−e ₅ ) is assumed to be C. The cold end sides of one of these divided capacitors C _e1 ′, C _e3 ′, C _e5 ′ are connected to each other, and the other capacitors C _e1 ″, C _e3 ,
The cold end side of C _e5 ″ is connected to terminal 6.

In addition, circuits [transistors 11e to 18e] equivalent to the transistors 11a to 18a are provided, and the connection point of the bases of the transistors 11e and 12e is connected to the terminal 37, and the transistor 1
The connection points of the bases of 5e and 16e are connected to the terminal 36.

The cold ends of the capacitors C _e1 ′, C _e3 ′, and C _e5 ′ are connected to the connection point of the emitters of the transistors 15e and 16e.

Furthermore, the capacitors C _f2 and C _f4 of BBDf are divided,
C _f2 ′, C _f2 ″, C _f4 ′, C _f4 ″, respectively, and
These capacitance values are _f2C , (1- _f2 )C,
f ₄ C, (1-f ₄ )C. The cold ends of these divided capacitors C _f2 ′ and C _f4 ′ are connected to each other, and this connection point is connected to transistor 1.
It is connected to the connection point of emitters 1e and 12e.
Further, the cold end sides of the other capacitors C _f2 ″ and C _f4 ″ are connected to the terminal 7 . And the transistor 14 on the output side of the current mirror circuit M _1e , M _2e
The collectors of capacitors e, 14e', 18e and 18e' are connected to the hot end side of capacitor C _f0 .

In this circuit, the signals of the capacitors C _d0 ′, C _d2 ′, C _d4 ′, C _e2 ′, and C _e4 ′ are taken out during the period when the signal φ ₂ is V _DC +V _P , and these are combined and output to the capacitor.
C is supplied to _e0 . Similarly, the signal φ ₂ is V _DC +V _P
During the period, capacitors C _e1 ′, C _e3 ′, C _e5 ′, C _f2 ′,
The signals of C _f4 ' are taken out and combined and supplied to the capacitor C _f0 .

Furthermore, if this circuit is drawn as a schematic block diagram similar to that shown in FIG. 4 above, it will become as shown in FIG. 7. In the figure, D, E, and F are twice d, e, and f (D ₁ = 2d ₁
..., E ₁ = 2e ₁ ..., F ₁ = 2f ₁ ...).

In other words, in the figure, the signal from input terminal 1 is
It is supplied to a series circuit of Z ^-1 delay circuits 81 and 82 forming BBDd. The signal from this input terminal 1 and the outputs of delay circuits 81 and 82 are respectively coefficients D ₀ ,
The signals D ₂ and D ₄ are supplied to a combiner 86 through weighting circuits 83, 84, and 85, and are added together. The signal from this synthesizer 86 constitutes BBDe Z ^-1
The signal is supplied to a series circuit of delay circuits 87 and 88.
The outputs of these delay circuits 87 and 88 are coefficients, respectively.
It is supplied to the combiner 86 through weighting circuits 89 and 90 for E ₂ and E ₄ and subtracted from the above-mentioned addition signal. In addition, the signal from the synthesizer 86 and the delay circuit 87,
The outputs of 88 are supplied to a combiner 94 through weighting circuits 91, 92, and 93 with coefficients E ₁ , E ₃ , and E _{5 ,} respectively, and are added together. A Z ^-1 delay circuit 95 in which the signal from the synthesizer 94 constitutes BBDf;
96 series circuits. This delay circuit 9
The outputs of 5 and 96 are supplied to a combiner 94 through weighting circuits 97 and 98 with coefficients F ₂ and F ₄ , respectively, and are subtracted from the above-mentioned addition signal.

Therefore, in this circuit, the transfer relationship H(z) from input terminal 1 to the output side of combiner 94 is H(z)=D ₀ +D ₂ Z ^-1 +D ₄ Z ^-2 /1+E ₂ Z ^-1 +E ₄ Z
^-2・E ₁ +E ₃ Z ^-1 +E ₅ Z ^-2 /1+F ₂ Z ^-1 +F ₄ Z ^-2・Z ^--5/2 , where each coefficient D ₀ ~ D ₄ , E ₁ ~ E ₅ , _F2 ~ _F4
, D ₀ = A ₂ , D ₂ = A ₄ , D ₄ = A ₆ , E ₁ = B ₁ , E ₂ =
A ₃ , E ₃ = 2 ₃ , E ₄ = A ₅ , E ₅ = B ₅ , F ₂ = B ₂ , F ₄ = B ₄
By doing so, a 4.5MHz trap circuit similar to that described above can be obtained. Note that the output signal is
It can be taken out arbitrarily from each stage of BBDf.

In this circuit, the frequency characteristic from the input terminal 1 to the output side of the synthesizer 86 is as shown by the broken line A in FIG. On the other hand, the frequency characteristics from the raw power side of the synthesizer 86 to the output side of the synthesizer 94 are as shown by the dashed line B in FIG. characteristics are obtained. In this characteristic diagram, the broken line A shows no peaking within the video signal band, but the dashed line B shows peaking.

Here, each coefficient is D ₀ ←→E ₁ , D ₂ ←→E ₃ , D ₄ ←→E ₅ , E ₂
Even if they are switched between ←→F ₂ and E ₄ ←→F ₄ , the frequency characteristics from the input terminal 1 to the output side of the synthesizer 94 will be the same. However, in that case, peaking occurs in the frequency characteristics from the input terminal 1 to the output side of the synthesizer 86.

That is, in the above circuit, the frequency characteristic at the output side of the synthesizer 86 is as shown by the broken line A, and by further supplying this signal to a circuit with the frequency characteristic as shown by the dashed line B, the synthesizer The frequency characteristic on the output side of 94 is as shown by solid line C. Therefore, even if peaking occurs in the latter half of this circuit, no peaking will occur in the overall characteristics from the first half.

In this way, a 4.5MHz trap circuit is constructed.According to the present invention, the filter is divided into a plurality of filters, and a circuit that does not cause peaking is placed at the front stage, so that each intermediate point The occurrence of peaking can be prevented.

Furthermore, in the above circuit, the low-frequency gain of each divided filter is all 0 dB as shown in Figure 8, so the DC level is always constant.
There is no need to provide a DC correction circuit, and the circuit configuration becomes extremely simple.

Furthermore, in the above-mentioned circuit, BBDf can also serve as a part of the BBD constituting the YC separation filter in the subsequent stage, for example.

The present invention is applicable not only to BBD but also to all types of CCD etc.
Applicable to CTD. Moreover, it can be applied not only to 4.5MHz trap circuits but also to various filters such as 3.58MHz trap circuits.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams for explaining the BBD, Figure 3 is a configuration diagram of a conventional transversal filter, Figures 4 and 5 are diagrams for explaining it, and Figure 6 is a diagram for explaining the BBD.
The figure is a block diagram of an example of the present invention, and FIGS. 7 and 8 are diagrams for explaining the same. 1 is an input terminal, C is a capacitor that forms the BBD, Q is a transistor that forms the BBD, 81,
82, 87, 88, 95, 96 are Z ^-1 delay circuits,
83 to 85, 89 to 93, 97, and 98 are weighting circuits, and 86 and 94 are combiners.

Claims (1)

[Claims] 1. In a cyclic transversal filter using a charge transfer element, the charge transfer element is divided into a plurality of parts to constitute a front-stage filter and a rear-stage filter connected in cascade to the front-stage filter, and each of the front-stage and rear-stage filters has a common structure. The filter constants of the front and rear stages are selected so that the peaking amount of the front stage filter is smaller than the peaking amount of the rear stage filter, and the total of the cascade-connected front and rear stage filters is filtered. A cyclic transversal filter that filters the common band according to its characteristics and prevents saturation of the signal by making the peaking amount of the post-stage filter larger than the peaking amount of the pre-stage filter.