JPS634658A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS634658A JPS634658A JP61146894A JP14689486A JPS634658A JP S634658 A JPS634658 A JP S634658A JP 61146894 A JP61146894 A JP 61146894A JP 14689486 A JP14689486 A JP 14689486A JP S634658 A JPS634658 A JP S634658A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- sealing body
- slits
- semiconductor chip
- electronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007789 sealing Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 230000008602 contraction Effects 0.000 claims 1
- 230000035882 stress Effects 0.000 abstract description 12
- 230000008646 thermal stress Effects 0.000 abstract description 10
- 238000005336 cracking Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 230000003313 weakening effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 239000000725 suspension Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路等の電子装置に関し、特に面
実装型と呼ばれている半導体集積回路に適用して好適な
技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to electronic devices such as semiconductor integrated circuits, and particularly relates to a technique suitable for application to semiconductor integrated circuits called surface mount type. .
半導体集積回路（以下においてＩＣという）は、デバイ
ス技術の向上にともなって次第に小型化される傾向にあ
る。そしてピン挿入タイプに対し、面実装型、或いは面
取付実装タイプと呼ばれているものが多用されつつある
。2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as ICs) tend to become increasingly smaller as device technology improves. In contrast to the pin insertion type, a surface mount type or a surface mount type is increasingly being used.
上記面実装型については、「電子材料Ｊ （１９８５年
２月号、発行所工業調査会、ｐｐ３３〜３７）に記載さ
れている。その概要は、本格的な薄型高密度実装用に開
発されたものが面取付タイプパッケージであり、実装方
法としては赤外線加熱リフロー法等が採用される、とい
うものである。The above-mentioned surface mount type is described in "Electronic Materials J (February 1985 issue, Kogyo Kenkyukai, pp. 33-37). The product is a surface-mounting type package, and an infrared heating reflow method is used as the mounting method.
本発明者は、上記面実装型ＩＣを実装する場合の信頼性
向上について検討した。The present inventor has studied how to improve the reliability when mounting the above-mentioned surface mount type IC.
以下は、公知とされた技術ではないが、本発明者によっ
て検討された技術であり、その概要は次のとおりである
。Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.
すなわち、面実装型ＩＣを実装基板（プリント基板等）
に実装する場合、半田ディッピングや赤外線リフロー法
等により、電極アウターリード部（外部接続端子）を半
田を介して実装基板に電気的接合する。これらの実装方
法では、パッケージが２６０℃〜３００℃にも加熱され
る。この際パッケージ内部において、半導体チップとレ
ジン等の封止体との間、更にリードフレームとレジン等
の異質物体間に界面剥離が発生することが明らかになっ
た。上記現象は、異質物体の熱膨張係数が相違するため
に発生するものである。上記界面剥離が発生すると、下
記の如き問題点が発生することが明らかになった。In other words, a surface mount IC is mounted on a board (printed board, etc.)
When mounting on a PCB, the electrode outer lead portion (external connection terminal) is electrically bonded to the mounting board via solder by solder dipping, infrared reflow method, or the like. In these mounting methods, the package is heated to as much as 260°C to 300°C. At this time, it has become clear that interfacial delamination occurs inside the package between the semiconductor chip and the sealing body such as resin, and between the lead frame and a foreign object such as resin. The above phenomenon occurs because the different materials have different coefficients of thermal expansion. It has become clear that when the above-mentioned interfacial peeling occurs, the following problems occur.
すなわち、第６図に示すように半導体チップ１とタブ２
との間に界面剥離３が発生すると、その界面剥離３部分
に水分がたまりやすく、クロルイオンＣ！−等を含んだ
水分の介在により半導体チップに形成されたアルミパッ
ドやアルミ配線を腐食させることが明らかＫな）た。上
記腐食は、ＩＣの短命化をもたらすものであり、好まし
くない。That is, as shown in FIG.
When interfacial peeling 3 occurs between C! It is clear that the presence of moisture containing - etc. corrodes the aluminum pads and aluminum wiring formed on the semiconductor chip. The above corrosion is undesirable because it shortens the life of the IC.
更ｋ、上記界面剥離は、半導体チップを固定するタブの
コーナー部、換言すれば角部に多く発生することが明ら
かになった。これは、角部に熱応力が集中するためであ
る。上記界面剥離が大であると、その近傍においてレジ
ンクラック、換言すれば封止体に割れが発生しやすく、
これが製品不良の一因となることも本発明者の検、討に
より明らかｋなった。Furthermore, it has been revealed that the above-mentioned interfacial peeling occurs more frequently at the corner portions of the tabs that fix the semiconductor chips, in other words, at the corner portions. This is because thermal stress is concentrated at the corners. If the above-mentioned interfacial peeling is large, resin cracks, in other words, cracks in the sealing body, are likely to occur in the vicinity.
It has become clear through investigation and investigation by the present inventors that this is a cause of product defects.
本発明の目的は、電子装置を構成する半導体チップとタ
ブ、封止体とリード部品等の異質物体間の界面剥離を低
減し、電子装置の信頼性を向上させることにある。An object of the present invention is to reduce interface peeling between dissimilar objects such as a semiconductor chip and a tab, a sealing body and a lead component, which constitute an electronic device, and improve the reliability of the electronic device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書および添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップを固定するためのタブの周辺部
に応力吸収手段としてたとえばスリット、切り込み、丸
穴等の各種形状の開口部を形成し、レジン材等の封止体
により半導体チップ、タブ、外部接続端子等を一体に封
止して電子装置を構成するものである。In other words, openings of various shapes such as slits, notches, and round holes are formed as stress absorbing means in the periphery of the tab for fixing the semiconductor chip, and the semiconductor chip, the tab, and the external An electronic device is constructed by integrally sealing connection terminals and the like.
上記した手段によれば、上記開口部によってタブの角部
のレジンの接着力が増しタブの角部に集中する応力が応
力吸収手段としての開口部によって緩和される。そして
赤外線り７０−法等により封止体が加熱されても、タブ
に作用する熱応力が応力吸収手段によって緩和され、タ
ブ上下の封止体が強固に接着しているので、タブ、リー
ドフレームの反り等の変形が押えられるようになり、上
記異質物体間の界面剥離が低減される。この結果、上記
界面剥離にともなって発生するアルミ配線の腐食、封止
体の割れ等の問題点が解決され、電子装置の信頼性を向
上せしめる、という本発明の目的が達成される。According to the above-mentioned means, the adhesive strength of the resin at the corners of the tab is increased by the openings, and the stress concentrated at the corners of the tab is alleviated by the openings serving as stress absorbing means. Even if the sealing body is heated by an infrared ray method or the like, the thermal stress acting on the tab is alleviated by the stress absorbing means, and the sealing bodies above and below the tab are firmly bonded. deformation such as warpage is suppressed, and interfacial peeling between the dissimilar objects is reduced. As a result, problems such as corrosion of the aluminum wiring and cracking of the sealing body that occur due to the above-mentioned interface peeling are solved, and the object of the present invention, which is to improve the reliability of electronic devices, is achieved.
〔実施例−１〕
以下、ｆｌ！１１図〜第３図上第３図て本発明を適用し
た電子装置の第１実施例を説明する。[Example-1] Below, fl! 11 to 3, a first embodiment of an electronic device to which the present invention is applied will be described.
なお、第１図は電子装置の内部構造を示す要部の平面図
、第２図は電子装置の斜視図、第３図は電子装置の要部
の断面図である。Note that FIG. 1 is a plan view of the main parts showing the internal structure of the electronic device, FIG. 2 is a perspective view of the electronic device, and FIG. 3 is a sectional view of the main parts of the electronic device.
本実施例の特徴は、タブの角部にスリットを形成し、タ
ブに作用する応力を緩和すると同時に封止体の一体化を
増強せしめたことにあり、本発明は面実装蛮ＩＣに適用
されている。The feature of this embodiment is that slits are formed at the corners of the tab to alleviate the stress acting on the tab and at the same time enhance the integration of the sealing body.The present invention is applicable to surface-mounted ICs. ing.
面実装型ＩＣ１１において、１２はタブ、１３はタブ吊
りリード、１４は半導体チップであり、上記タブ、１２
のほぼ中央部に固定されている。そして半導体チップ１
４に形成されたパッド１５とインナーリード１６とはＡ
Ａ線、或いはＡｕ線等はよりボンディングされている。In the surface-mounted IC 11, 12 is a tab, 13 is a tab suspension lead, and 14 is a semiconductor chip.
It is fixed almost in the center of the and semiconductor chip 1
The pad 15 and inner lead 16 formed in A
A wire, Au wire, etc. are more bonded.
なお、仮想線入は、第２図に示すよ５に封止体２１によ
って封止されたときの外縁部を示すものであり、１７は
面付は実装可能に形成された外部接続端子である。Note that the imaginary line mark 5 indicates the outer edge when sealed by the sealing body 21 as shown in FIG. .
ここで注目すべきは、上記タブ１２のコーナー部、換言
すれば四隅の角部にかぎ型のスリット２０が形成されて
いることである。上記スリット２０は、本発明でいう開
口部に相当するものである。What should be noted here is that hook-shaped slits 20 are formed at the corners of the tab 12, in other words, at the four corners. The slit 20 corresponds to an opening in the present invention.
上記スリット２０を形成することにより、角部に応力が
作用した場合、スリット２０によって緩和され、半導体
チップ１４方向く伝達する力が弱められる。更に、第３
図に示すように封止体２１がスリブ）２０の形成位置く
おいて一体化される部分が大になる。説明の便宜のため
、タブ１２から上部の封止体２１を上側パッケージ、下
部の封止体２１を下側パッケージとすると、両者を結合
する部分がスリット２０の面積分に応じて大になり、−
体化が増強される。しかもスリブ）２０の形成位置は１
．実装時に最も熱応力が集中するタブ１２０角部である
から、タブ１２の角部が封止体１２によって最も強く押
えつけられるようｋなる。By forming the slits 20, when stress acts on the corners, it is relieved by the slits 20, and the force transmitted in the direction of the semiconductor chip 14 is weakened. Furthermore, the third
As shown in the figure, a large portion of the sealing body 21 is integrated at the position where the sleeve 20 is formed. For convenience of explanation, let us assume that the sealing body 21 above the tab 12 is an upper package and the sealing body 21 below is a lower package. −
Embodiment is enhanced. Moreover, the formation position of the sleeve) 20 is 1
．． Since these are the corners of the tab 120 where thermal stress is most concentrated during mounting, the corners of the tab 12 are pressed most strongly by the sealing body 12.
換言すれば、タブ２１が変形しようとしても、封止体２
１によって強固に固定され、変形し得ない状況になる。In other words, even if the tab 21 tries to deform, the sealing body 2
1, it is firmly fixed and cannot be deformed.
上記封止体２１の固定は、半導体チップ１４にも作用す
るので、タブ１２と半導体チップ１４との間に、第３図
に示すように界面剥離が発生しな（なる。したがってタ
ブ１２と半導体チップ１４との間に水分がたまることが
なく、これに付随して発生する上記問題点が解消される
ことになる。Since the fixing of the sealing body 21 also acts on the semiconductor chip 14, no interfacial peeling occurs between the tab 12 and the semiconductor chip 14 as shown in FIG. Moisture will not accumulate between the tip and the chip 14, and the above-mentioned problems associated with this will be solved.
上記電子装置は、下記の如き効果を奏するものである。The above electronic device has the following effects.
（１） 半導体チップを固定するタブの周辺部で最も
熱応力が集中する角部にスリットを形成し、熱応力を緩
和するとともに、封止体が一体化する部分を上記スリッ
トの面積に応じて増強するように構成することにより、
タブ、半導体チップの熱応力による変形を低減する、と
いう効果が得られる。(1) A slit is formed at the corner where thermal stress is most concentrated around the tab that fixes the semiconductor chip to alleviate the thermal stress, and the area where the sealing body is integrated is adjusted according to the area of the slit. By configuring to enhance
This has the effect of reducing deformation of the tab and semiconductor chip due to thermal stress.
（２）上記（１）により、タブ、半導体チップ間に界面
剥離が発生せず、水分の介在が低減されて、製品の信頼
度が向上する、という効果が得られる。(2) According to the above (1), there is no interfacial peeling between the tab and the semiconductor chip, the presence of moisture is reduced, and the reliability of the product is improved.
（３） 上記（１）により、封止体の割れが低減され
、製品の信頼度が向上する、という効果が得られる。(3) According to the above (1), cracking of the sealed body is reduced, and the reliability of the product is improved.
（４） 上記（１）たより、高温による加熱が可能に
なり、実装時の作業が容易になる。という効果が得られ
る。(4) Based on the above (1), it becomes possible to heat the device at a high temperature, which facilitates the work during mounting. This effect can be obtained.
〔実施例−２〕
次に、第４図を参照して本発明の第２実施例を説明する
。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG.
なお、第４図囚〜（至）は上記スリットとして示した開
口部の各種形状を示すものであり、タブに作用する熱応
力、封止体との関連は上記第３図について述べたとおり
である。Note that Figures 4 to 4 show various shapes of the opening shown as the slit above, and the relationship between the thermal stress acting on the tab and the sealing body is as described in Figure 3 above. be.
タブ１２の角部には、第４図（２）に示すように開口部
として丸穴３１を形成してもよい。A round hole 31 may be formed at the corner of the tab 12 as an opening, as shown in FIG. 4(2).
この場合も、角部に作用する応力が緩和され、丸穴３１
の開口面積に対応して封止体の一体化が増強される。In this case as well, the stress acting on the corner is relaxed and the round hole 31
The integration of the sealing body is enhanced in accordance with the opening area of .
タブ１２の角部には、第４図０３）に示すように、開口
部としての角型のスリット３２を形成してもよい。この
場合も、角部に作用する応力が緩和され、スリット３２
の開口面積忙対応して封止体の一体化が増強される。A rectangular slit 32 as an opening may be formed at the corner of the tab 12, as shown in FIG. 4 (03). In this case as well, the stress acting on the corner is relaxed and the slit 32
The integration of the sealing body is enhanced in accordance with the opening area of the opening.
タブ１２の角部には、第４図（Ｑに示すように開口部と
して切り込み部３３を形成してもよい。この場合も、角
部に作用する応力が緩和され、切り込み部３３の開口面
積に対応して封止体の一体化が増強される。A notch 33 may be formed at the corner of the tab 12 as an opening, as shown in FIG. Accordingly, the integration of the sealing body is enhanced.
タブ１２０角部には、第４図■に示すように開口部３４
として切り込みとスリットとを合せた形状のものを形成
してもよい。この場合も、角部に作用する応力が緩和さ
れ、開口部３４の開口面積に対応して封止体の一体化が
増強される。The corner of the tab 120 has an opening 34 as shown in FIG.
Alternatively, a combination of a cut and a slit may be formed. In this case as well, the stress acting on the corners is relaxed, and the integration of the sealing body is enhanced in accordance with the opening area of the opening 34.
上記各形状の開口部をタブに形成することにより、この
リード部品を用いた電子装置は、上記同様の効果を奏す
ることができる。By forming the openings in the above shapes in the tab, an electronic device using this lead component can achieve the same effects as above.
〔実施例−３〕
次に、第５図を参照して本発明の第３実施例を説明する
。[Embodiment 3] Next, a third embodiment of the present invention will be described with reference to FIG.
本実施例の特徴は、上記各実施例と同様に界面剥離を低
減するとともに、タブ吊りリードを介して侵入しようと
する水分を低減し得るように構成したことＫある。The feature of this embodiment is that, like the above-mentioned embodiments, it is configured to reduce interfacial peeling and to reduce moisture that attempts to enter through the tab suspension lead.
４１はタブであり、そのほぼ中央部には半導体チップ４
２が固定されている。そしてタブ４１の外周部でタブ吊
りリード４３との結合部に開口部として丸穴４４が形成
されている。41 is a tab, and the semiconductor chip 4 is located almost in the center of the tab.
2 is fixed. A round hole 44 is formed as an opening at the outer circumference of the tab 41 at the joint with the tab suspension lead 43.
上記丸穴４４は、上記各実施例と同様に封止体の結合を
増強する作用を有すると同時に下記の如き注目すべき作
用を有する。The round hole 44 has the effect of enhancing the bonding of the sealing body as in each of the above embodiments, and at the same time has the following noteworthy effect.
すなわち、電子装置内に侵入しようとする水分は、タブ
吊りリード４３を伝わって侵入する分が、大である。こ
の侵入径路に丸穴４４を形成すると、侵入径路の面積が
小になる。換言すれば、水分く対する抵抗が増大するこ
とになり、電子装置の耐湿性が向上する。That is, a large portion of the moisture that attempts to enter the electronic device passes through the tab suspension lead 43. By forming the round hole 44 in this intrusion path, the area of the intrusion path becomes smaller. In other words, the resistance to moisture increases, and the moisture resistance of the electronic device improves.
本実施例に示したリードフレームを用いた電子装置は、
上記効果を奏するうえに下記の効果を奏する。The electronic device using the lead frame shown in this example is
In addition to the above effects, the following effects are also achieved.
（５） タブとタブ吊りリードとの結合部に開口部を
形成することＫより、タブ吊りリードを介して侵入する
水分九対し抵抗が大になり、水分の侵入が低減されて電
子装置の耐湿性が向上する、という効果が得られる。(5) Forming an opening at the joint between the tab and the tab suspension lead increases the resistance to moisture entering through the tab suspension lead, reduces moisture intrusion, and improves the moisture resistance of electronic devices. This has the effect of improving sexual performance.
以上に、本発明者によってなされた発明を実施例にもと
づき具体的に説明したが、本発明は上記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることはいうまでもない。例えば、開口部は
第１実施例に示すタブ吊りリードの近傍に形成してもよ
い。Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the opening may be formed near the tab suspension lead shown in the first embodiment.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野である面実装型のＩＣに
適用した場合について説明したが、それに限定されるも
のではなく、ＤＩＰ型のＩＣ等、ピン挿入量の電子装置
にも利用することができる。In the above explanation, the invention made by the present inventor was mainly applied to surface-mounted ICs, which is the background field of application. , it can also be used in electronic devices with pin insertion.
本願において開示される発明のうち代表的なものＫより
【得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained from representative invention K among the inventions disclosed in this application is as follows.
すなわち、タブの外周部でありて特に加熱時に熱応力の
集中しやすい角部に開口部を形成することＫより、加熱
時の応力を緩和するとともに封止体の一体化を増強する
ことができ、タブの変形、タブとこれに固定された半導
体チップとの間の界面剥離が低減されるので、電子装置
の耐湿性の向上、封止体の割れの低減を計ることができ
る。In other words, by forming an opening at the corner of the outer periphery of the tab where thermal stress tends to concentrate especially during heating, it is possible to alleviate the stress during heating and enhance the integration of the sealing body. Since the deformation of the tab and the interfacial peeling between the tab and the semiconductor chip fixed thereto are reduced, the moisture resistance of the electronic device can be improved and the cracking of the sealed body can be reduced.
第１図〜第３図は本発明を適用した電子装置の第１実施
例を示すものであって、
第１図は電子装置の内部構造を示す要部の平面図、
第２図は電子装置の外形を示す斜視図、第３図は電子装
置の内部構造を示す要部の断面種形状の平面図、
第５図は本発明の第３実施例を示すタブの平面図、
第６図は本発明に先だって検討された電子装置の要部の
断面図をそれぞれ示すものである。
１１・・・電子装置、１２．４１・・・タブ、１３．４
３・・・タブ吊りリード、１４．４２・・・半導体チッ
プ、１５・・・パッド、２０，３１，３２，３３，３４
゜４４・・・開口部、２１・・・封止体。
代理人 弁理士 小 川 勝 男
第 ２ 図
第 ３ 図
ノｌ
／Ｚ
第 ４ 図1 to 3 show a first embodiment of an electronic device to which the present invention is applied. FIG. 1 is a plan view of the main parts showing the internal structure of the electronic device, and FIG. 3 is a plan view of the cross-sectional shape of the main part showing the internal structure of the electronic device, FIG. 5 is a plan view of the tab showing the third embodiment of the present invention, and FIG. 1A and 1B each show cross-sectional views of essential parts of electronic devices that were considered prior to the present invention. 11...Electronic device, 12.41...Tab, 13.4
3... Tab suspension lead, 14.42... Semiconductor chip, 15... Pad, 20, 31, 32, 33, 34
゜44... Opening portion, 21... Sealing body. Agent Patent Attorney Katsutoshi Ogawa Figure 2 Figure 3 Figure No. 1 /Z Figure 4
Claims (1)
と、上記半導体チップ主面に形成された複数のパッドと
、上記タブの周囲に設けられた複数のリードと、上記複
数のリードと上記複数のリードとを電気的に接続するワ
イヤと上記半導体チップと上記タブと上記複数のリード
と上記ワイヤとを封止する封止体とを用い上記タブの周
辺部に応力吸収手段が設けられていることを特徴とする
電子装置。 ２、上記応力吸収手段は上記タブの角部に設けられた開
口部であることを特徴とする特許請求の範囲第１項記載
の電子装置。 ３、上記応力吸収手段は樹脂からなる封止体の熱収縮に
よりタブに作用する応力を吸収することを特徴とする特
許請求の範囲第１項記載の電子装置。[Claims] 1. A semiconductor chip, a tab for fixing the semiconductor chip, a plurality of pads formed on the main surface of the semiconductor chip, a plurality of leads provided around the tab, and the plurality of leads provided around the tab. A stress absorbing means is provided around the tab using a wire electrically connecting the lead and the plurality of leads, the semiconductor chip, the tab, a sealing body sealing the plurality of leads and the wire. An electronic device characterized by being provided with. 2. The electronic device according to claim 1, wherein the stress absorbing means is an opening provided at a corner of the tab. 3. The electronic device according to claim 1, wherein the stress absorbing means absorbs stress acting on the tab due to thermal contraction of a sealing body made of resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61146894A JPS634658A (en) | 1986-06-25 | 1986-06-25 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61146894A JPS634658A (en) | 1986-06-25 | 1986-06-25 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS634658A true JPS634658A (en) | 1988-01-09 |
Family
ID=15417978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61146894A Pending JPS634658A (en) | 1986-06-25 | 1986-06-25 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS634658A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110886A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Lead frame for semiconductor and semiconductor device using the same |
| JP4643753B1 (en) * | 2010-06-03 | 2011-03-02 | 晋一 深田 | Culture support hydroponic equipment |
| JP2017216294A (en) * | 2016-05-30 | 2017-12-07 | 株式会社デンソー | Semiconductor device manufacturing method |
-
1986
- 1986-06-25 JP JP61146894A patent/JPS634658A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110886A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Lead frame for semiconductor and semiconductor device using the same |
| JP4643753B1 (en) * | 2010-06-03 | 2011-03-02 | 晋一 深田 | Culture support hydroponic equipment |
| JP2011250762A (en) * | 2010-06-03 | 2011-12-15 | Shinichi Fukada | Hydroponic culture device for supporting culture soil |
| JP2017216294A (en) * | 2016-05-30 | 2017-12-07 | 株式会社デンソー | Semiconductor device manufacturing method |
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