JPS634644A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate the need for mounting a timing generating circuit, etc., and to simplify a peripheral circuit by reading the information of a memory cell by a static system. CONSTITUTION:A source region in a first MISFET Qp or Qn for a fundamental cell 5 is connected at first fixed potential Vcc or Vss, a source region in a second MISFET Qn or Qp at second fixed potential Vss or Vcc and drain regions in the first and second MISFETs to a data line D, thus constituting a memory cell. A gate electrode for the first MISFET is connected to first fixed potential or a word line W and a gate electrode for the second MISFET to the word line W or second fixed potential respectively, thus organizing the information of a memory cell for an ROM 4B. Accordingly, the information of the memory cell M can be read by a static system.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device that employs a master slice method and has a memory function.

[Conventional technology]

Semiconductor integrated circuit devices that use the master slice method are
Many memory functions and logic functions can be formed by changing the wiring pattern on the master wafer. The master wafer has a plurality of basic cells each composed of one or more semiconductor elements arranged in a first direction to form a basic cell column, and the basic cell column is arranged in a row direction in a predetermined manner with a wiring area interposed therebetween. It consists of multiple locations arranged at intervals of .

Semiconductor integrated circuit devices employing this type of master slicing method are characterized by being able to complete products in a short time in response to requests from users. On the manufacturer side, in order to reduce the development and production costs of master wafers, they optimize the layout of basic cells, form as many memory and logical functions as possible, and increase the efficiency of master wafer usage. Need to improve.

Therefore, a technology has been proposed that can efficiently form a ROM (memory function) in a basic cell that mainly has a logic function (
1985 IEE International Solid State Circuits Conference (19851E
EE 1international 5olid-St
aLe C1rcuits Conference)
p126. p127), ROM of this technology is complementary type M
A memory cell unit is composed of nine basic cells composed of IS FETs. The memory cell unit is
Information is written into eight n-channel first MISFETs (memory cells), and one n-channel second MISFET
is used as an MI S FET for memory cell unit selection. Each drain region of the first MISFET is connected to the data line, and each source region of the first MISFET is connected to the second MISFET.
It is connected to a reference potential (ground potential) via a FET. In other words, information is read out from this ROM in a dynamic manner. Writing of information to the first MISFET (memory cell) is performed by connecting the gate electrode to a word line or to a reference potential.

[Problem that the invention seeks to solve]

The present inventor has developed the results of studies on such technology.

It was found that the following problem occurred.

Since the above-mentioned ROM uses a dynamic method for reading information, taking into consideration the variety of ways in which the ROM is used, variations are likely to occur in the parasitic capacitance of the data line, the operation timing, etc. Therefore, a control circuit for an information read operation, a timing signal generation circuit, etc. are required, and peripheral circuits such as a decoder circuit become complicated.

Furthermore, in the dynamic method, malfunction may occur due to capacitive coupling between wires at different potentials and data lines. For this reason, wiring with different potentials.

Since the wiring cannot pass over the ROM block and must take a detour, the wiring efficiency of the entire semiconductor integrated circuit device (LSI) decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for performing an information read operation of a memory function using a static method in a semiconductor integrated circuit device that employs a mask slicing method, thereby solving problems caused by a dynamic method. .

Another object of the present invention is to provide a technique capable of improving the degree of integration of the memory function and simplifying the circuit configuration of the memory function in a semiconductor integrated circuit device that employs the master slice method. be.

Another object of the present invention is to provide a technique that achieves the above-mentioned object and allows information to be written to the storage function efficiently and in a short time.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Means for solving problems]

The outline of one typical invention disclosed in this application is as follows.

Complementary MI5FE consisting of first and second Mt 5FETs
In a semiconductor integrated circuit device adopting a master slicing method in which a basic cell is configured with T, the first M of the basic cell is
The source region of the ISFET is set to the first fixed potential, the second MISF
The source region of ET is set at a second fixed potential, and the first and second MIS
The drain region of the FET is connected to a data line to form a memory cell.

The gate electrode of the first MISFET is connected to a first fixed potential or a word line, and the gate electrode of the second MISFET is connected to a word line or a second fixed potential, respectively, to configure information in the memory cell.

[For production]

According to the above-mentioned means, since the information of the memory cell can be read out in a static manner, there is no need to provide a timing generation circuit or the like, and the peripheral circuitry can be simplified.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example! ]

Embodiment I is an embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device equipped with a ROM that employs a master slice method.

FIG. 1 (schematic plan view) shows a semiconductor integrated circuit device employing a master slice method according to a first embodiment of the present invention.

As shown in FIG. 1, a plurality of external terminals (bonding pads) and 21 output buffer circuits 3 are arranged around the periphery of a semiconductor integrated circuit device 11 that employs a master slice method.

Although not shown in the figure, there are power supply voltage (for example, circuit operating voltage 5 [V]) wiring V c c , 'base 1
1! Voltage (e.g. circuit ground potential OrV) distribution I! J.I.
vss is extended respectively.

A reinforcing power supply voltage wiring Vce or reference voltage wiring Vss extends in the center of the semiconductor integrated circuit device l.

A logic circuit (logic function) 4A, a ROM (memory function) 4B, and a RAM (memory function) 4G are arranged in the center of the semiconductor integrated circuit device 11, respectively.

Each of the logic circuit 4A, ROM4B, and RAM4C is
It is composed of basic cells 5 shown in the figure (plan view of main part).

Basic cell 5 has four p-channel MISFET
Q p I-Q p a and four n-channel MIS
FETQrz "Complementary MISFET consisting of Qn4
It consists of

The MISFET Qp is an n-type transistor provided on the main surface of an n-type semiconductor substrate 6 in a region surrounded by a field insulating film 12.
It is composed of a type well region 7, a gate insulating film, a gate electrode 9, and a P″ type source region and drain region 10.

, source region or drain region 10 of MISFETQP
is formed integrally with the source region or drain region 10 (or drain region or source region 10) of another adjacent MISFET Qp. M I 5FETQn
8. is a p-type well region provided on the main surface of semiconductor substrate 6 in a region surrounded by field insulating film 12; Gate insulating film, gate electrode9. It is composed of an n° type source region and drain region 11. The source region or drain region 11 of MI 5FETQn is connected to other adjacent MI
S F E T Q n It is configured in a negative body with the source region or drain region 11 (or the drain region or source region 11). In other words, the basic cell 5 can constitute a 4-input NAND gate circuit. A plurality of basic cells 5 are arranged in a column direction to form a basic cell column, and a plurality of basic cell columns are arranged in a row direction via wiring regions (wiring channels). The MISFETQ
A power supply voltage wiring Vcc extending in the direction of one column is on M
A reference voltage wiring Vss extending in one column direction is provided on the I5FETQn. Each of the power supply voltage wiring VcC1 and the reference voltage wiring Vss is formed, for example, in a first layer wiring formation process using an aluminum film.

As shown in FIG. 3 (block diagram), the ROM 4B includes a memory cell array 13, an address conversion circuit 14,
Decoder circuit 15. It is composed of an output circuit 16. Figure 4 (main logic circuit diagram of Figure 3) shows a specific 2wo
The configuration of a decoder circuit 15 for rd (word) and the arrangement of memory cells M are shown.

As shown in FIGS. 3 and 4, the decoder circuit 15
The 4-input NAND gate circuit 15a inputs the address signal of the address conversion circuit 14, and the output signal of the 4-input NAND gate circuit 15a is connected to the word line W. Alternatively, the inverter circuit 15b selects Wl.

It is composed of an inverter circuit 15c that inverts the output signal of the inverter circuit tab to select word line Wo or Wl. The word line W extends in the same direction (or in a direction perpendicular to) the extending direction of the basic cell row.

It is configured to extend over a memory cell array 13 made up of memory cells M.

The memory cell M consisting of the basic cell 5 is constructed as shown in FIG. 5 (equivalent circuit diagram) and FIG. 6 (reproduction diagram of FIG. 5).

As shown in FIGS. 5 and 6, the memory cell M includes four unit memory cells m Ip m 2 e ms and m4
It consists of Unit memory cell m is one MIS
It is composed of complementary MISFETs consisting of a FETQp and one MISFETQn, and has l[bit,] of information. Memory cell M is.

2w so that the word line does not limit the integration density.

rd(Wo l wo, wt, Wl)X2b i
It is composed of t(Do 1DI) and has 4 [bit] of information.

The unit memory cell mI is MISFETQP! The source region of is the power supply voltage wiring Vec, MISFE TQ n
The source region of I is the reference voltage wiring Vss, MISFET
The drain regions of QPt and Q n s are data lines. are connected to each other. And the unit memory cell m1 is
The gate electrode of MISFETQPt is connected to the word line wo, MI
The gate electrodes of SFETQns are respectively connected to the reference voltage wiring Vss, and as shown in FIG.
IT (or "'0") is written, that is, unit memory cell m.

, word line W0 is selected (set to low level)
and M I S F E T Q P + become conductive, and the power supply voltage Vcc becomes the data line. is read out.

In the unit memory cell m2, the source region of MISFET QP2 is connected to the 'N source voltage wiring Vcc, the source region of MISFET Q n 2 is connected to the reference voltage wiring Vss, and MISFET
The drain regions of Q P 2 and Q n 2 are connected to the data line D0, respectively. And unit memory cell m
2 is 1 The gate electrode of MISFET QP2 is connected to the power supply voltage line Vcc, and the gate electrode of MISFET Qn2 is connected to the word line W
The information 1101# (or '1
”) is not being written.In other words, in the unit memory cell m2, when the word line Wo is selected (set to high level), the M I S F E T Q n * becomes conductive, and the reference voltage Vss becomes the data. It is read out on line D0.

Similarly, the unit memory cell m3 has information on the data line.
1'' (or '''O'') is read out, and the unit memory cell m4 outputs the information '1' (or ''') to the data line D1.
0”) is read.

That is, the gate electrode of one MISFETQ of unit memory cell m is connected to the word line W, and the gate electrode of one MISFETQ of unit memory cell m is connected to the word line W.
Information is written by connecting the gate electrode of Q to the same fixed potential as the source region. Moreover, the unit memory cell m in which information has been written can read out information in a static manner in which when the word line W is selected, a potential representing information appears on the data line.

In this way, the basic cell 5 is comprised of complementary MI S FETs. In the semiconductor integrated circuit device II that adopts the master slice method, the first MISFET of the basic cell 5
(QP or Qn) source region at a first fixed potential (Vcc
or Vss), the second M I S FET (Qn or Qp
) to a second fixed potential (Vss or Vcc),
The drain regions of the first and second MI 5FETs are connected to the data line to form a memory cell, and the first MISFE
By connecting the gate electrode of T to the first fixed potential or the word line W and the gate electrode of the second MISFET to the word line W or the second fixed potential, respectively, to configure the information of the memory cell M of the ROM4B, the memory cell M Since this information can be read out using a static method, it is possible to achieve the same degree of integration as the dynamic method.

Also, multiple different? 1! The wiring of the position is ROM pro software 4
Since it can pass over B and there is no need for a detour, wiring efficiency is good and wiring design using CAD becomes easy.

In addition, by configuring the basic cell 5 with four complementary MISFETs that can configure a 4-input NAND gate circuit,
Since all MISFETs Qp and Qn in the basic cell 5 can be used, the memory cell M of the static type ROM 4B can be configured efficiently.

In addition, static type ROM4B does not have problems with the parasitic capacitance of the data line and operation timing compared to the dynamic type, so it is difficult to control the control circuit.

There is no need to provide a timing signal generation circuit, etc.

Peripheral circuits can be simplified.

Further, the static type ROM 4B does not require a precharge operation, and can further reduce power consumption.

As mentioned above, the memory cell M, that is, the basic cell 5, is composed of unit memory cells m1 to m4.

The number of information corresponding to the number of unit memory cells m, 4 [bit,
] is written. The information writing wiring pattern of the memory cell M is formed using CAD. Thereafter, information can be written in the mask ROM 4B by wiring the basic cell 5 in a wiring forming step using a mask (photoresist mask) formed with an information writing wiring pattern.

In each of FIG. 7 (schematic plan view of basic cell 5) and FIG. 8 (reproduction diagram of FIG. 7), 6 types of 16 types of memory cells M in which 4 bits of information are written are shown. Memory cell M
Indicates I=M s.

In FIGS. 7 and 8, basic cell 5 and basic cell 5
The wiring formed in between is performed in a two-layer wiring formation process (for example, a two-layer aluminum wiring formation process). word line W,
The power supply voltage wiring Vce and the reference voltage wiring Vss are formed in a first layer wiring formation process extending in one row direction and one column direction. The data line is formed in the process of forming a second layer of wiring extending in the direction of one row. Connections between each wiring, wiring and MI
Connections with SFETQp and Qx East are indicated by black circles (.).

In this way, the basic cells 5 constituting the memory cell M are prepared in advance.
By preparing unit wiring patterns corresponding to , combining these unit wiring patterns to form an information writing wiring pattern, and writing information to the basic cell 5 using this information writing wiring pattern, + Since it is no longer necessary to design a wiring pattern for every 1 [bit,], information can be written into the ROM 4B efficiently and in a short time.

Note that in the present invention, it is optimal to use the basic cell 5 that can configure a 4-input NAND gate circuit, but the ROM4B
The logic circuit 4A and RAM 4C other than the above are not necessarily limited to the basic cell 5 that can configure a 4-input NAND gate circuit, but may be configured with a basic cell that can configure a 2-input, 3-input/NAND gate circuit. , the present invention also provides 2
ROM is used as the basic cell that can configure the input NAND gate circuit.
4B memory cells M can be configured. In this case, four types of unit wiring patterns in which two pieces of information are written in the memory cells M are prepared in advance.

Further, according to the present invention, in a semiconductor integrated circuit device of a so-called gate filling type in which there is no wiring region between basic cell columns, the memory cells M of the ROM 4B may be configured in the basic cells arranged in a spreading manner.

Furthermore, the present invention provides a memory cell M of the ROM4B in a basic cell composed of an MI S FET having a smaller gate width (channel width) than an MI S FET of a basic cell constituting a logic circuit with a large driving capacity. may be configured.

Memory cell Mti--The basic cells that make up the memory cell Mti are as follows.

This is because the driving capacity may be small. Since the ROM 4B configured in this manner can reduce the area of the memory cell M, the degree of integration can be improved.

[Example ■]

Embodiment 2 is another embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device equipped with a RAM employing the master slice method.

FIG. 9 (equivalent circuit diagram) shows a memory cell constituting a RAM of a semiconductor integrated circuit device that employs the master slice method, which is Embodiment (2) of the present invention.

The memory cell M of the RAM of this embodiment (2) is the same as that of the above embodiment! 1 in 5 basic cells that can configure a 4-input NAND gate circuit
It is configured with information of [biL]. Memory cell M
is composed of transfer circuits 17a, 17b, and inverter circuits 17c and 17d. Transfer circuit 17b, inverter circuit 17c
and 17d constitute an information storage section (portion surrounded by a dotted line).

W and W are word lines, D is a data line, and D out is an information output line.

The RAM configured in this manner can obtain substantially the same effects as in the embodiment (2).

〔Effect of the invention〕

A brief explanation of the effects that can be obtained by one typical invention among the inventions disclosed in this application is as follows.

Complementary MISFET consisting of first and second MISFET
Configure the basic cell. In a semiconductor integrated circuit device adopting a master slice method, a first MI of the basic cell
The source region of the SFET is set to the first fixed potential, and the source region of the SFET is set to the first fixed potential.
The source region of T is set at a second fixed potential, the first and second MISF
A memory cell is configured by connecting the drain region of the ET to a data line.

By connecting the gate electrode of the first MISFET to the first fixed potential or the word line and the gate electrode of the second MISFET to the word line or the second fixed potential, respectively, to configure the information of the memory cell, the memory! Niru's information on Instagram
Since it is possible to read out data using a single-click method, there is no need to provide a timing generation circuit or the like, and one peripheral circuit can be simplified.

[Brief explanation of the drawing]

Figure 1 is an embodiment of the present invention! 1 is a schematic plan view of a semiconductor integrated circuit device that employs a master slice method. 2 is a plan view of essential parts of a basic cell configuring the semiconductor integrated circuit device shown in FIG. 1; FIG. 3 is a block diagram of a ROM configuring the semiconductor integrated circuit device shown in FIG. 1; This figure is a main part logic circuit diagram of FIG. 3, and FIG. 5 is an equivalent circuit diagram of the memory cell shown in FIG. 4. Figure 6 is a reproduction of Figure 5. FIG. 7 is a schematic plan view of the memory cell (basic cell) shown in FIG. 4. Figure 8 is a reproduction of Figure 7. FIG. 9 is an equivalent circuit diagram showing a memory cell constituting a RAM of a semiconductor integrated circuit device r employing a master slice method, which is Embodiment 2 of the present invention. In the figure, 1... semiconductor integrated circuit device, 2... external terminal. 3...7 input/output buffer circuits, 4A...logic circuit, 4
B... ROM, 4C... RAM, 5... Basic cell, 13... Memory cell array, 14... Address conversion circuit, 15... Decoder circuit, 16... Output circuit, Vcc. ...Power supply voltage wiring, Vss...Reference voltage wiring, QP e Qrs...MISFET, M
...Memory cell, m...Unit memory cell, W...
Word line, D...data line.

Claims (1)

[Claims] 1. Complementary MIS consisting of a first MISFET with a first conductivity type channel and a second MISFET with a second conductivity type channel
In a semiconductor integrated circuit device employing a master slicing method in which a basic cell is configured with FETs, the source region of a first MISFET of the basic cell is set to a first fixed potential and a second MISFET.
A memory cell is configured in which the source region of the SFET is connected to a second fixed potential different from the first fixed potential, and the drain regions of the first and second MISFETs are connected to a data line, and the gate electrode of the first MISFET of the memory cell is connected to the first fixed potential. A semiconductor integrated circuit device, characterized in that the second MISFET is connected to a potential or a word line, and a gate electrode of the second MISFET is connected to the word line or a second fixed potential to constitute information of a memory cell. 2. The semiconductor integrated circuit device according to claim 1, wherein the configuration of the information of the memory cell is performed in a wiring formation process. 3. The basic cell is a basic cell capable of configuring a 4-input NAND gate circuit composed of four complementary MISFETs.
2. The semiconductor integrated circuit device described in 2. 4. The memory cell constitutes a ROM in which a predetermined number of information is written in a basic cell consisting of a predetermined number of complementary MISFETs. each semiconductor integrated circuit device. 5. The information of the memory cell is prepared by preparing a plurality of unit wiring patterns for writing a predetermined number of information, and combining these unit wiring patterns to form an information writing wiring pattern. 5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is constructed by wiring basic cells in a wiring forming step using a wiring pattern.