JPS6344205B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic focus detection device for a camera that automatically performs focus detection using changes in the contrast of a subject image.

An optical image of a subject formed by a lens has a property that the difference between brightness and darkness of the image, that is, the contrast, becomes maximum when the focus is adjusted (hereinafter referred to as focusing). This is a phenomenon that occurs because the light intensity (power spectrum) at each spatial frequency of the subject image reaches its maximum at the time of focus, and if this phenomenon is captured, the focus can be automatically detected.

Conventionally, methods for extracting such contrast information itself include methods using non-linear photoconductive elements such as CdS, or lining up a large number of minute photoelectric elements on the image plane, and then detecting a pair of adjacent elements among them. A method of statically detecting the difference in photoelectric output between
A self-scanning photoelectric device consisting of a single row photoelectric device group consisting of a plurality of microscopic photoelectric devices and a scanning circuit corresponding to this photoelectric device group, as disclosed in Japanese Patent Laid-Open No. 55-35317, etc. A method of dynamically obtaining a contrast signal from the photoelectric output of a microphotoelectric element using a converter has been proposed.

Further, as a method of detecting the in-focus state using the contrast detection element as described above, for example, contrast detection is disclosed in Japanese Patent Application Laid-open No. 55-29832 and Utility Model Application No. 53-95830. There is a method of arranging the element at a position equivalent to the imaging plane and detecting the state in which the contrast signal shows the maximum value, or a method of detecting the state in which the contrast signal shows the maximum value, or a method of detecting the state where the contrast signal shows the maximum value, or a method of detecting the state where the contrast signal shows the maximum value, or a method of detecting the state where the contrast signal shows the maximum value, or a method of detecting the state where the contrast signal shows the maximum value, There is a method of arranging two contrast detection elements at two positions equidistant from each other and detecting a state in which the contrast signal outputs from both contrast detection elements are equal. A method is known in which a surface equivalent to the imaging surface is mechanically vibrated back and forth and the state of change in contrast output within the vibration period is analyzed.

These automatic focus detection methods that utilize contrast information of a subject image are suitable for being incorporated into an automatic focus detection device of a single-lens reflex camera as a so-called TTL focus detection device.

By the way, high-end cameras such as single-lens reflex cameras have interchangeable lenses, so the range of subject distances that can be photographed is wide, and the use of high-performance lenses allows for sharp images to be obtained, as well as a wider range of subject brightness that can be photographed. is wide.

Therefore, in order to apply an automatic focus detection device to a single-lens reflex camera such as the one described above, a number of strict conditions must be satisfied. Firstly, the focus detection accuracy is high, secondly, it can be applied to a wide range of subject brightness, thirdly, it can be used even in the presence of camera shake or to moving subjects, and fourthly, it can be used in various ways. It is required to be applicable to interchangeable lenses. However, none of the above-mentioned conventional devices or methods could necessarily satisfy these conditions. In particular, it is equipped with a photoelectric element array consisting of a plurality of microphotoelectric elements and a scanning circuit corresponding to the photoelectric element array, which are arranged at two equidistant positions before and after a position equivalent to the imaging surface of the lens system. Two sets of self-scanning photoelectric conversion units that output time-series photoelectric conversion signals corresponding to the illuminance distribution of an image, and two arbitrary microphotoelectric elements with a constant interval in each of the self-scanning photoelectric conversion units. a contrast detection circuit that outputs the peak value of the photoelectric output difference within a certain period as a contrast signal in time series in accordance with the amount of extension of the lens system; In an automatic focus detection device of a camera configured to compare and output a focus display instruction signal, if the focus effective range limit level is fixed, a false focus instruction signal will be generated when the contrast of the subject is high. There is a problem that it is determined that the camera is in focus even though it is not in the proper focus state.

In order to solve this problem, it is possible to increase the focus effective range restriction level, but simply increasing the focus effective range restriction level does not allow focus detection for low contrast subjects. This causes the inconvenience that it cannot be performed with high precision.

Therefore, in order to solve these contradictory problems, the present invention proposes a photoelectric element array consisting of a plurality of microphotoelectric elements arranged at two equidistant positions before and after a position equivalent to the imaging surface of the lens system. and two sets of self-scanning photoelectric conversion units each including a scanning circuit corresponding to the photoelectric element array and outputting a time-series photoelectric conversion signal corresponding to the illuminance distribution of the subject image; a contrast detection circuit that outputs the peak value of the photoelectric output difference within one scanning period between arbitrary two minute photoelectric elements spaced apart as a contrast signal in time series in accordance with the amount of extension of the lens system; and a focus effective range determination circuit that compares the levels of the two contrast signals with a predetermined effective range limit level proportional to the peak value of the time-series photoelectric conversion signal, It is an object of the present invention to solve the above problem by outputting a focus instruction signal obtained from the two contrast signals when the signal levels are simultaneously higher than the effective range limit level.

The present invention will be explained below based on the drawings.

FIG. 1 is a diagram showing an embodiment in which the present invention is applied to a single-lens reflex camera 1. As shown in FIG.

In the figure, 2 is a lens system, 3 is a half mirror, and 4 is a total reflection mirror.
The self-scanning photoelectric conversion unit 5 in the automatic focus detection device U according to the present invention is arranged on the optical path of the reflected light.

Reference numeral 6 denotes a light emitting diode for displaying the focusing state, which will be described later. Three of them (6a, 6b, and 6c, which will be described later) are arranged in a direction perpendicular to the plane of the figure, and there is a confirmation window (not shown) behind the camera 1. ) is provided.

Reference numeral 7 is a film, 8 is a focus plate, 9 is a condenser lens, 10 is a pentaprism, and 11 is an eyepiece lens. When exposing the film 7, the half mirror 3 and the total reflection mirror 4 are moved out of the optical path by a mirror moving mechanism (not shown).

FIG. 2 shows a general contrast distribution of a subject image in the above camera.

The contrast value of the image of the subject 12 formed by the lens system 2 shows a unimodal distribution with a maximum value at the in-focus position. Focus detection methods using contrast information are roughly divided into two types depending on whether the property that this distribution shows a peak or the property that the peak is symmetrical on the left and right sides is used. Of these, the present invention relates to the latter method.

Next, FIG. 3 shows an example of the overall configuration of the camera automatic focus detection device U shown in FIG. 1.

A video circuit U ₂ , a contrast detection circuit U ₃ , a focus determination circuit U ₄ , and a display drive circuit U 5 are successively connected to the light receiving unit U ₁ including the self-scanning photoelectric conversion unit ₅ , Further, the output line of the display drive circuit _U5 is divided into two parts, one of which is connected to the focus display element composed of the light emitting diode 6, and the other to the lens drive device _U6 . The level drive device _U6 is composed of a lens drive motor and the like.

When the subject image formed by the lens system 2 enters the self-scanning photoelectric conversion unit 5, the self-scanning photoelectric conversion unit 5 is driven and photoelectrically converted by the video circuit _U2 , and the subject image is A time-series photoelectric conversion signal (hereinafter referred to as video output) corresponding to the illuminance distribution of the image is output. From the video output, the contrast detection circuit U ₃ extracts the contrast values of the respective subject images on both image sensors (described later) in the photoelectric conversion section 5 as a contrast signal. From the contrast signal output, a focus determination circuit U ₄ obtains a focus instruction signal indicating the in-focus state, and based on the focus instruction signal, the blinking control of the focus display element 6 is performed via the display drive circuit U ₅ . The amount of extension of the lens system 2 is controlled by the lens driving device _U6 .

Hereinafter, each component circuit etc. in FIG. 3 will be explained in more detail.

First, FIGS. 4 and 5 show an example of the configuration of the light receiving section _U1 .

In the light receiving section _U1 , a sensor package 14, a light splitter 16, and an infrared cut filter 17 are sequentially stacked from the bottom in the figure.

The sensor package 14 includes two sets of self-scanning photoelectric conversion units 5a and 5b as described below.
and monitor sensors M _A and M _B (hereinafter referred to as
A sensor IC chip 15 in which M _A is called an A monitor sensor and M _B is called a B monitor sensor is installed.

In addition, the two sets of self-scanning photoelectric conversion units 5a, 5
b are photoelectric element arrays S _A and S _B each consisting of a plurality of micro photoelectric elements (hereinafter S _A is referred to as A image sensor, S _B
(referred to as a B image sensor), and scanning circuits SR ₁ and SR ₂ consisting of shift registers for scanning and driving the image sensors S _A and _SB , respectively.

Specifically, the image sensors S _A and S _B are
CCD (Charge Coupled Device), BBD (Bucket
Brigade Device), MOS-FET, etc. can be applied. In addition to the photoelectric conversion function, all of these have a signal charge accumulation function that allows each unit cell to accumulate signal charges generated by photoelectric conversion.

In this invention, we will continue to explain the case where the MOS-FET type is applied. Note that a mask sensor to which a light blocking mask is attached is disposed at one end of each of the image sensors S _A and _SB , as will be described later.

Furthermore, the monitor sensors M _A and _MB are formed of photoelectric elements and are for detecting average illuminance, and are preferably arranged as close as possible to the corresponding image sensors S _A and _SB . In the example shown in the figure, two image sensors are provided, one each for each image sensor S _A and S _B , but it is not necessarily necessary to provide two image sensors, and only one image sensor is provided. may be provided and shared by both image sensors S _A and _SB . However, the light intensity on the A image sensor S _A and the light intensity on the B image sensor S _B may differ, so in preparation for such a case,
The monitoring function can be performed more effectively by disposing two monitor sensors M _A and M _B as shown in the figure.

Incidentally, the charge accumulation time of each image sensor S _A and _SB is configured to be inversely proportional to the amount of light incident on the monitor sensors M _A and _MB .

Next, the light splitter 16 includes an A image sensor S _A
A half mirror 16a corresponding to the B image sensor S _B and a total reflection mirror 16b corresponding to the B image sensor S B are incorporated, and as shown in FIG.
The light that has passed through is incident on the A image sensor S _A and the A monitor sensor M _A , and then the half mirror 16a
The light reflected by B is reflected again by the total reflection mirror 16b.
The light enters the image sensor S _A and the B monitor sensor M _B. With this configuration, the A image sensor S _A and the B image sensor S _B are equivalent to being placed a certain distance apart on the optical axis, and the entire light receiving section U ₁ is placed at a predetermined position. By doing so, the A and B image sensors S _A and S _B can be positioned at two positions before and after the film equivalent surface (a surface equivalent to the imaging surface of the lens system 2) and equidistant from each other.

The infrared cut filter 17 is connected to both image sensors.
It is intended to block unnecessary infrared light when the spectral sensitivities of S _A , _SB and monitor sensors M _A , _MB extend into the infrared region, and their installation is not essential.

FIG. 6 and FIGS. 7A and 7B are conceptual diagrams showing the principle of focus detection by the self-scanning photoelectric conversion units 5a and 5b arranged as described above. Since the A image sensor S _A and the B image sensor S _B are placed equidistantly in front and behind the film equivalent surface, both image sensors S _A and S _B have images that are a certain distance apart on the optical axis. They will be incident on each. If the contrast distribution of the subject image is symmetrical, as shown in FIG. 7A, each image sensor S _A ,
When the contrast values on S _B become equal, the equivalent surface of the film and the focal position coincide. Figure 7B
As shown in , if the film equivalent surface and the in-focus position do not match, a difference ΔC occurs between the respective contrast values. Therefore, both image sensors S _A ,
Focus detection can be performed by detecting whether the contrast values on S _B match or do not match.

Next, the video circuit _U2 will be explained.

The video circuit U ₂ drives the above-mentioned self-scanning photoelectric converter 5 to obtain a video output corresponding to the illuminance distribution of the subject image. The conversion unit 5 is also shown,
In this context the video circuit _U2 will be described.

First, FIG. 8 shows the principle using a block diagram.

The video circuit U ₂ includes a start pulse generation circuit 18, an image sensor drive circuit 19, a clock pulse generation circuit 20, and an amplifier 21.

The photocurrents output from the monitor sensors M _A and _MB are input to the start pulse generation circuit 18, and a pulse train signal having a frequency proportional to the brightness on the monitor sensors M _A and _MB is generated. This pulse train signal and the clock pulse generated by the clock pulse generation circuit 20 are input to the image sensor drive circuit 19, and drive pulses for scanning the image sensors S _A and _SB are generated. On the other hand, image sensor
The output signals of S _A and _SB are amplified by an amplifier 21 and a video signal is outputted to an output terminal 22 .

Here, since the image sensors S _A and _SB are charge accumulation type as described above, the dynamic range of their photoelectric characteristics can be widened by changing the charge accumulation time. FIG. 9 schematically shows the photoelectric characteristics of each of the image sensors S _A and _SB . For charge accumulation times T ₁ , T ₂ , and T ₃ , the photoelectric characteristics are distributed as shown in distributions 23a, 23b, and 23.
It changes like c. The charge accumulation time is T ₁ <
The relationship is T ₂ < T ₃ . For example, if the charge accumulation time is fixed at T ₂ , the dynamic range in which the photoelectric characteristics do not saturate is expressed as d, but if the accumulation time changes from T ₁ to T ₃ , the dynamic range becomes d′. It spreads like that. Therefore, by changing the charge accumulation time according to the brightness of the subject image, the dynamic characteristics of the photoelectric characteristics can be expanded as a result. Furthermore, if the charge accumulation time changes in inverse proportion to the average brightness of the subject image, even if the average brightness of the subject changes, the time-series photoelectric charges read out from each image sensor S _A , S _B The output, in other words, the video output output from the output end 22 does not change, and as a result, the contrast output described below remains unchanged.

Next, FIG. 10 shows a specific circuit example of the start pulse generation circuit 18 and the image sensor drive circuit 19.

In the start pulse generation circuit 18, the symbol M is a monitor sensor diode, and the monitor sensor
Shown as a representative of M _A or M _B. 25 again
is a constant current source, 26 is a comparator, and _S1 is an analog switch.

On the other hand, the symbol FF ₁ in the image sensor drive circuit 19 indicates a D flip-flop circuit 24a, 24
b, 24c are inverters, 27 is an AND gate,
28 is an 8-bit binary counter, 29 to 31 are OR gates, and 32 to 34 are NOR gates.

A photoelectric conversion signal is extracted from the monitor sensor diode M using the charge accumulation mode in the same way as the image sensors S _A and _SB . That is, the charge generated in the monitor sensor diode M is accumulated due to the capacitance of the internal or external output line of the diode M, and the first charge is generated at the anode terminal of the diode M.
A voltage Vm as shown in Figure 1 is generated. this voltage
A comparator 26 compares Vm and a threshold voltage Mt generated at the terminal of the resistor R ₁ by the constant current source 25 . The output _M0 of the comparator 26 becomes a high level when Vm matches Mt, and when the Q terminal output of the D flip-flop _FF1 is at a high level, the output of the AND gate 27 becomes a high level and the output of the D flip-flop _FF1 becomes a high level. Reset. At this time, the Q terminal of the D flip-flop _FF1 becomes low level, the reset of the D flip-flop _FF1 is released, and the reset of the 8-bit binary counter 28 is also released, and the counter operation starts.
A series of digital waveforms are output from the 8-bit binary counter 28 to terminals φ ₁ to φ 1 in accordance with the clock pulses generated by the clock pulse generation circuit 20.
Output to _φ8 . From the signals output to the terminals φ ₃ to _{φ 7} , the A image sensor is
S _A start pulse A _S and B image sensor
A start pulse Bs for S _B is generated. The start pulse As is input to the control terminal of the analog switch _S1 , resets the output of the monitor sensor diode M to the Vs level, and returns to the initial state of charge accumulation. The signal output to terminal _φ8 is
D flip-flop via inverter 24a
It is input to the clock terminal C of FF ₁ , makes the output of D flip-flop FF ₁ high again, waits until the moment when the output of the monitor sensor diode matches Mt, and outputs the output from the A image sensor S _A and the B image sensor. This becomes a signal input to the sensor IC chip 15 in order to combine the output of S _B. Scanning pulses φ A and φ _B for scanning the A and B image sensors S _{A and SB} are generated from the signals outputted to the terminals φ ₁ and φ ₂ by the OR gates 30 and 31 and the inverter 24c. Terminal φ ₁
A video reset pulse φ _R for resetting the photoelectric output of each bit of the A and B image sensors S _A and S _B is generated from the signal output from the D flip-flop FF ₁ and the output signal from the D flip-flop FF 1 .

As mentioned above, the start pulse As for driving the A image sensor S _A is generated from the pulse signal of the output M ₀ of the comparator 26, and the A image sensor S _A is scanned by the scanning pulses φ _A and φ _B according to the clock pulse. After the scanning is completed, the B image sensor S _B is scanned in the same manner. The charge accumulation time is the start pulse As,
It is determined by the interval of Bs. If you do this, the video output will look like the bottom row of Figure 11,
Since the interval between each bit of the video output is always the same even if the charge accumulation time is different, the configuration of the photoelectric output extraction circuit in the subsequent stage can be simplified.

Next, FIG. 12 further shows the connection relationship between the video circuit _U2 from which the output terminals of each signal are derived as described above and the sensor IC chip 15.

A known noise compensation diode (not shown) may be incorporated within sensor IC chip 15 to remove noise from the video output and make focus detection more accurate.

Next, FIG. 13 shows an example of an electric circuit of the image sensor S _A and S _B section, and the video circuit U ₂
This figure more specifically shows the connection relationship with each output terminal derived from . Code 35a~ in the figure
35n, 35a'-35n', 36a, 36b, 37
A and 37b are FET gates, respectively, and 24a is an inverter.

Then, the start pulse As and the scanning pulse φ _A ,
φ _B is input to A shift register SR ₁ , and turns on FET gates 35a, 35b to 35n sequentially,
The charges accumulated in each microscopic photoelectric element (hereinafter also simply referred to as a bit) of the image sensor S _A are sequentially taken out to the output line 38a. Similarly, the start pulse Bs and scanning pulses φ _A and φ _B are in the B shift register.
Input to SR ₁ , FET gates 35a', 35b' to 3
5n', the charges accumulated in each bit of the B image sensor S _B are taken out to the output line 35b. The outputs of these A and B image sensors S _A and S _B are fed to the FET gate 3 controlled by the signal _φ8 .
7a, 37b and an inverter 24d, and output as one time-series photoelectric output Vi. Since the output of this image sensor is taken out as a charging voltage charged to the internal junction capacitance of the micro photoelectric element (photodiode) or the video line capacitance of the external output line, each bit is controlled by the signal φ _R. FET gate 36
By resetting using a and 36b, the initial state is returned.

FIG. 14 shows a timing chart of the scanning pulses φ _A and φ _B , the reset pulse φ _R , and the time-series photoelectric output Vi.

The photoelectric output detected in this manner is amplified by the amplifier 21 in the video circuit U ₂ to become a video output video, which is input to the subsequent processing circuit.

Next, FIG. 15 shows an example of the circuit configuration of the contrast detection circuit _U3 . This contrast detection circuit _U3 is designed to convert the difference in photoelectric output between any two bits at a constant interval between the image sensors S _A and S _B , for example between every other two bits, into a contrast output. It is.

In FIG. 15, numerals 40 to 43 are first to fourth sample and hold circuits, 44 and 45 are first,
a second differential circuit, 46 a first switch circuit, 47
48 is an absolute value circuit, 48 is a second switch circuit, 49 is an A peak value detection circuit, and 50 is a B peak value detection circuit.

The video output input to terminal 39 is
Fourth four sample hold circuits 40, 41,
42 and 43 at the same time. The first sample and hold circuit 40 has a sample pulse set so as to hold the output of every 4 bits of the discrete video output, as shown in FIG. 17a. In the second sample and hold circuit 41, a sample pulse is set with a delay of one bit from the sample pulse of the first sample and hold circuit 40, and the output of every 4 bits is similarly held.

Similarly, the sample pulse is set in the third sample and hold circuit 42 and the fourth sample and hold circuit 43 with a delay of 1 bit from the second sample and hold circuit 41, respectively, and both of them are set with a delay of 1 bit from the second sample and hold circuit 41. Bit by bit output is retained.

A first differential circuit 44 extracts the difference between the signals output from the first sample and hold circuit 40 and the third sample and hold circuit 42 . Similarly, the difference between the signals output from the second sample and hold circuit 41 and the fourth sample and hold circuit 43 is extracted by the second differential circuit 45. The output signals of the first and second differential circuits 44 and 45 are switched by a first switch circuit 46 for each bit of the image sensor and converted into one time-series photoelectric output signal. This combined difference signal is converted by the absolute value circuit 47 into a positive or negative absolute value signal. Next, the second switch circuit 48
, the absolute value signal is A image sensor
It is divided into the S _A part and the B image sensor S _B part. The respective absolute value signals are input to the A peak value detection circuit 49 and the B peak value detection circuit 50, the peak value within one scanning period of each absolute value waveform is detected, and the peak value is detected at the start of the next scanning period. is retained until

These peak value signals represent contrast signals of the subject image, and the contrast signal of the A image sensor S _A is output to a terminal 51 and the contrast signal of the B image sensor S _B is output to a terminal 52. below,
The respective contrast signals are referred to as an A contrast signal C _A and a B contrast signal C _B.

FIG. 16 shows a more specific circuit example of the circuit configuration diagram of FIG. 15. In the figure, S ₂ to _{S 11} are analog switches, and C ₁ to _{C 6} are capacitors. Figures 17a-h show how the video output is processed.

FIG. 18 is a timing chart showing the control pulses of the analog switches S ₂ to _{S 11} used in the circuit of FIG. 16 and the timing Sc of the video outputs of the image sensors S _A and _SB . The video output input to terminal 39 is analog switch S ₂ , S ₃ , S ₄ , S ₅
are simultaneously input to capacitors C ₁ , C ₂ , C ₃ , C ₄
Therefore, it is converted into a sample and hold signal. In order to control the respective analog switches S ₂ , S ₃ , S ₄ , S ₅ , a sample pulse P ₁ is connected to the terminal 53.
A sample pulse P ₂ is input to the terminal 54, a sample pulse P ₃ is input to the terminal 55, and a sample pulse P ₄ is input to the terminal 56 at the timing shown in FIG. The signals sampled and held using the analog switch _S2 and the analog switch _S4 are sent to an operational amplifier 57 which becomes a buffer amplifier.
The signal is inputted to the operational amplifier 44a, which serves as a differential amplifier, via a and 57c, and the differential output between the two is extracted. Similarly, the signals sampled and held using analog switch _S3 and analog switch S5 are input to operational amplifier _45a , which serves as a differential amplifier, via operational amplifiers 57b and 57d, and the differential output between the two is inputted to operational amplifier 45a, which serves as a differential amplifier. Extracted. The output of the operational amplifier 57a is the 17th
As shown in FIG. b, similarly, the operational amplifier 57b,
The outputs of 57c and 57d are shown in Fig. 17c and 57d, respectively.
It will look like d and e. Figure 17a represents the video output. The output of the operational amplifier 44a is the 17th
The output of the operational amplifier 45a is as shown in FIG. 17g, and the output of the operational amplifier 45a is as shown in FIG. These two differential outputs are alternately switched bit by bit by analog switches S ₆ and S ₇ to which control pulses P ₅ and P ₆ are input to terminals 58 and 59, respectively, and converted into one time series signal. be synthesized. The combined differential output is converted into a positive absolute value signal by the operational amplifier 47a and diodes D ₁ and D ₂ . The absolute value signal converted in this way is as shown in FIG. 17h, which is the extracted absolute value of the signal in the shaded areas in FIGS. 17f and g. This absolute value signal exactly corresponds to the photoelectric output difference between every other two bits of the video output. Next, the absolute value signal is transmitted to the operational amplifier 4.
After being amplified by 7b, the signal is simultaneously input to two analog switches S ₈ and S ₉ . analog switch
The terminal 60 of _S8 receives a control pulse _P7 as shown in FIG.
is input, and the peak value of the absolute value signal within one scanning period of the portion of the A image sensor S _A is held by the operational amplifier 49a, the diode _D3 , and the capacitor _C5 . Similarly, the control pulse _P8 is input to the terminal 61 of the analog switch _S9 , and the operational amplifier 5
By 0a, diode D ₄ and capacitor C ₆ ,
The peak value of the B image sensor S _B portion is held. Analog switches S ₁₀ and S ₁₁ are connected to terminals 62 and 6.
By inputting the control pulse _P8 to 3,
It is provided to discharge the charges of capacitors _C5 and _C6 every scanning period. Those peak values are calculated by the operational amplifiers 49b and 50 which serve as buffer amplifiers.
b, the A contrast signal is output to the terminal 51 and the B contrast signal is output to the terminal 52.

Then, Fig. 19A, B, Fig. 20 and Fig. 21
Figures A and B are diagrams for explaining the characteristics of the contrast signal. The subject image is distributed when focusing 6
If the illuminance distribution is as shown in 5a, the illuminance distribution will be as shown in distribution 65b when out of focus. Here, the horizontal axis is the moving distance l in the plane perpendicular to the optical axis.
It is. When these illuminance distributions are incident on each bit S _A1 to S _A7 of an image sensor having a light receiving aperture with vertical and horizontal lengths of y and w and a pitch of p, each bit receives light within an area of w x y. is received and converted into a photoelectric output, and the photoelectric output difference between two bits with an interval of 2p is detected. The solid line 66a is the distribution 65a
The dotted line 67a shows the distribution of the photoelectric output difference corresponding to the distribution 65b. The peak values of the distribution of these photoelectric output differences become contrast signals 66b and 67b, and as the subject image goes out of focus, the contrast signals decrease.

Now, in the bit string of image sensor S _A , the 20th
As shown in the figure, an edge chart 68 with bright and dark areas is projected.
moves horizontally at a speed v, if the method detects the photoelectric output difference between adjacent bits, the second
As shown in FIG. 1A, when the edge portion of the edge chart image 68a enters the aperture of each bit in the image sensor, the contrast signal decreases. This means that the contrast signal changes depending on the movement of the subject or the presence of camera shake.
Accurate focus detection cannot be performed. On the other hand, if the above-mentioned method detects the photoelectric output difference every other bit, as shown in FIG. Therefore, highly accurate focus detection can be performed. Figure 21A,
The horizontal axis of B is the time corresponding to the amount of movement of the edge portion of the edge portion of the image 68a.

Next, a method for detecting the in-focus state from the A contrast signal and the B contrast signal will be described with reference to FIGS. 22A and 25B. As shown in Figure 22, the image of Ezdziyat 68 is
If the illuminance is I ₁ for the bright area and I ₂ for the dark area, and the difference in illuminance is ΔI, the photoelectric outputs V ₁ and V ₂ for these are proportional to the illuminance I ₁ and I _2, respectively. do. Therefore, their photoelectric output difference ΔV=V ₁ −
V ₂ =K·ΔI=k(I ₁ −I ₂ ). Here, k is a proportionality constant. As shown in FIG. 23, when the subject image is divided into two by the light splitter 16, light with energy E is transmitted to image sensor S _A as τaE,
On the B image sensor, it becomes τbE. τa and τb are 2
is the transmittance of the light splitter 16 for two optical paths.
If the transmittances τa and τb of these two optical paths are different,
As shown in Figure 24 A and C, A image sensor
When Etzjiat 68 is imaged on S _A ,
The photoelectric output difference ΔVa is ΔVa=V ₁ a−V ₂ a=k・τa・ΔI
=k·τa(I ₁ −I ₂ ). On the other hand, Fig. 24B,
As shown in D, when the edge chart 68 is imaged on the B image sensor S _B , the photoelectric output difference ΔVb is ΔVb=V ₁ b−V ₂ b=k・τb・ΔI=k・τb
(I ₁ − I ₂ ). If the video output is as shown in Fig. 24C and D, the photoelectric output difference signal at the in-focus position will be as shown in Fig. 24E, and the peak value of the AB image sensor S _A and S _B section will be Certain A contrast signals and B contrast signals do not match, and the ratio of these contrast signals is τa/τb. The AB contrast signal with respect to the lens extension _amount le becomes as shown in _FIG . The film equivalent plane 72 is brought into focus. However, as shown in FIG. 24E, the value of the A contrast signal when the image is formed on the A image sensor S _A (position 73) and the value of the B image sensor S _B
If the values of the B contrast signal are different when the image is formed at (position 73'), for example, the distribution of the A contrast signal will be like C _A ', and the intersection of these distributions will be at position 74, and the focus will be It deviates from position 71.

Therefore, in order to perform accurate focus detection, A
It is necessary that both the contrast signal distribution C _A and the B contrast signal distribution C _B be symmetrical. To this end, as one of the methods to solve the problem caused by the imbalance in transmittance of the light splitter 16, it is necessary to separate the photoelectric conversion outputs of the A image sensor S _A and the B image sensor S _B. Both video outputs may be balanced by inputting amplifiers and adjusting the gains of those amplifiers appropriately.

In this embodiment, focusing on making the contrast signal proportional to τa or τb, A
By amplifying or attenuating either the contrast signal or the B contrast signal, a mutually symmetric AB contrast signal distribution is obtained and the problem of imbalance in transmittance is solved.

For example, the photoelectric output difference ΔVa of A image sensor
If it is amplified or attenuated so that ΔVa'=ΔVa·(τb/τa), the AB contrast signal distribution becomes symmetrical.

Next, the focus determination circuit _U4 will be explained. This circuit _U4 obtains each focus instruction signal indicating a focus position, a front focus state, a back focus state, and a state indicating that focus cannot be detected from the contrast signal C _A and the B contrast C _B.

First, FIG. 26 shows an example of the basic configuration of the focus determination circuit _U4 .

In the figure, reference numeral 75 indicates an A contrast signal.
76 is an input terminal for _B contrast signal C _B , 77 is a contrast compensation circuit, 78 is a focus detection circuit, 79 is a direction detection circuit, 80
is not possible (hereinafter referred to as NG) detection circuit, 81 is a focus effective range determination circuit, 82 is a focus state determination circuit, 83 is an output terminal for a front pin instruction signal, 84
85 is a focus instruction signal output terminal, and 85 is a rear focus instruction signal output terminal.

The A contrast signal C _A input to the terminal 75 and the B contrast signal C _B input to the terminal 76 are input to the contrast compensation circuit 77.
The contrast signals are adjusted so as to have a mutually symmetrical contrast signal distribution, and are input to the focus detection circuit 78 and the focus effective range determination circuit 81. The focus detecting circuit 78 sends a signal indicating the in-focus position, the direction detecting circuit 79 sends a signal indicating the state of front focus and back focus, and the NG detecting circuit 80 sends a signal indicating that the focus cannot be detected to the focus effective range determination circuit. It is input to the focus state determination circuit 82 together with the output signal of terminal 81 and subjected to logic processing.
A front focus instruction signal is output to a terminal 84, a focus instruction signal is output to a terminal 84, and a rear focus instruction signal is output to a terminal 85. The focus detection failure instruction signal is sent to terminals 83 and 85.
are output simultaneously.

The contrast compensation circuit 77 corrects the imbalance in the A and B contrast signal distributions caused by the imbalance in transmittance of the light splitter 16 as described above.
The output of either the A contrast signal C _A or the B contrast signal C _B , or both, is amplified or attenuated. As this contrast compensation circuit 77, for example, a circuit as shown in FIG. 27 is applied. When the A or B contrast signal is input to the terminal 86, the values of the resistors R ₁₉ , R ₂₀ , and R ₂₁ are appropriately selected in advance, and the width is increased to the terminal 87 by adjusting the variable resistor R ₂₂ . Or an attenuated contrast signal is obtained. By matching this amplification factor or attenuation factor to the ratio of the transmittance of the light splitter 16, balanced contrast signals of both A and B can be obtained.

Here, the principle of determining the in-focus state by the focus determining circuit _U4 will be explained using FIGS. 28A, B, and C. As shown in Figure 28A, A contrast signal C _A distribution and B
There is a contrast signal C _B distribution, and the intersection point 71 of these is the correct focus position. However, these contrast signals C _A or C _B have been corrected by the contrast compensation circuit 77 as described above.
A focus effective range limit level 88 is set, and only when both contrast signals C _A and C _B are higher than this level 88, output of the focus instruction signal is permitted. The difference between both contrast signals C _A and C _B is taken as shown in FIG. 28B, and this difference signal
When C _D (=C _A −C _B ) is positive, a signal representing the front pin state 83a is output, and when it is negative, a signal representing the rear pin state 85a is output. Then, as shown in FIG. 28C, the difference signal
When the absolute value of C _D |C _D |=C _E is smaller than the focus detection threshold level 89 and is within the effective range of the focus display, there is a focus display area 84a, and the focus instruction signal is is output. Also, if the absolute value C _E is not in the focus display effective range and is smaller than the NG level 90, the NG display ranges 90a and 90b
, and a focus detection failure instruction signal is output. These in-focus display area 84a and NG display area 90a, 9
In areas other than 0b, the front pin and rear pin instruction signals are output in the front pin display area 83b and the rear pin display area 85b, respectively. This in-focus display area 84a is the contrast difference signal C _D in FIG. 28B.
corresponds to a portion sandwiched between both threshold levels 83a and 85a, and a focus instruction signal is output even in a portion slightly deviated from the accurate focus position 71.
For practical purposes, the focus display area 84a can be made narrow enough to be considered to be in focus.

By providing the focus display area 84a with a certain width in this manner, stable focus display can be performed during actual photographing.

Even if the A contrast signal C _A distribution and the B contrast signal C _B distribution increase or decrease while maintaining balance, the position of their intersection 71 (focus point) remains unchanged.

This means that accurate focus detection can be performed regardless of the contrast level of the subject. This effect is an advantage of the method using two sets of self-scanning photoelectric conversion sections sandwiching the film equivalent surface.

However, as described above, when setting the focus display area 84a with a width near the focus position, if the focus detection threshold level 89 is fixed, the focus A problem arises in that the width of the focus display area 84a changes.
For example, as shown in FIG. 29, the contrast of the subject changes and the video output changes from distribution 91 to distribution 9.
2, the photoelectric output difference 91a changes to a photoelectric output difference 92a. At this time, the absolute value of the difference between the AB contrast signals C _A and C _B decreases from the distribution C _E to the distribution C _F in FIG. 30. If the focus detection threshold level 89 is fixed as shown in the figure, the focus display area 84e for the distribution C _E is
Further, a focused display area 84f is obtained for the distribution C _F. That is, as the contrast of the subject decreases, the width of the in-focus display area 84f increases.

With such a method, focusing accuracy deteriorates for subjects with low contrast, and the in-focus display state becomes unstable near the in-focus position.

In order to eliminate the above-mentioned drawbacks, in this embodiment, the focus detection threshold level 89 is set to a level proportional to the sum of the A and B contrast signals, thereby creating a focus display area that does not depend on the contrast of the subject. It has gained. FIG. 31A shows the distribution of AB contrast signals C _A , _CB , and FIG. 31D shows a contrast signal distribution C _A ′, _CB ′ that is lower than that in FIG. 31A. Figure 31B is the sum of the AB contrast signals C _A and C _B in Figure 31A, C _A
Similarly, Figure _31E shows the third
It shows the sum of the AB contrast signals C _A ′ and C _B ′ in FIG. 1D. Values proportional to these sums are set as focus detection threshold levels 89a and 89b, respectively, as shown in FIG. 31C and F. In this way, the focus display areas 84a and 84a' have almost the same width, and accurate and stable focus detection can be performed regardless of the contrast of the object.

Next, FIG. 32 is a block diagram showing a more detailed configuration example of the focus determination circuit _U4 shown in FIG. 26.

That is, the focus determination circuit 78
0, addition circuit 91, absolute value circuit 92, attenuation circuit 9
3 and a comparison circuit 94.

Further, the NG detection circuit 80 includes an NG level generation circuit 95 and a comparison circuit 96, and the focus effective range determination circuit 81 further includes a focus effective range limit level generation circuit 97 and a comparison circuit 98.

Then, the A contrast signal C _A inputted to the terminal 75 is sent to B by the contrast compensation circuit 77.
It is corrected to maintain balance with the contrast signal C _B , and is input to the differential circuit 90 together with this B contrast signal C _B , and the difference between the corrected A contrast signal C _A1 and B contrast signal C _B is detected. A direction detection circuit 79 extracts a signal indicating the state of the front pin and rear pin from the differential output.
The difference output is simultaneously input to the absolute value circuit 92, and a signal corresponding to the absolute value of the difference between the AB contrast signals is output.

On the other hand, the corrected A contrast signals C _A1 and B
The contrast signal C _B is input to the adder circuit 91,
The addition output is attenuated at a constant ratio by an attenuation circuit 93 to reach a focus detection threshold level, and is compared with the absolute value output from the absolute value circuit 92 in a comparison circuit 94. Also, the absolute value output above is
The NG level generated by the NG level generation circuit 95 is compared with the comparison circuit 96. Furthermore, the corrected A contrast signal C _A1 and B contrast signal C _B
is compared with the focus effective range limit level generated by the focus effective range limit level generation circuit 97 in a comparison circuit 98 . The outputs of the direction detection circuit 79 and comparison circuits 94, 96, and 98 are input to a focus state determination circuit 85, and signals indicating the focus state are output to terminals 83, 84, and 85.

FIG. 33 shows a more specific circuit example of the direction detection circuit 79, focus detection circuit 78, and NG detection circuit 80 in the focus determination circuit _U4 shown in FIG. 32 above.

Hereinafter, the operation of the above circuit will be explained, and the configuration will also be explained. A corrected to terminal 75'
The contrast signal C _A1 and the B contrast signal C _B are input to the terminal 76, and the difference between the two is extracted by the operational amplifier 90a, which is a differential circuit.At the same time, the difference between the two is extracted by the operational amplifier 91a, which is an addition circuit. The sum of both is extracted.

The difference signal, which is the output signal of the operational amplifier 90a, is converted into an absolute value signal of the difference by the operational amplifier 92a, the diodes _D5 , _D6 , and the operational amplifier 92b. The signals are respectively input to other comparators 96a.

Further, the difference signal which is the output signal of the above-mentioned operational amplifier 90a is sent to the comparator 79 which becomes the direction detection circuit 79.
a, and a digital signal indicating whether the difference signal is positive or negative is output to terminal 99. On the other hand, the signal added by the operational amplifier 91a is attenuated at a constant ratio by the resistors R ₃₉ , R ₄₀ , and R ₄₁ forming the attenuation circuit 93 to reach the focus detection threshold level. A switch 93a is provided to change the focus detection threshold level into two levels, and the focus detection accuracy can be adjusted by this switch 93a. In the illustrated circuit example, switching is performed in two stages, but switching may be performed in three or more stages. This focus detection threshold level is determined by the comparator 94a.
A digital signal representing the magnitude relationship with the absolute value signal of the difference is outputted to the terminal 100.
Further, the NG level is generated by resistors _R42 and _R43 , which constitute the NG level generation circuit 95, and is generated by a comparator 96a.
is compared with the absolute value signal of the difference, and a digital signal representing the magnitude relationship thereof is outputted to the terminal 101.

34A to 34E show terminal 99 and terminal 101.
This shows how the digital signal is output.
First, Fig. 34A shows the corrected A contrast signal.
FIG. 34B shows the difference signal between C _A1 and the B contrast signal C _B , and FIG. 34D shows the absolute value of the difference signal. The digital signal outputted to the terminal 99 is as shown in FIG. 34C, with a high level indicating a front pin state and a low level indicating a rear pin state. FIG. 34E shows a digital signal output to the terminal 101, which becomes high level when the NG level 90 is greater than the absolute value signal of the difference.

In the digital signal shown in Fig. 34C, when the amount of defocus increases, the corrected A contrast signal C _A1 and B contrast signal C _B match, so that the digital signal is as shown in Figs. 35A and B. Even in the front pin state, it often shows a low level. Therefore, the difference between the contrast signals of C _A1 and C _B is NG.
When the level is lower than 90, NG display area 90
One of the purposes of the NG detection circuit 80 is to avoid displaying the front pin and the rear pin as a.

FIG. 36 and FIGS. 37 a to 37 h are diagrams for explaining the operation of the focus effective range determination circuit 81.

As mentioned above, focus effective range limit level 88
The output of the focus instruction signal is allowed only when both the contrast signals C _A1 and C _{B are larger than the contrast signals C A1 and C B} , but these contrast signals may become higher or lower depending on the subject. For this reason, if the focus effective area restriction level 88 is constant, an in-focus display may be made at a place that is not in an in-focus state. Figure 37a shows a relatively high contrast signal distribution, and Figure 37e shows a relatively low contrast signal distribution. FIGS. 37b and 37f each represent the absolute value signal of the contrast signal difference. Fixed focus range limit level 8
8, and focus detection threshold level 89a, 8
9b is set as shown in the figure, focus effective areas 104 and 104' are obtained, and at this time, focus instruction signals as shown in FIGS. 37c and 37g are obtained, respectively. In FIG. 37g, an accurate focus instruction signal is obtained, but in FIG. 37c, a false focus instruction signal appears in the shaded area. If the focus effective range limit level 88 is fixed in this manner, a problem arises in that a false focus instruction signal is issued when the contrast signal is high. Therefore, in the present invention, when the contrast signals C _A1 and _CB are high, the focus effective range limit level 88 is set high to prevent the generation of the false focus instruction signal. That is, in this variable focus effective range limit level setting method, the focus effective range limit level is determined in proportion to the peak value of the video output. As shown in FIG. 36, when the video output changes from 105 to 105a, the contrast signal also increases, and at the same time the peak value 106 of the video output from the B image sensor section changes to peak value 106a, which also becomes high. If the focus effective range limit level 88 changes in proportion to the change in the peak value of the B image sensor section, the focus effective range limit levels 107 and 108 in FIGS. are obtained, and at this time, focus instruction signals as shown in FIGS. 37d and 37h are obtained. In this manner, the variable focus effective range limit level setting method can prevent false focus display from occurring. In the examples shown in Figures 37a and 37e, the peak value of the video output of the B image sensor section is used, but the peak value of the video output of the A image sensor section may also be used, or the average value of both may be used to obtain the same effect. Can be done. Incidentally, even with the fixed focus effective range limit level setting method, if the level is increased, false focus display can be prevented, but focus detection becomes impossible for objects with low contrast. With the variable focus effective range limit level setting method according to the present invention, focus detection is possible even for objects with low contrast, and false focus display can be prevented.

Next, FIG. 38 shows an example of the circuit configuration of a focus effective range determination circuit 81 to which the above-described variable focus effective range limit level setting method is applied. In the figure, 110 is a video signal input terminal, 111 is a subtraction circuit, 112 is a peak hold circuit, and 113 is a subtraction circuit.
is a dark level detection circuit, 114 is a differential circuit, 115
is an attenuation circuit, and 116 is a determination circuit.

When a video signal is input from the terminal 110, a subtraction circuit 111 first subtracts a certain level from the video output, and a peak hold circuit 112 detects the peak value of the video output. On the other hand, the dark level detection circuit 113 detects the output of the mask sensor 35a or 35b whose location is shown in FIG.
14. The differential output is then input to the attenuation circuit 115 to create a focus effective range limiting level. Next, the determination circuit 116 compares this focus effective range limit level with both the contrast signals C _A1 input to the terminal 75a and C _B input to the terminal 75b, and
A signal indicating the focus effective range is output at 17.

FIG. 39 shows a more specific circuit example of the focus effective range determination circuit shown in FIG. 38. The configuration will be explained along with the operation below.

The process in which the focus effective range limit level is extracted and the timing of the control pulses of the analog switches _S12 to _S15 applied to the circuit of FIG.
It is shown in Figure 0. The output 123 of the mask sensor 35a or 35b is extracted from the video output input to the terminal 110 by the analog switch _S12 to which the control pulse _P10 is input according to the timing shown in FIG. _{40 and the capacitor C7} . This signal is sampled and held, and is input to one terminal of an operational amplifier 114a, which is a differential amplifier, via an operational amplifier 113a, which is a buffer amplifier. This sampled and held output Vd corresponds to the dark level caused by the dark current of the image sensor S _A or S _B. The charge stored in capacitor _C7 is applied to terminal 120 by the control pulse shown in FIG.
_P11 is discharged and reset by the input analog switch _S13 . On the other hand, a certain level is subtracted from the above video output by the resistor R ₄₄ and the constant current source 118, and the analog switch S ₁₄ receives the control pulse P ₁₂ shown in FIG. 40 at the terminal 121.
The peak value of the video output of the B image sensor S _B section is extracted by the operational amplifier 112a, the diode _D7 , and the capacitor _C8 . This peak value is calculated by the operational amplifier 11 which becomes a buffer amplifier.
2b to the other terminal of the operational amplifier 114a. The charge stored in the capacitor C ₈ is applied to the terminal 122 by the control pulse P ₁₃ shown in FIG.
is discharged and reset by the analog switch _S15 which is inputted. Next, the operational amplifier 114a
The differential output from is attenuated by resistors R ₅₀ , R ₅₁ , and R ₅₂ to create a focus range limiting level. The switch 115a is provided to switch the focus effective range restriction level into two levels, and this switch 115a allows the focus effective range to be set to an appropriate value in response to changes in the contrast signal distribution due to changes in the F value of the lens, etc. You can select the area restriction level. In the figure, 2
Although the steps are changed in this embodiment, the steps may be changed to three or more steps. As described above, the variable setting circuit is constituted by the resistors R ₅₀ , R ₅₁ , R ₅₂ and the switch 115a. This focus effective range limit level is determined by the contrast signal C _A1 inputted to the terminal 75a and the comparator 116.
a, and the other is the contrast signal C _B input to the terminal 75b and the comparator 116.
When both the contrast signals C _A1 and C _B are higher than the focus effective range limit level, a signal that becomes high level is outputted to the terminal 117 by the AND gate 116c.
The signal waveform of Vp-Q ₁ in Fig. 40 is the signal waveform of operational amplifier 1.
12b, and corresponds to the waveform obtained by subtracting a certain amount _Q1 from the peak hold waveform Vp of the video output. The waveform Vp- _Q1 -Vd represents the output of the operational amplifier 114a, and corresponds to the waveform obtained by subtracting the dark level (output level of the mask sensor) Vd from the waveform Vp- _Q1 . By subtracting the dark level Vd in this way, it is possible to compensate for the increase in the peak value that occurs when the charge accumulation time becomes longer or when the dark level becomes higher due to temperature. An appropriate focus range limit level 124 is obtained that is not affected by changes in . It is not always necessary to subtract the fixed amount Q ₁ here, and the same effect can be obtained as long as the focus effective range limit level is proportional to the peak value of the video output.

FIG. 41 shows a specific circuit example of the focus state determination circuit 82 shown in FIG. 32. FIG. 42 shows the focus state determination circuit 82.
The control pulses used for this are shown. Also the fourth
FIG. 3 shows signals input to the focus state determination circuit 82 and instruction signals output. The output signal of the direction detection circuit 79 as shown in FIG. 43e is input to the terminal 99,
The output signal of the focus detection circuit 78 as shown in FIG. 43c is input to the terminal 100, the output signal of the NG detection circuit 80 as shown in FIG. The output signal of the focus effective range determination circuit 81 as shown in FIG. 43d is input to the input signal. These signals are subjected to logic processing by AND gates 125, 126, NOR gates 127, 128, OR gates 132, 133, and inverters 24e, 24f, 24g, and output to D flip-flops _FF2 ,
Three types of signals are output to the Q terminals of FF ₃ and FF ₄ .
A control pulse _P15 as shown in FIG. 42 is input from a terminal 135 to the clock terminal C of these three D flip-flops.

Therefore, once these three signals are processed, they are held for one scanning period Ts. Therefore, a stable instruction signal can be obtained. The Q output terminals of these three D flip-flops FF ₂ , FF ₃ , FF ₄ are as follows:
input to one terminal of NOR gates 129, 130, 131, respectively, and these NOR gates 129,
It is connected to an output terminal 83 for a front focus instruction signal, an output terminal 84 for a focus instruction signal, and an output terminal 85 for a rear focus instruction signal via terminals 130 and 131, respectively. Although not shown in FIG. 41, as shown in _FIG . diode 6
a, 6b, 6c, and the other is a lens drive device
It is connected to U ₆ .

In addition, each of the Noah gates 129, 130, 13
The other input terminal of 1 has two terminals 136, 1
37 are commonly connected through an OR gate 134, and the light emitting diodes 6a, 6b, 6c, etc. are caused to emit light only when the input signals from these two terminals 136, 137 are simultaneously at low level.

Then, one terminal 1 of the above two terminals
36, one scanning period Ts as shown in FIG.
A digital signal _P15 that changes every time is inputted, and causes the light emitting diodes 6a to 6c to blink.

By doing so, it is possible to realize flashing light emission with a frequency proportional to the brightness of the subject, and when the brightness is low, the flashing frequency is slowed down so that a warning can be given. In addition, the other terminal 137 receives a digital signal _P16 that becomes high level when the shutter is released, and when the shutter is released, the light from the light emitting diodes 6a to 6c for displaying the focus influences the photometry for controlling the exposure. It prevents you from doing so. Therefore, if the influence on photometry can be prevented by other means, the terminal 137 is not particularly necessary.

Further, the lighting section of the light emitting diodes 6a to 6c is as shown by the signal _P17 in FIG. 42.

This focus state determination circuit 82 sends a signal as shown in FIG. 43g to the light emitting diode 6a, a signal as shown in FIG. 43h to the light emitting diode 6b, and a fourth signal to the light emitting diode 6c.
When a signal as shown in Figure 3i is applied, the light emitting diode 6b lights up in the focus display area, the light emitting diode 6a lights up in the front focus state, and the light emitting diode 6c lights up in the back focus state, and furthermore, the light emitting diode 6c lights up in the back focus state. When the focus cannot be detected, the light emitting diodes 6a and 6
c lights up at the same time.

In addition, each of the light emitting diodes 6a to 6 as described above
Along with the display operation by c, the lens driving device is activated by the front focus or rear focus signal as described above.
_U6 is controlled, the amount of extension of the lens system 2 is controlled, and the focusing operation is automatically performed.

As detailed above, according to the present invention, the self-scanning photoelectric conversion unit performs time-series photoelectric conversion proportional to the illuminance distribution of the subject image at two positions equidistant before and after the position equivalent to the imaging surface of the lens system. output a signal,
On the other hand, the peak value within one scanning period of the photoelectric output difference between any two microscopic photoelectric elements with a constant interval in each of the self-scanning photoelectric conversion sections is determined to correspond to the amount of extension of the lens system. output as two contrast signals in time series, and further determines a focus effective range based on a predetermined effective range limiting level proportional to the peak value of the time-series photoelectric conversion signal and the level of the two contrast signals. When the levels of these two contrast signals are simultaneously higher than the effective range limit level, the two contrast signals are compared by the circuit.
Since the focus instruction signal obtained from each contrast signal is output, the following extremely excellent effects can be obtained.

As explained above, the present invention changes the focus effective range restriction level according to the contrast of the subject, so that the focus detection accuracy for subjects with low contrast is guaranteed and the contrast of the subject is reduced. This has the effect of preventing the generation of false focus instruction signals that occur when the focus is high. In addition, even if the contrast changes due to changes in the subject or camera shake, stable focus detection or display can be performed within a range that can be considered to be practically in-focus near the in-focus position. When displaying, the display light does not flicker and a stable lighting display state can be obtained. Furthermore, since it is possible to give stable focusing instructions even when there are changes in brightness or contrast of the subject, it is possible to give accurate focusing instructions even when there is a moving subject or in the presence of camera shake.

Furthermore, since it is a so-called TTL type that performs focus detection using the light that has passed through the photographic lens system,
It is possible to provide a practical automatic focus detection device suitable for single-lens reflex cameras, TV cameras, etc.

In addition to the above-mentioned common effects, each of the embodiments also exhibits the following effects.

That is, when a mask sensor is disposed in a part of the photoelectric element array and a predetermined effective range restriction level is set by the value obtained by subtracting the output level of the mask sensor from the peak value of the time-series photoelectric output, Accurate focus display can be performed while maintaining sufficient focus detection ability even under special circumstances such as low-brightness subjects or elevated ambient temperatures.

Additionally, if a variable setting circuit is provided that can set the effective range restriction level to an arbitrary level, false focus will not be displayed even when the aperture ratio of the lens becomes large or the contrast of the subject becomes extremely strong. This can be accurately prevented, and accurate focus display can be performed at all times.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing an embodiment in which an automatic focus detection device for a camera according to the present invention is incorporated into a single-lens reflex camera, Fig. 2 is a schematic diagram showing the contrast distribution of a subject image, and Fig. 3 is a schematic diagram showing an embodiment of the camera autofocus detection device according to the present invention. A block diagram showing an embodiment of an automatic focus detection device for a camera,
FIG. 4 is an exploded perspective view of the light receiving section in the same device;
FIG. 5 is an explanatory diagram of the optical path of the light receiving section, etc., shown in a side view. FIGS. 6 and 7 A and B are explanatory diagrams of the focus detection principle of the device of FIG. 3, and FIG. Figure 3 is a block diagram showing an example of the video circuit in the device, Figure 9 is a characteristic diagram showing the photoelectric conversion characteristics of the image sensor, and Figure 10 is a specific diagram of the start pulse generation circuit and image sensor drive circuit in Figure 8. 11 is a timing chart of control pulses applied to the circuit of FIG. 10, FIG. 12 is a block diagram showing a more detailed configuration of FIG. 8, and FIG. 13 is a diagram of FIG. 3. 14 is a timing chart of pulses that drive the image sensor, FIG. 15 is a block diagram showing an example of the contrast detection circuit in FIG. 3, and FIG. The specific circuit diagram in the figure, Figures 17a to 17h are
5 is a diagram showing the contrast signal extraction process by the circuit of FIG. 5, FIG. 18 is a timing chart of control pulses applied to the circuit of FIG. 16, and FIG.
B, FIG. 20, and FIGS. 21A and B are schematic diagrams for explaining the characteristics of the contrast signal by the circuit of FIG. 15, and FIGS. 22, 23, and 24A.
~E and FIGS. 25A and 25B are illustrations of the problem caused by the imbalance of two contrast signals, the second
6 is a block diagram showing an example of the focus determination circuit in FIG. 3, FIG. 27 is a circuit diagram showing an example of the contrast compensation circuit in the circuit of FIG. 26, and FIGS. Characteristic curve diagrams for explaining the focus discrimination operation by the circuit of FIG. 29, FIG. 30, and FIG. 31 A to F
3 is a characteristic diagram for explaining the focus detection action shown in FIG. 3, FIG. 32 is a block diagram showing an example of a more specific example of the focus determination circuit in FIG. 26, and FIG. 34A to 34E and 35A and 35B are characteristic diagrams illustrating the direction detection signal and focus detection failure display signal according to FIG. 32, and FIGS. 36 and 37 are diagrams showing circuit examples.
Figures a to h are diagrams for explaining the operation of the focus effective range determination circuit in the circuit of Figure 32;
The figure is a block diagram showing an example of the structure of the focus effective range judgment circuit in Fig. 32 using the variable focus effective range limit level setting method, Fig. 39 is a diagram showing a specific circuit example of Fig. 38, and Fig. 40 is a diagram showing a specific example of the circuit shown in Fig. 38. The figure is an explanatory diagram of the signal processing process by the circuit in Figure 39, Figure 41 is a diagram showing a specific circuit example of the focus state determination circuit in Figure 32, and Figure 42 is a control applied to the circuit in Figure 41. Pulse timing charts in FIGS. 43a to 43i are characteristic diagrams for explaining the signal processing process by the circuit in FIG. 41. 2... Lens system, 5... Self-scanning photoelectric conversion unit, 6a, 6b, 6c... Light emitting diode, 16
...Light splitter, 19... Image sensor drive circuit, 35a, 35b... Mask sensor, 77...
Contrast compensation circuit, 78...Focus detection circuit, 79...Direction detection circuit, 80...NG detection circuit, 81...Focus effective range determination circuit, 82
...Focus state determination circuit, 115a...Switch, M _A , M _B ... Monitor sensor, R ₅₀ , R ₅₁ ,
R ₅₂ ...Resistors that make up the variable setting circuit, S _A , S _B ...
...Image sensor, SR ₁ , SR ₂ ...Scanning circuit, U ₁
...Receiving section, _U2 ...Video circuit, _U3 ...Contrast detection circuit, _U4 ...Focus judgment circuit,
U ₅ ... Display drive circuit, U ₆ ... Lens drive device.

Claims (1)

[Scope of Claims] 1. A photoelectric element array, each consisting of a plurality of microphotoelectric elements, arranged at two equidistant positions before and after a position equivalent to the imaging surface of the lens system, and a scanning circuit corresponding to the photoelectric element array. two sets of self-scanning photoelectric conversion units that output time-series photoelectric conversion signals corresponding to the illuminance distribution of the subject image; a contrast detection circuit that outputs the peak value of the photoelectric output difference between each microscopic photoelectric element within a certain period as a contrast signal in time series in accordance with the amount of extension of the lens system; a focus effective range determination circuit that compares the levels of the two contrast signals with an effective range limit level that changes in proportion to the peak value, and the level of the two contrast signals is determined by the effective range limit level. When simultaneously greater than the level, the corresponding 2
An automatic focus detection device for a camera, characterized in that a focus support signal obtained from two contrast signals is output. 2. A mask sensor in which a light shielding mask is attached to a minute photoelectric element is arranged in a part of the photoelectric element array, and the output level of the mask sensor is subtracted from the peak value of the time-series photoelectric conversion signal. The automatic focus detection device for a camera according to claim 1, wherein the effective area restriction level is set. 3. The automatic focus detection device for a camera according to claim 1 or 2, wherein the focus effective range determination circuit includes a variable setting circuit that can set the effective range restriction level to an arbitrary level.