JPS6343833B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION The present invention relates to an apparatus for detecting and correcting known erroneous channels in multiple channel parallel data processing systems, such as magnetic tape storage systems. More specifically, the present invention relates to increasing the number of correctable error channels recorded on the same recording medium without increasing the number of redundant channels. In magnetic tape storage systems, the tape size,
Industrial standards have been established regarding data formats and recording densities. For example, to record nine tracks on a tape, a 1.27 cm wide tape is used.
Typically, data is recorded on tape bit-parallel and byte-serial. This recording format allows the same nine-track head to be used to read data from or write data to tape at different densities. Magnetic tape is flexible and highly flexible. Magnetic tape storage systems differ from other forms of mobile magnetic storage media, such as rigid magnetic disks, in that they
Transferring data requires moving the tape in uneven contact with one or more fixed heads. Microscopic debris that becomes loose between the head and tape, or spots of oxide defects in the tape, result in loss of signal amplitude and data errors in one or more channels. Under these circumstances, the recovered clock of the erroneous channel may become out of sync with the data of the other channels. As a result, recording data to or reading data from tape may be erroneous over very long segments. In this regard, tape noise length presents a different data recovery problem than either transient or burst noise. The characteristics of errors induced by transient or burst noise are:
It is that it usually has a finite duration.
Reproduction of defective data is possible by using an error checking code with cyclic characteristics. This code is complex in theory and usage. Examples of magnetic tape storage systems that can record at variable densities and utilize cyclic codes for error detection and correction include:
IBM 3803 magnetic tape controller used with IBM 3420 model 4, 6, and 8 magnetic tape units. The cyclic code actually used is the U.S. Patent No.
It is explained in No. 3868632. Current tape usage practice is that in a set of nine channels, redundant information for seven channels is recorded on the remaining two channels. According to this configuration, up to two error channels can be corrected. Regarding the case where one set of channels is provided with two redundant channels and two or more sets of logically independent parallel channels are recorded on a tape, please refer to Japanese Patent Laid-Open No. 88109/1988. This publication discloses a method and apparatus that utilizes unused redundancy in one channel set to correct multiple erroneous channels in another channel set. Prior art for detecting and correcting errors in nine-channel data processing systems includes U.S. Reissue Patent No. 28923, U.S. Patent No. 3868632, and IBM Technical Disclosure Publication (IBM).
Technical Disclosure Bulletin, Vcl.14, pp38
~46, May 1972), and the IEEE document “Dual Track Error Correction Codes for Magnetic Tape” (A
Double Track Error Correction Code for
Magnetic Tape, IEEE Transactions on
Computers, June 1976, pp642-645). The codes disclosed in the above-referenced U.S. Pat. I need. These check bits will be recorded later. When recovering data from parallel channels, the check bits of each block must effectively be recomputed and compared. Devices using such cyclic codes are complex and expensive. More importantly, the verification information obtained when restoring one data block is discarded when restoring the next data block. The above IEEE document discloses a code structure that uses vertical parity check codes and a single diagonal parity check code stored on two redundant channels to correct two error channels.
The IBM Technical Disclosure Bulletin describes a method for restoring records from multiple tapes by calculating data values to replace unavailable data from simple parity with modulus 2 added to the available data. are doing. SUMMARY OF THE INVENTION It is an object of the present invention to detect and correct erroneous channels on a multi-channel parallel data processing system without the need for cyclic correction or block decoding, so that the check information obtained during recovery of recorded data is It is an object of the present invention to provide an apparatus used to detect and correct errors in subsequently restored data. Another object of the invention is to provide an apparatus for detecting and correcting up to three known error channels even with long (almost infinite) error runs. Another object of the invention is to provide an apparatus for generating internal pointers pointing to error channels in the absence or to supplement external pointers. Another object of the present invention is to record a single parity code in a variety of data formats and to record check bytes in data and data formats.
It is an object of the present invention to provide a device that can be selectively inserted into a bite. The above objectives provide that a multi-channel data processing system having at least one redundant channel:
This is accomplished by an embodiment of the invention coupled to a device that corrects up to three error channels. In the error channel correction device, vertical parity check codes are recorded in the first redundant channel, and diagonal parity check codes taken in a predetermined positive or negative slope direction are recorded in one format selected from a group of formats. recorded. The group of formats includes non-distributed formats such as second and third redundant channels, distributed formats that include regularly spaced pairs of channel-crossing byte locations, and distributed formats that include regularly spaced pairs of channel-crossing bytes. Consists of a mixed format used with redundant channels. In order to accurately reproduce the data recorded on the parallel channels, the error channel correction device determines syndromes from the parity check code and the data. More specifically, the error channel correction device determines both diagonal syndromes and vertical syndromes from the parity check code and data.
Error detection is based on the fact that two syndromes intersect at the same error location in a known error channel. Corrections are made by logically combining the error or correction signal with the original channel data. In this case, one of the two crossing syndromes must be a diagonal syndrome. When generating a correction signal, means are provided for selecting from the two diagonal syndromes a syndrome that is close to the known error channel. In the present invention, when an error is detected in a known channel, successive corrections of the syndrome are made by inverting the parity of the syndrome diagonally across the error location. Therefore,
The remaining diagonal syndromes are only affected by new errors that have not yet been corrected. As an aspect of the invention, internal pointers pointing to error channels are generated from diagonal syndromes and vertical syndromes in the absence or as an aid to external pointers. Internal pointer generation uses a dedicated counter,
This is done by modifying the counter value as a function of the bit position difference based on the parity check code mismatch in the diagonal and vertical syndromes. The discrepancy in the parity check codes of the diagonal and vertical syndromes across the error location determines the initial value of the counter and the direction in which it is changed. The next mismatch between the diagonal syndrome and the vertical syndrome determines when the counter stops. The pointer itself is the first
This is the count difference in intra-channel bit positions between the first syndrome mismatch and the second syndrome mismatch. A discrepancy between a far diagonal syndrome and a vertical syndrome increases the counter, and a discrepancy between a near diagonal syndrome and a vertical syndrome decreases the counter. The only exception is that the channel recording the vertical parity code may be erroneous. In this case, the two diagonal syndromes coincide and the vertical syndrome indicates a mismatch. DESCRIPTION OF THE EMBODIMENTS Referring to FIG. 1, there is shown a simplified block diagram of a multiple channel parallel data storage system incorporating the present invention. Information from the information source 1 is applied to a buffered control device 3. The control device 3 formats the data, performs the necessary parity encoding and causes the formatted and parity encoded data to be recorded on parallel channels of the storage unit 5.
The buffered control device 7 reads the data recorded on the parallel channel and uses it in the device 11 that uses it.
Reformat and decipher it to give to. Operationally, the information of the controller 3 is sent in parallel form via the path 2 to the parity check encoder 9.
In the encoder 9, parity check bits are generated sequentially for sets of information signals called bytes.
After the parity check bit has been recorded together with the information signal, both of these are read out from the storage unit 5 and
By utilizing two syndromes and a pointer to guide a correction signal and combining the correction signal with the read information, parity detected errors in the information can be modified. The derivation of the syndrome and correction signals is done in the decoder 19. Decoder 1
9 induces the syndrome using test bits. Test bits covering the information (data) signal are recorded in the vertical direction and in the cross-channel direction with a positive or negative slope. Referring again to FIG. 1, decoder 19 interacts with controller 7 to receive data via path 21 and return decoded data via path 33. FIG. 4 is a logic diagram showing the generation of syndromes, their correction, and generation of correction signals by the decoder. The data applied via the decoder input path 21 is input to the diagonal syndrome generator 2.
3. Processed by error pattern generator 25 and error corrector 27. Generally speaking, data with errors on parallel tracks are processed by syndrome generator 2.
3 is applied to the parallel line of passage 21 connected to 3.
The output of the syndrome generator 23 is applied to an error pattern generator 25. Single channel (i=j)
The correction signal e _n (i) for correcting is applied to the error corrector 27 via a path 29. When correcting two channels, the signals e _n (i) and e _n (j) are applied to the error corrector 27 via paths 29 and 35. Continuous syndrome correction is accomplished by feeding the correction signal back to gating device 22 via path 601 and interacting with new syndrome information being input from syndrome generator 23 to error pattern generator 25. be done. Recording Format and Test Bits for Correcting Two Channels Referring now to FIGS. 2A-2C, a format for recording nine parallel channels along the tape is shown. In Figure 2A,
Parity for 8 channels (tracks)
A channel P is provided for recording bits. Such parity bits are covered by U.S. Patent No.
It is known as the Vertical Redundancy Check (VRC) bit, as described in US Pat. A byte _Bn consisting of 8 bits and a VRC bit is recorded simultaneously on 9 channels. It may be read from the recorded channel and reorganized into bytes as disclosed in US Reissue Patent No. 25,527. In FIG. 2A, let B _n (k) refer to the mth bit as we proceed from left to right along the kth channel. Further, let B _n represent an 8-bit byte recorded on parallel channels 0-7 of a recording medium such as magnetic tape. B _n can be expressed as follows. B _n = [B _n (0), B _n (1), B _n (2), ... B _n (7)] ... (1) where m = 0 to M, and M = 8xn. B _n (8) is the byte parity of B _n recorded on channel P. That is, B _n (8)= ₇ 〓 ^k=0 B _n (k) ……(2) (The circle on the sum symbol indicates the modulus 2 total.) B ₀ , B ₈ , B ₁₆ , B ₂₄ ,… ..., B _8N is a check bite. Each provides diagonal parity check bits for the seven data bytes on either side of it: B _n (k)= _7-k 〓Γ ^t=0 B _nt (k+t) _k 〓Γ ^t=1 B _n+t (k-t)
...(3) Byte B _-1 at the two ends of the record,
B _-2 ,...,B _-7 and byte B _M+1 ,B _M+2 ,...,
B _M+7 does not exist. These are considered to be all zeros in the calculation of equation (3). Parity check formula (2) and (3)
can be rewritten as: ₈ 〓Γ ^k=0 B _n (k)=0 ...(4) ₇ 〓Γ ^k=0 B _nk (k)=0 ...(5) The read byte may have an error. If the parity checks of equations 4 and 5 are not satisfied, the result is called an error syndrome. In Figures 2B and 2C, channel 0 is provided for the parity bit. That is, channel 0 is provided for recording diagonal parity check bits taken in the positive slope direction. In FIG. 2D, diagonal parity checking is shown to be performed in the negative and positive slope directions. The formats of FIGS. 2B and 2C are used for two-track corrections, and the format of FIG. 2D is used for three-track corrections. Encoder for Generating Diagonal Check Bits Referring now to FIG. 3, there is shown an encoder 9 that generates the parity check bits required in the format of FIG. 2A. The vertical parity check bits are obtained by simply adding modulus 2 the channel bit values in the vertical (cross-channel) direction. Vertical check (VRC) logic and apparatus are explained in detail in the prior art (see, eg, US Reissue Pat. No. 28,923), so further explanation may be unnecessary. Therefore,
Only the diagonal parity check bit generation portion is shown here. It consists of a shift register capable of generating diagonal parity check bits. The diagonal parity check bits are later set by the control device 3 at track-crossing bite positions B ₀ , B ₈ , B ₁₆ , . . . in order to satisfy the format of FIG. 2A.
Recorded in B _8N . Vertical parity check bits are recorded on channel 8 (track P). encoder 9
The diagonal parity check bit generation portion of is a 7-stage flip-flop (FF1, FF2,...FF6,
It consists of a shift register including FF7). Interposed between each shift register stage is a multiple input single output exclusive OR (XOR) gate. XOR
Gate 195, 197, 199, 201, 20
In addition to connecting one register stage to another (e.g. FF2 to FF3), each of 3,205 has inputs connected to bits arranged diagonally across the channels of the channel set. have XOR gate 193 is the end of B _n+i (0) and XOR gate 205 receives the bit from location B _n+i (6). The bit value from position B _n+i (7) is in stage FF7
directly driven. This shift register configuration operates according to equations (3) and (5). φ is all zero bytes. Check bytes B ₀ , B ₈ , B ₁₆ as the φ bytes and data bytes are entered in the order shown.
Each bit of . . . is generated at output 6 by successive shifting and input processing. That is, first check byte B ₀ is generated, then B ₈ is generated, and so on, all check bytes are generated. this is
To generate B _n (m=0, 8, 16, 24,
), φ, B _n+1 , B _n+2 , ..., B _n+7 bytes must be put into the shift register in this order. When B _n+i is entered, i of B _n
The th bit is generated at the output 6 of the encoder 9.
So far, a combination of vertical parity check and diagonal parity check can correct up to two error channels. Since only the case of generating diagonal parity check bits with a positive slope will be described here, please refer to the above-mentioned publication for the generation of diagonal parity check bits with a negative slope. Recording Format and Testing for Correcting 3 Channels Referring to FIG. 2D, a format is shown that is capable of correcting up to 3 known error channels out of T channels. As will be explained below, this requires only 2(T-1) additional test bits in addition to the three test channels. In the format shown in FIG. 2D,
Let Z _n (t) denote the mth bit along the tth channel. There are (T+2) tracks numbered from 0 to T+1. The bit position m changes from 1 to M. The 0th, Tth, and (T+1)th channels are provided for recording parity check bits. (T
The test bit in the +1)th channel is the sum of modulus 2 bits at the same position m in the remaining (T+1) channels. This test is called a vertical parity test. The corresponding encoding formula is as follows. Z _n (T+1)= _T 〓Γ ^t=0 Z _n (t) ...(A-1) As shown in Figure 2D, each test bit of the 0th channel is arranged along a diagonal line with a positive slope. Give a parity check. Similarly, each test bit of the Tth channel provides a parity check along a diagonal with a negative slope. The mth diagonal test with positive slope is called the d ⁺ _n test and is given by the following encoding formula: Z _n (0) = _T 〓Γ ^t=1 Z _nt (t) ... (A-2) The m-th diagonal test with a negative slope is called the d ^- _n test, and is determined by the following encoding formula. Given. Z _n (T) = _T 〓Γ ^t=1 Z _nt (T-t) ... (A-3) To calculate the diagonal check bits from position 0 to (T-1) in the first part of the record. requires data bits from empty positions with negative numbers. For convenience, these data bits are considered to have a binary value of zero. At the end of the record, test channels 0 and T are extended by (T-1) bit positions to provide diagonal test bits for all bits in each channel. The extended position test bits require data bits from empty positions, but it is assumed that these data bits also take on a binary value of zero. In FIG. 1, the structure of the control devices 3 and 7 and the internal control of the storage unit 5 belong to the prior art, and therefore the relationship between the encoder 9 and the control device 3 and the relationship between the control device 7 and the decoder 19 is shown. A detailed explanation of the relationship will be omitted. Typical systems containing the general functions of buffering, encoding, and decoding are found in the IBM 3803 magnetic tape controller and the IBM 3420 magnetic tape unit. Restoration of Encoded Data Moving away from the mechanism by which vertical and diagonal parity check bits are generated, formatted, and recorded on a multi-channel parallel storage medium, we will shift the focus of the discussion to the ultimate objective of the present invention. .
The ultimate objective of the invention is to detect and correct up to three known erroneous channels in a given set of channels. In the following discussion, the error syndrome will be explained first, and then the decoding process will be explained. In explaining the decoding process, the second
Two-channel correction with an erroneous channel pointer and single-channel correction without a pointer will be discussed separately with reference to the formats shown in FIGS. The format of FIG. 2A will then be used to describe three channel correction with pointers and single channel correction without pointers. Finally, we will explain how error correction is symmetrical in reading in backward reading as well as in forward reading. Syndrome Determination for Two-Channel Correction As mentioned above, the bytes read may have errors. If the parity checks expressed by equations (4) and (5) are not satisfied, the result is called an error syndrome. In other words, a non-zero syndrome clearly indicates the presence of an error.
Let B^ _n be the mth 8-bit byte read from the recording medium. Furthermore, let B^ _n (8) be the byte parity read from the recording medium. The mth vertical parity check syndrome is according to the following relational expression:
It is represented by Sv _n . Sv _n = ₈ 〓Γ ^k=0 B^ _n (k) ...(6) mth diagonal parity check error syndrome
Sd _n is expressed as follows. Sd _n = ₇ 〓Γ ^k=0 B^ _nk (k) ...(7) The modulus 2 difference between the read B^ _n (k) and the written B _n (k) is the mth byte's This is the error pattern e _n (k) at the k-th bit position. B _n (k)=B^ _n (k)e _n (k) ...(8) If equations (4) and (6), (5) and (7) are combined, respectively, [B^ _n (k )B _n (k)] by substituting e _n (k), we get the following. Sv _n = ₈ 〓Γ ^k=0 [B^ _n (k)B _n (k)] = ₈ 〓Γ ^k=0 e _n (k) ……(9) Sd _n = ₇ 〓Γ ^k=0 [B ^ _nk (k)B^ _nk (k)〕= ₇ 〓Γ ^k=0 e _nk (k) ...(10) Errors now in one unknown error track or up to two known error tracks The error in
It can be corrected by processing the syndromes Sv _n and Sd _n . Syndrome Determination for Three-Channel Correction The syndrome processing associated with the format shown in FIG. 2D is done in the same manner as in FIG. 2A. In the case of 3-track correction, in order to distinguish between recorded and read data, syndromes, and correction signals (Figure 2D), let the recorded bit value be Z _n (t) and the read bit value be Z^. _n (t)
shall be. This read bit value may contain errors. Formula applied to read data (A
-1), (A-2), or (A-3) parity check results are called error syndromes. The mth vertical parity check results in the following syndrome. Sv _n = _T+1 〓Γ ^t=0 Z^ _n (t) ... (A-4) The mth diagonal parity check with positive slope produces the following syndrome. Sd ⁺ _n = _T 〓Γ ^t=0 Z^ _nt (t) ... (A-5) The mth diagonal parity check with negative slope produces the following syndrome. Sd ^- _n = _T 〓Γ ^t=0 Z^ _nt (T-t) ... (A-6) Formulas (A-1) and (A-4), Formulas (A-2) and (A-5) , formulas (A-3) and (A-6) yield the following result. Sv _n = _T+1 〓Γ ^t=0 [Z^ _n (t) Z _n (t)] ... (A-7) Sd ⁺ _n = _T 〓Γ ^t=0 [Z^ _nt (t) Z _nt (t)] ...(A-8) Sd ^- _n = _T 〓Γ ^t=0 [Z^ _nt (T-t) Z _nt (T-t)] ...(A-9) e _n (t) Define as follows, e _n (t) = Z^ _n (t) Z _n (t) ... (A-10) Equations (A-7), (A-8), (A-9) formula (A-
10), we get the following result. Sv _n = _T+1 〓Γ ^t=0 e _n (t) ... (A-11) Sd ⁺ _n = _T 〓Γ ^t=0 e _nt (t) ... (A-12) Sd ^- _n = _T 〓Γ ^t=0 e _nt (T-t) ... (A-13) By processing these syndromes, various errors can be corrected. In magnetic tape, by far the most common errors are channel errors caused by large scratches in the magnetic medium. Error channels are known by signal loss, excessive phase errors, unacceptable recording patterns, and other similar external pointers. In the absence of such an external pointer, the error channel can be known by processing the syndrome. By handling the above syndromes, up to three known error channels can be corrected, and one error channel can be determined and corrected even in the absence of external pointers. If there is a pointer specifying one error channel, a second error channel can be determined and these two error channels can be corrected. Decryption Process and Decryption Device The decryption process involves accessing the data and transferring it from multiple parallel channels of the storage unit 5 to the control device 7. The controller 7 now cooperates with the decoder 19 to determine which channel is in error and generates a correction signal. When considering multiple channel correction, there is a difference between using redundancy to determine that a bit in a given channel is in error and using redundancy to correct the error. Note that there is a countervailing relationship. Error correction is the calculation of a data value to replace the error value. Two-channel correction using pointers Correct all errors if they are confined to at most two known channels as pointed to by channel error pointers i and j (where i < j). I can do it. Equation (9) can be rewritten as follows for an error in the mth byte. Sv _n =e _n (i)e _n (j) (11) Each diagonal parity check is affected by at most two error patterns. Assuming that all errors are corrected up to the (m-1)th bit position of each channel and that the syndrome formula is adjusted for all corrected error patterns, the error in the mth byte is ( Affects the m+i)th and (m+j)th diagonal tests. That is, for these diagonal checks, equation (10) can be rewritten as follows. Sd _n+i =e _n (i) ……(12) Sd _n+j =e _n (j)e _n+ji (i)
When j≠8...(13) Equations (11) and (12) generate the following error pattern. e _n (i)=Sd _n+i ……(14) e _n (j)=Sd _n+i Sv _n ……(15) Next, the byte B _n is calculated using equations (8), (14),
Corrected using (15). B^ _n (i)=B _n (i)e _n (i) ……(16) B^ _n (j)=B _n (j)e _n (j) ……(17) If j≠8 For example, the (m+j)th diagonal syndrome is modified to reflect the correction of B _n (j) as follows. Sd _n+j ←Sd _n+j e _n (j)
If j≠8... (18) The above correction procedure is similarly applied to the next byte by increasing m by +1. If the new values of channel error pointers i and j are not less than their previous values, they can be changed at any byte position m. All channels must be at least 7
If there is no error in consecutive bytes, i
Any value can be assigned to and j. Here, it is assumed that i<j. Internal pointer generation and single channel error correction In this case, the jth channel is in error and j
is not known. An error in the mth byte affects the mth vertical parity check and the (m+j)th diagonal parity check. For these parity checks, equations (9) and (10) can be rewritten as follows. Sv _n = e _n (j) ... (19) Sd _{n + j} = e _n (j), when j≠8 ... (20) Note that Sv _n = 1 indicates the presence of an error. Pointer j is the smallest integer among numerical values 0 to 7 that satisfies the following expression. Sv _n = 1 = Sd _{n + j} ... (21) If Sv _n = 1 for all j from 0 to 7
and Sd _n+j =0, then j=8. Then,
Byte B _n is corrected as follows. B^ _n (j)=B^ _n (j)e _n (j) ……(22) If j≠8, it will be used later (m+
j)th diagonal syndrome is as follows
Amended to reflect corrections in B^ _n (j). Sd _n+j ←Sd _n+j e _n (j) ...(23) Note that if pointer j is modified by a byte, the error is not limited to one track. sea bream. Such errors cannot be corrected without making a false correction. A new value for j can be used after at least seven consecutive bit positions without errors. Decoder Embodiment Referring to FIG. 4, a detailed logic diagram of the decoder 19 is shown. It includes a diagonal syndrome generator 23, an error pattern generator 25 and an error corrector 27. Data B^ _n+i (0), B^ _n+i (1),…
..., B^ _n+i (6), B^ _n+i (7) are applied to the syndrome generator 23 in byte series and bit parallel. The syndrome generator 23 is a seven-stage shift register (stage
The input to each stage except the last (FF1-FF7) is the modulus 2 addition of the contents of the shift register stage and the applied data bit. Data byte B^ _n+8 is syndrome generator 2
At the same time as the data byte B^ _n
is likewise applied via path 21 to error corrector 27. Error corrector 27 shown in FIG.
logically combines (module addition) the error correction signal e _n (i) or e _n (j) provided from paths 29 and 35 with the corresponding element of the data byte to provide corrected data to path 33. It is composed of Error pattern generator 25 in FIG. 4 includes a syndrome processor 24 and gate devices 22 and 26 that correct the syndromes included in processor 24 and generate error correction signals e _n (i) or e _n (j). In this embodiment, up to two error channels may be corrected. Syndrome processor 24 has an 8-speed shift.
Contains registers (FF7...FF0). The input to each stage except the first stage is the content of each stage and the gate device 2.
This is the sum of the syndrome correction value derived from 2 and the modulus 2. This gate configuration is
The error correction signal e _n (j) on the path 601 is set to the pointer value J ₁
~ _J7 to the corresponding XOR gate of the syndrome processor 24. Similarly, the shift register contents of syndrome processor 24 are passed through gating device 26 controlled by other pointer values I ₀ -I ₇ . All values displaced from 0 to 7 of the diagonal syndrome Sd _n+i are stored in the syndrome processor 2
4 shift register stages FF ₇ -FF ₀ and associated gates of gating device 26. Connect each stage of the shift register
The XOR gate modifies the syndrome value by the corrected error pattern from the previous cycle when the syndrome value is displaced to a new position.
Each cycle in which each byte is inserted into the syndrome generator 23, one bit is shifted from it;
The first stage of the syndrome processor 24 is entered. AND only when two error channels are corrected, as shown in gate device 26.
Gate 605 will pass the value of Sd _n+i as a correction signal. This is done by enabling gate 605. On the other hand, this value is input 6
Vertical parity syndrome and exclusive OR on 3
and the result is applied to path 601.
If only one channel is being corrected, no syndrome correction made via path 601 is necessary. That is, for single channel correction, only the correction signal e _n (i) is sent via path 29 to error corrector 27 . I and J represent pointers that specify up to two error channels. These pointers can be derived externally or generated internally. How to generate pointers internally will be explained later.

[Table] Table 1 shows the functions of pointers I and J for Boolean variables P ₀ , P ₁ , D ₂ , . . . , P ₈ . P _k =1
Indicates that the kth channel is incorrect. P _k =0
Indicates that the kth channel is not in error. Here it is 0k8. It turns out that both syndrome generation and error correction are continuous processes. In Figure 4
B^ ₀ , B^ ₁ , . . . , B^ _n , B^ _n+1 are input to the syndrome generator 23 in a shifted manner. When B ₈ is entered, e ₀ (i) and e ₀ (j) appear. Generally speaking,
When B^ _n+8 is input to the syndrome generator 23, e _n (i) and e _n (j) are applied to the error corrector 27. Generation of first channel error pointer by logic device The pointer j of the first error channel is given by equation (21)
It can be determined by finding the lowest value of m and j for which . This can be done by a logic device or a counter device. In Table 2, the relationship between the vertical syndrome and the diagonal syndrome is expressed by an ordinary Boolean function formula that specifies the minimum value of j that satisfies the following equation. The method of using the counter device with Sv _n =1 and Sd _n+j =1 will be explained later for the general case assuming that there are (T+1) tracks.

[Table] Here, Sv _n is the mth vertical parity check syndrome, and Sd _n+i is the (m+i)th diagonal parity check syndrome. Three-channel correction using channel error pointers For decoding purposes, errors shall be limited to at most three known channels, and these error channels shall be pointed to by channel error pointers i, j, k. Assume. It is assumed here that i represents the lowest numbered channel among the error channels having channel numbers 0 through T, and k represents the highest numbered channel. Pointer j represents the remaining error channel, so i<j<k or j=T+
1 holds true. Assuming that all errors are corrected up to the (m-1)th bit position in each channel, and the syndrome formula is adjusted for all corrected error patterns, the error pattern at the mth position of the error channel is the syndrome Sd ⁺ _n+i ,
It can be determined from Sd ^- _Tk and Sv _n . The formulas for these syndromes are formulas (A-11), (A-12),
(A-13). Therefore,
If we remove the known zero error patterns corresponding to error-free channels and the corrected error patterns up to the (m-1)th position, the syndrome equation can be written as: Sd ⁺ _n+i = e _n (i) ... (A-14) Sd ^- _n+Tk = e _n (k) ... (A-15) Sv _n = e _n (i)e _n (j)e _n (k) ... (A-16) Equations (A-14), (A-15), and (A-16) generate the following error pattern. e _n (i)=Sd ⁺ _n+i ...(A-17) e _n (k)=Sd ^- _n+Tk ...(A-18) e _n (j)=Sv _n Sd ⁺ _n+i Sd ^- _n+Tk ...(A-19) The error at the m-th position can be corrected as follows. Z _n (i)=Z^ _n (i)e _n (i) ……(A-20) Z _n (j)=Z^ _n (j)e _n (j) ……(A-21) Z _n (k)=Z^ _n (k)e _n (k) ……(A-22) If only two channels are in error, assign a pointer to one channel without error and follow the above algorithm. processing may be carried out. The resulting error pattern for this error-free channel must be zero. This provides an additional check against erroneous corrections. Before proceeding to the correction of the next bit position, the syndromes affected by the correction must be corrected (especially the syndromes used later). Modifications are indicated by arrows from previously calculated syndrome values to new values. Sd ^- _n+Ti ←Sd ^- _n+Ti e _n (i) ……(A−23) Sd ⁺ _n+k ←Sd ⁺ _n+k e _n (k) ……(A−24) Sd ⁺ _{n+ j} ←Sd ⁺ _n+j e _n (j)
When j<T+1...(A-25) Sd ^- _n+Tj ←Sd ^- _n+Tj e _n (j)
If j<T+1... (A-26) The above correction procedure can be applied to the next bit position by increasing the value of m by 1. Generation and Use of Pointers In the preceding discussion, we have frequently referred to pointers that specify error channels (or tracks). In the following description, we will mainly explain how to generate and use pointers internally. Pointers may be externally derived or internally generated. Normally, in order to generate an external pointer, the read conditions of data recorded in a channel must be sensed in some way in an analog manner. Methods and apparatus for generating external pointers are outside the scope of this invention. The invention includes means for generating one or more internal pointers for error correction in the absence of an external pointer as if an external pointer were present. Assume that a record is written onto a tape with the purpose of error-free reproduction of the record from the tape. Assume that when the tape has just been started and the record is at m=0, there are no errors and all pointers are off. After some time, if an error occurs on one of the channels and no external pointer is generated indicating the channel is in error,
It is necessary to generate a first internal pointer to specify the error channel. Once the first internal pointer is generated, it must remain on to correct errors in the pointed channel while playback operations continue. Of course, such a method of allocating pointers may unduly limit the correction capabilities of the system. This is especially the case if there are no consecutive errors in the indicated channel. However, some systems allow pointers to disappear if no errors occur within a predetermined amount of time after the first error is detected. In this example, it is assumed that one error occurs on one channel. An indication of that channel is given by an external pointer or a first internal pointer. Detection of the first erroneous channel is within the correction capabilities of the system. Additionally, in this case, the first internal pointer is maintained on to correct errors in the indicated channel. But what would happen if other errors were corrected on other channels? This can be pointed to by the second internal pointer as well. However, the pointer pointing to the third error channel can only be generated externally. In other words, the first internal pointer is turned on when the other pointers are absent. The second internal pointer may be internally activated only when the first pointer is present. The second internal pointer is activated whether the first pointer was generated internally or externally. Although internal pointers are considered highly reliable, up to two of the three pointers used in the example system may be generated internally.
Furthermore, two internal pointers cannot be generated at the same time. This is because the second internal pointer requires the existence of a known first pointer as a precondition. Internal pointer generation utilizes a diagonal parity check and a vertical parity check covering the channel. Generation of First and Second Channel Error Pointers If there is no channel error pointer, it is assumed that the error is limited to only one channel. This error channel can be indicated and errors can be corrected. Non-zero at mth position of one channel
The pattern is dictated by a non-zero vertical parity check syndrome Sv _n . Consider the case where this error is in a channel with unknown pointer j and there are no errors in other channels. In this case, the following equation can be obtained from equations (A-11) and (A-12). Sv _n = e _n (j) = 1 ... (A-27) Sd ⁺ _n+j = e _n (j) = 1
In the case of j≠T+1... (A-28) Pointer j is a value from 0 to T that satisfies the following formula.
is the smallest integer up to . Sd ⁺ _n+j = Sv _n = 1 ... (A-29) If j is all from 0 to T, Sv _n =
1 and Sd ⁺ _n+j = 0, then j=T+1. Referring now to FIG. 6A, a first error pointer generator is shown for obtaining an indication of the first error channel when no other pointers are present. This generator consists of a pair of latches 401 and 4
Including 07. These latches start and stop counting down ring counter 405, respectively.
The output of ring counter 405 represents pointer j. Latches 401 and 407 are responsive to syndromes Sd ⁺ _n+T and _Svn , respectively. When Sd ⁺ _{n + T} = 1, latch 401 is set and counter 405
The count value of is made equal to T. Each time bit position m changes along the channel, the counter is decremented by one. On the other hand, when Sv _n =1, latch 407 is set and counter 405 is stopped. The counter value at this point forms pointer j. Latch 401 is set before latch 401 is set.
In the special case where 7 is set, j is equal to T+1. The theory of generation of the second error pointer is explained in the above-mentioned publication. The equations described therein relate to syndromes for two sets of channels. These formulas can be applied to this embodiment with slight modifications. The embodiment of the second error pointer generator disclosed therein consists of a counter device driven by various syndromes. Referring now to FIG. 6B, there is shown the second error pointer generator when the first pointer points to a channel other than T+1. This generator consists of a pair of ring counters 405 and 4
06, and each of these counters
15 and 417, pointers i and j are generated.
The latch 401 is a descending type ring counter 4.
05 to the value j, and the latch 407 sets the rising ring counter 406 to the value j. By the set latches 401, 407
When AND gate 413 is activated, a "stop and gate out" signal is sent to ring counter 40.
5,406. exclusive OR gate 42
Only if a simultaneous mismatch occurs at both points 3 and 425, the output of AND gate 411 will indicate that the second pointer j has been set to T+1. aisle 6
A mismatch between inputs Sv _n and Sd ⁺ _n+j on paths 63 and 75 sets latch 401, and a mismatch between inputs Sv _n and Sd ^- _n+Tj on paths 63 and 71 sets latch 40.
Set 7. Referring now to FIG. 6C, there is shown the second pointer when the first pointer points to channel T+1.
An error pointer generator is shown. The objective is to obtain a second pointer i given a first pointer j=T+1. The generator includes a rising ring counter that is set to zero by latch 427 when input Sd ^- _n+T is one. When m is incremented by one, this counter is incremented by one. Initially, i is set to 0, then i follows the value of the counter. Sd ⁺ _n+i is 1
It should be noted that the counter is stopped when it becomes equal to , and the count value becomes a pointer value.

[Brief explanation of drawings]

FIG. 1 is a block diagram representing a multiple channel parallel storage system including a parity encoder for writing data and a parity decoder for error checking when data is read from the system; FIGS. 2A-2D are parity encoders; FIG. FIG. 3 is a diagram showing a diagonal parity encoder; FIG. 4 is a schematic logic diagram showing the occurrence of the syndrome in the decoder, its correction, and the generation of a correction signal; FIG. 5 is a diagram showing in detail the error corrector 27 of the decoder shown in FIG. 4, FIG. 6A is a logic diagram of the first internal pointer generator, and FIGS. 6B and 6C are respectively shown when the first pointer is T+1. FIG. 4 shows the second pointer generator when it is not set or when it is set. 19...Decoder, 22, 26...Gate device,
23...Diagonal syndrome generator, 24...Syndrome generator, 25...Error pattern generator, 27...Error corrector.

Claims (1)

[Scope of Claims] 1. A device for correcting an error channel among a plurality of parallel channels in which data is written, which writes a vertical parity check code for the data into a first channel, and performs a predetermined correction for the channel. means for writing diagonal parity check codes taken in positive and negative slope directions into separate channels or regularly spaced cross-channel locations; and determining a vertical syndrome from said vertical parity check codes and data; means for determining a diagonal syndrome from said diagonal parity check code and data; and means for detecting a mismatch between a vertical syndrome and a diagonal syndrome across the same error; and while continuously updating bit positions along the channel. An error channel correction device comprising means for examining the output of the detecting means and generating a pointer indicating an unknown error channel according to the number of bit positions from the first mismatch detection to the next mismatch detection. 2 A device for correcting an error channel among a plurality of parallel channels in which data is written, writes a vertical parity check code for the above data into the first channel, and sets the above data in a predetermined positive or negative slope direction. means for writing a diagonal parity check code taken in another channel or regularly spaced cross-channel locations; and determining a vertical syndrome from said vertical parity check code and data; means for determining a diagonal syndrome from the data; and means for generating a pointer to an unknown error channel by comparing the vertical syndrome and the diagonal syndrome while continuously updating bit positions along the channel; An error channel correction apparatus comprising: means for generating a correction signal for a bit from a vertical syndrome and a diagonal syndrome across the bit on the error channel; and means for inverting the diagonal syndrome across the corrected bit.