JPS62246179A - Information recorder - Google Patents

Abstract

PURPOSE:To prevent the read of erroneous data or the impossibility of read which occurs because the number of errors exceeds the correcting capability of an error correcting circuit, by performing the alternating processing if a burst error longer than a prescribed length is detected in case of RAW. CONSTITUTION:A GF arithmetic circuit 15 takes in data from a syndrome generating circuit 12 and a work buffer 14 and continues the operation until an error position and an error pattern are obtained. The error position and the error pattern calculated in this manner are not only stored in a correcting circuit 13 but also inputted to a burst detecting circuit 17. The burst detecting circuit 17 checks whether a burst error occurs or not in accordance with the information of the received error position; and if the burst error longer than a preliminarily determined length occurs, a disk device controller 7 discriminates that data of this sector has not reliability, and this data is written in an alternative sector again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a highly reliable information recording device such as an optical disk device that prevents reading of erroneous data and a state in which reading is impossible.

[Conventional technology]

Generally, in optical disk devices, the reliability of the disk medium is lower than that of magnetic disks, so the reliability of data has traditionally been increased by employing powerful error correction codes. In order to further improve reliability, we check the write track before writing, i.e., pre-check, and read the data immediately after writing to check whether it can be read correctly, i.e., read-after-write (R).
Ead-After-Write (hereinafter referred to as RAW) is often used in combination.

When an error is detected in a pre-check or RAW, data is written to a predetermined replacement area within the disk, in other words, replacement processing such as replacement sectors and trunks is performed, and incorrect data is read due to a disk defect. This prevents it from becoming unreadable.

FIG. 9 shows a block diagram of the optical disc device of the present invention. Data read from the optical disc drive 1 is demodulated by the modulation/demodulation circuit 2 and stored in the sector buffer 3. The error correction circuit 4 corrects errors in the data stored in the sector buffer 3 and then writes the data into the track buffer 5. The data in the track buffer 5 is output to the data bus 8 through an interface circuit 6 with the host computer, and when data is written, the data is written to the optical disk drive through a path opposite to that for reading. All of these operations are configured to be performed under the control of the optical disk controller 7.

By the way, during RAW, conventionally, the error correction circuit 4 performs error correction on the data in the sector buffer 3, and if the number of errors is within the correction capability of the error correction circuit 4, the optical disk controller 7 is notified that the error is normal. It reports that it can be read out, and only reports an abnormality when an error beyond its correcting ability occurs.

In response to this, the optical disk controller 7 performs replacement processing such as replacement sectors and replacement tracks to avoid reading erroneous data and improve the reliability of the optical disk device. FIG. 10 shows a flowchart of such conventional RAW processing.

[Problem that the invention seeks to solve]

However, with conventional error handling methods in optical disk devices, even if it is a burst error that can be corrected during RAW immediately after writing to the disk, defect growth and VF
When a longer burst error occurs due to out-of-synchronization of O, etc., there is a problem that erroneous data may be read or reading may become impossible.

The present invention has been made in order to solve the above-mentioned problems in conventional optical disk devices, and avoids reading of erroneous data due to the growth of burst errors and the state of being unable to read data, thereby improving reliability of optical disk devices, etc. The purpose is to provide an information recording device.

[Means and operations for solving the problem] In order to solve the above problem, the present invention provides a means for detecting the length of a burst error in an information recording apparatus, and a means for detecting the length of the burst error. The apparatus includes means for transmitting an output signal when a burst error of a predetermined length or longer is detected, and means for detecting the output signal and performing replacement processing.

With this configuration, when a burst error of a predetermined length or more is detected during RAW, replacement processing is performed, avoiding reading of incorrect data due to burst error growth and an unreadable state, and improving reliability. It becomes possible to measure.

(Embodiment) An embodiment will be described below. Fig. 1 is a block diagram showing the main parts of an embodiment in which the present invention is applied to an optical disk device, and the same or corresponding parts as in Fig. 9 are denoted by the same reference numerals. It is attached.

In the figure, reference numeral 11 denotes a block buffer within the error correction circuit 4, which is used to store correction unit data (1 code word). 12 is a syndrome generation circuit in which the syndrome is calculated according to the definition; 13 is a correction circuit; 14
A work buffer is used to store the intermediate results of the calculation in the CF calculation cycle 1S15.

16 is an error correction circuit controller, and 17 is a burst detection circuit.

Next, the operation of the error correction circuit 4 configured as described above will be explained. Data read from the disk is demodulated and input to the block buffer 11 and syndrome generation circuit 12 of the error correction circuit 4 via the sector buffer 13. The syndrome determined by the syndrome generation circuit 12 is input to the CF calculation circuit 15, subjected to a predetermined calculation, and stored in the work buffer 14. C.F.
The upper calculation circuit 15 takes in data from the syndrome generation circuit 12 and the work buffer 14, and continues calculation until the error position and error pattern are determined.

The error position and error pattern thus calculated are stored in the correction circuit 13, and the error position is input to the burst detection circuit 17. The correction circuit 13 corrects the block buffer 11 based on the error position and error pattern.
1, the receiver corrects the received data and transfers it to track buffer 5.
An operation of 0 or more written to the error correction circuit controller 1
6 is repeated as many times as the number of code words in one sector.

On the other hand, the burst detection circuit 17 checks whether or not a burst error has occurred based on the error position information received by the receiver, and if a burst error of a predetermined length or longer has occurred, it indicates this to the disk. Report to device controller 7.

The disk device controller 7 includes a burst detection circuit 17
When a signal from the sector is detected, the data in that sector is deemed to be unreliable even if an error occurs within the correction capability of the error correction circuit, and data is rewritten to the alternate sector. The disk device controller 7 executes data writing and RAW using the above process, and correctable burst errors that existed during data writing become uncorrectable due to subsequent defect growth and VFO out-of-synchronization caused by it. This prevents a burst error from occurring, causing incorrect data to be read or becoming unreadable.

Next, the error correction code used in this embodiment will be explained.

In this embodiment, for example, a Reed-Solomon code (Reed-3olomon code) having the following parity check matrix is used.
Code) shall be used.

・・・・・・・・・・・・(11 Here, α is the irreducible polynomial F on the finite field G F f21 (
x)=0. Now, the received data string is R-Do2
rz+...r l, -1)...
... (2), four syndromes shown by the following equation (3) are generated.

Error position is 1 + js error pattern is 1lli,
When ej is assumed, the error position and error pattern when an error occurs can be found as follows.

(i) When there is one error, e, m S On α' -St/ So...
・=”−(41(ii) When there are two errors, the error location-Silane polynomial is x”+a, x+a, wQ−−−−−−1−−(51). Here, σI = (SIS! +56Sfi)/(SIS!+S
l”)・・・・・・・・・・・・(6) σo −(S+Sz+sz”)/(sos,+s+”
)・・・・・・・・・(7)

X-σIy Fist...... (If we set it as 81, (
5) The formula is y”+y+σ./σ−;0・・・・・・・・・・(9)
becomes. The solution to equation (9) is σ. /σl′, and if α′ is the solution of equation (5) obtained from this and equation (8), then α1−σ+α8・・・・・・・・・・・・( 10) e+
= (αJSO+S+)/(α゛+α...
...(11> ej - (α'sO+sl)/(αKame+αJ)...
......(12) becomes.

Next, a specific configuration for finding such error positions and error patterns will be explained. FIG. 2 is a block diagram of the syndrome generation circuit 12. Data read from the disk passes through sector buffer 3,
Through the data line 32, an exclusive OR circuit (XOR
o, XOR+, X0Rt.

XOR+)21.22.23.24. The input data is stored in registers (RO) 25,
α multiplier circuit 29, α2 multiplier circuit 30. An exclusive OR is performed on the output of the α3 multiplier circuit 31 in bit correspondence, and each register (RO+RI+RZ, R3) 25.
Stored on 26.27.28. After this, each time data is input via the data line 32, each time 1° α, α2 . The output of α3 times and the input data are exclusive ORed, and each register (
Ro, R,.

R2, R3) are stored in 25, 26, 27, 28.

By repeating the above operations, when all the data has been input, registers (R,, R1+ R,, Rs) 25.2
At 6.27°28, the syndrome So+Sll S2+ S3 defined by the above equation (3) has been found.

The syndrome thus generated by the syndrome generation circuit 2 is then subjected to a predetermined calculation in the GF calculation circuit 15 shown in FIG. First, addition on GF is executed as follows. The two pieces of data added via the data bus 53 are stored in the register (ORo, CRI) 40.
．． 41. Then the register (ORo,
The data stored in CRI) 40 and 41 is subjected to exclusive OR on a bit-by-bit basis by an exclusive OR circuit (XOR) 44, and the result is stored in a register (OR4) 47.

Multiplication on GF is performed as follows.

The two data to be multiplied via the data bus 53 are stored in registers (ORz, ORz) 42 and 43,
ROM (LOGI) for data conversion.

LOGg) 45.46 converts the vector representation into a cyclic representation. Next, direct data from the data conversion ROM (LOGI) 45 is selected by the selector 49, and this data and the data conversion ROM (LOGz
) 46 is sent to the mode 255 calculator (AD
D) The force U is calculated by 50. The addition result is converted from a cyclic representation to a vector representation by a data conversion ROM (UNLOG) 51 and stored in a register (OR5) 52.

Division is performed in the same way as multiplication, except that the divisor is input into the register (ORz) 42 and the output from the inversion circuit (INV) 48 is selected as the input to the adder (ADD) 50 in mode 255. be done.

In this embodiment, a Reed-Solomon code with double error correction is used, but during RAW, the correction capability is reduced and single correction is performed. In other words, when two or more errors are detected per code word during RAW, it is reported to the disk device controller that an uncorrectable error has occurred, and if there is one or no errors, reading can be performed normally. report. This is to avoid a situation where defects in the disk grow over time and data that was readable at the time of RAW becomes unreadable later.

By the way, when one error is detected in one code word during RAW, the error position and error pattern are calculated according to the above equation (4), and the error position and error pattern are calculated from the calculation circuit 15 on the GF to the correction circuit 13.
is input to the burst detection circuit 17.

FIG. 4 shows the configuration of the burst detection circuit 17. In the burst detection circuit, error position data output from the GF arithmetic circuit 15 is stored in a register (CR, ) 60 via a data line 65. And this register (
The data stored in the register (CR+) 60 has already been stored in the register (C
The previous error position stored in Rz) 61 is compared with the previous error position by a comparator (GOM P +) 62, and if they are equal, a counter (CNT) 63 is incremented. Then, the count value of the counter (CNT) 630 and the number given on the data line 66 are compared by a comparator (COM Pg) 64, and if there is a burst error exceeding the number given on the data line 66 within l sector, Comparator (COM P z)
64 detects it and reports it to the disk controller 7 via a signal line 67. As a result, the disk controller 7 can detect a sector in which a burst error has occurred, and even if the error is within its correction capability, it can treat this sector as having low reliability and perform replacement processing. It is configured.

FIG. 5 shows an example of data error occurrence in this embodiment.

The data shown in FIG. 5 has a burst error of k bytes. The operation of the burst detection circuit will be specifically explained below with reference to FIG. The error position determined by the arithmetic circuit 15 on the CF is determined by the data line 65.
The register (CR+) 60 near -/+ is sent through the register (CR+). If the contents of the register (cRz) 61 are cleared in advance, the error position 1-1 is first cleared in the register (cRz) 61.
CRI) 60, the comparator (C
The output of OMP+) 62 remains at H'. Register (CRI) by clock CK at the next timing
The contents of the register (CRffi) 60 are latched, and the output of the comparator (COM P +) 62 becomes “L”. Next, the data z-1 is stored in the register (CRI) 60.
When latched, a clock pulse for the counter (CNT) 63 is generated by ANDing the delay signal of the latch clock CKt and the inverted signal of the comparator (C0MP+) 62, and the counter (CNT) 63 is incremented.

By repeating this operation, if the value k of the counter (CNT) 63 becomes thicker than the preset value (ko), the output of the comparator (COM P z) 64 becomes L, and the signal w A pulse (BUR3T) indicating the occurrence of a burst error is output from @67. Fig. 6 is a timing chart showing the operation of each part in the burst detection circuit.

As mentioned above, k>k in the burst detection circuit.

By detecting this error and having the optical disk controller perform alternate processing, the original burst error can be converted into a larger uncorrectable burst due to the growth of disk defects and the resulting VFO out-of-synchronization during subsequent reading. It is possible to avoid a situation where an error occurs and incorrect data is read. FIG. 7 shows a flowchart when a burst error is detected and replacement processing is performed.

The means for detecting burst errors does not necessarily need to be configured as hardware within the error correction circuit. The second embodiment shown in FIG. 8 is also applied to an optical disk device, in which burst errors are detected by software in the optical disk controller and replacement processing is performed. The error correction code used in this example is (3
6,32°5) Use Reed-Solomon code. In this embodiment, when writing data, data on the data bus 8 is taken into the interface 6 and further written into the trunk buffer 5. The error correction circuit 4 adds redundant bytes to the data in the trunk buffer 5 and writes it into the sector buffer 3-1. The data in the sector buffer 3-1 is modulated by the modulation/demodulation circuit 2, and the data is modulated by the optical disk drive l.
sent to.

In the RAW mode, data read from the optical disk drive 1 is demodulated by the modulation/demodulation circuit 2 and written to the sector buffer 3-2. Sector buffer 3-+ and 3.
. . , so that it can be accessed from the optical disk controller 7. Here, the optical disk controller 7 is a sector buffer L.

and 34, and count the length of the burst error. When a burst error of a certain length or more is detected, the optical disk controller 7 performs replacement processing in the same way as in the first embodiment. By configuring the optical disk device in this way, it is possible to eliminate the need for special hardware. , the effects of the present invention can be easily achieved.

(Effects of the Invention) As described above in detail based on the embodiments, according to the present invention, when a burst error of a predetermined length or more is detected during RAW, replacement processing is performed. Due to burst errors caused by errors that occur after data is written to the memory card or the resulting VFO out of synchronization, the number of errors may exceed the correction ability of the error correction circuit, resulting in reading incorrect data or making reading impossible. This makes it possible to prevent such problems, and provides an information recording device such as an optical disk device with high reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of an information recording device according to the present invention, FIG. 2 is a block diagram showing a syndrome generation circuit in the error correction circuit, and FIG. 3 is a block diagram showing the same <Block configuration diagram showing arithmetic circuit on GF,
FIG. 4 is a block diagram showing the same burst detection circuit, FIG. 5 is a diagram showing an example of data error occurrence, and FIG. 6 is a timing diagram showing the operation of each part of the burst detection circuit shown in FIG. 4. FIG. 8 is a block configuration diagram showing a second embodiment of the present invention, and FIG. 9 shows an example of the configuration of a general optical disk device. The block diagram, FIG. 1O, is a flowchart when executing the replacement process in the apparatus shown in FIG. 9. In the figure, 1 is an optical disk drive, 2 is a modulation/demodulation circuit, 3.3-+, 3-i are sector buffers, 4 is an error correction circuit, 5 is a track buffer, 6 is an interface,
7 indicates an optical disk controller. Patent issuer: Olympus Optical Industry Co., Ltd. Figure 1 Figure 1, 4 Figure 2 Figure 4 Figure 5 1 Byte Figure 6 Figure 7

Claims (1)

[Claims] In an information recording device equipped with an error correction circuit that performs error correction on data, means for detecting the length of a burst error;
When the burst error length detection means detects a burst error of a predetermined length or more, the read-after An information recording device characterized in that, when a burst error of a predetermined length or longer is detected during writing, replacement processing is performed.