JPS6343489A - Representative line selection and processing system in multi-processor electronic switching system - Google Patents

Representative line selection and processing system in multi-processor electronic switching system

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Publication number
JPS6343489A
JPS6343489A JP18890386A JP18890386A JPS6343489A JP S6343489 A JPS6343489 A JP S6343489A JP 18890386 A JP18890386 A JP 18890386A JP 18890386 A JP18890386 A JP 18890386A JP S6343489 A JPS6343489 A JP S6343489A
Authority
JP
Japan
Prior art keywords
representative
subscriber
line
electronic switching
switching system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18890386A
Other languages
Japanese (ja)
Inventor
Shinji Gogo
吾郷 真治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18890386A priority Critical patent/JPS6343489A/en
Publication of JPS6343489A publication Critical patent/JPS6343489A/en
Pending legal-status Critical Current

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  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To attain detection processing of an idle subscriber line without communicating with another processor by making the common storage device of a multi-processor electronic switching system have the busy idle state of all the representative subscriber lines. CONSTITUTION:The busy idle state of subscriber lines A, B and C exists in the common main storage device 7 which is directly coupled to the respective central control equipments. Therefore when a certain call requests an incoming to the subscriber A of the representative line G1, the system need not commit the process to the central control equipment 4 and by directly scanning the busy idle state of the common main storage device 7, it is decided whether or not the incoming to the subscriber line B can be possible when the subscriber line A is not idle.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマルチプロセッサ電子交換システムの代表群選
択処理方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a representative group selection processing method for a multiprocessor electronic switching system.

〔従来の技術〕[Conventional technology]

従来、マルチプロセッサ電子交換システムにおいては、
代表加入者に対する着信における空回線判定のための情
報(メモリ領域)はその加入回線を制御している中央f
fi理装同装置ロセッサ)固有の記+!i領域に存在し
、その情報は加入者の状態が遷移してゆく時、逐次当該
プロセッサによる処理により更新されていた。
Traditionally, in multiprocessor electronic switching systems,
Information (memory area) for determining whether an idle line is received when a call is received for a representative subscriber is stored in the central network controlling the subscriber line.
fi Risou same equipment processor) unique note +! The information exists in the i-area and is updated by processing by the processor as the status of the subscriber changes.

第1図はマルチプロセッサ電子交換システムの一例を示
すブロック図、第2図は代表回線の構成要素を示す図で
ある。
FIG. 1 is a block diagram showing an example of a multiprocessor electronic switching system, and FIG. 2 is a diagram showing the components of a representative line.

このマルチプロセッサ電子交換システムは、プロセッサ
が2台の場合で、中央制御装置1,4、主記憶装置2,
5、通話路制御211装置3.6、共通主記憶装置7で
構成され、代表口11G1の加入者AとCを中央制tl
lWil 1の制御下に収容し、代表口1!1lG1の
加入者Bを中央制御装置4の制御下に収容している。
This multiprocessor electronic switching system has two processors, central controllers 1 and 4, main memory 2,
5. It is composed of a communication path control 211 device 3.6 and a common main storage device 7, and centrally controls subscribers A and C of the representative port 11G1.
The subscriber B of the representative port 1!11G1 is accommodated under the control of the central control unit 4.

第3図(1) 、 (2) 、 (3)はこの次空加入
回線の検出方法の代表例を示す図で、それぞれノーマル
Figures 3 (1), (2), and (3) are diagrams showing typical examples of the method of detecting this next idle additional line, and are respectively normal.

サーキュラ、ユニフォームランダム方式である。It is a circular, uniform random method.

後者の2つの方式はサーキュラ方式の中の最初の着信加
入回線を決定する方法を規定している。
The latter two schemes specify how to determine the first incoming subscriber line in a circular scheme.

ノーマル検出方式を採用した場合、加入回線Δが空状態
でないときには次に加入回線Bの空塞状態を検出する必
要がある。加入回線Bの空塞情報は主記憶装置5に存在
し、この検出要求はデータバス8を経由して中央制御装
置4に制御を渡すことになり、このとき中央制御211
装置1は一時的な持ち状態になり、中央υ制御装置4か
ら応答が帰ってくるまでは処理が中断することになる。
When the normal detection method is adopted, when the subscriber line Δ is not in an empty state, it is necessary to detect whether the subscriber line B is idle or busy. The idle/busy information of the subscriber line B exists in the main storage device 5, and this detection request passes control to the central controller 4 via the data bus 8. At this time, the central controller 211
The device 1 enters a temporary hold state, and processing is suspended until a response is returned from the central υ control device 4.

(発明が解決しようとする問題点) 上述した従来のマルチプロセッサ電子交換システムにお
ける代表回線選択処理ではAとBの空状態を知るために
2つのプロセッサ間で空か否かの情報を受は渡すことに
よって着信可能な加入回線を検出することが起り得る。
(Problems to be Solved by the Invention) In the representative line selection process in the conventional multiprocessor electronic switching system described above, in order to know the free status of A and B, the receiver passes information on whether the lines are free or not between the two processors. It is possible to detect a subscriber line that can be terminated by this.

現在のように多種多様な交換サービスが電子交換システ
ムに要求されるようになると、それにともなうソフトウ
ェアの生産が比例的に増大してゆく一方で、各中央制御
装置の処理スピードが有限であることからシステムの持
つ処理能力が非常に重要な問題として存在し続けること
になる。ところで前記のような場合、代表回線選択!l
a理という1つの処理の中で異なるプロセッサとの通信
を必要とすることは代表加入者に含まれる加入回FIl
数が多いほど処理時間に大きく影響を与えることになる
As a wide variety of exchange services are now required of electronic exchange systems, the production of software will increase proportionally, but the processing speed of each central control unit is limited. The processing power of the system will continue to be a very important issue. By the way, in the above case, select the representative line! l
The need for communication with different processors in one process called a processing is due to the subscription circuit FIl included in the representative subscriber.
The larger the number, the greater the impact on processing time.

本発明の目的は上記の欠点を解決し、1つの代表加入者
の回線の中で?!数の中央制御装置下に首かれる加入回
線のうち着信可能な回線を検出するための処理時間を最
小にする代表回線選択方式を提供することである。
The purpose of the present invention is to solve the above-mentioned drawbacks and to solve the problems within one representative subscriber's line. ! It is an object of the present invention to provide a representative line selection method that minimizes the processing time for detecting a line capable of receiving a call from among subscriber lines connected under a central control unit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のマルチプロセッサ電子交換システムにおける代
表回1i13f!択処理方式は、システムの共通記憶装
置上にシステム配下の全代表加入回線の空塞状態をおき
、代表回線選択処理時、最初に着信要求のあった中央制
御装置が直接共通記憶装置の空塞状態を走査して空加入
回線を検出するものである。
Representative times 1i13f in the multiprocessor electronic switching system of the present invention! In the selection processing method, all representative subscriber lines under the system are placed in a vacant/blocked state on the system's common storage device, and during representative line selection processing, the central control unit that received the first incoming call request directly stores the vacant/blocked state in the common storage device. It scans the status and detects idle subscriber lines.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の代表団m1選択処理方式が適用された
マルチプロセッサ電子交換システムの一実施例のブロッ
ク図、第2図は第1図の電子交換システムにおける代表
回線の構成要素を示す図である。
FIG. 1 is a block diagram of an embodiment of a multiprocessor electronic switching system to which the delegation m1 selection processing method of the present invention is applied, and FIG. 2 is a diagram showing the components of a representative line in the electronic switching system of FIG. It is.

本実施例においては、加入回線A、B、Cの空塞状態は
各中央制御装置と直結している共通主記憶装置7の中に
存在している。
In this embodiment, the idle/busy status of subscriber lines A, B, and C exists in the common main memory 7 directly connected to each central control unit.

したがって、ある呼が代表回線G1の加入者Aに対して
着信要求をしたとき、システムは中央制御!表装置に処
理を委ねる必要がなく、直接共通主記憶装置7の空塞状
態を走査することで、加入日nAが空でない場合、加入
回線Bに着信可能か否かを決定出来る。
Therefore, when a call is requested to be received by subscriber A on representative line G1, the system is centrally controlled! There is no need to entrust the processing to the table device, and by directly scanning the common main storage device 7 for the empty/busy state, it can be determined whether or not a call can be received on the joining line B if the joining date nA is not empty.

このことは全ての空加入回線検出方法に適用出来るもの
で、汎用性が高い。また、共通主記憶装置7に全代表加
入回線の空塞状態を保持するために各通話路制御IIV
R1!3.6からの中央制御装置1゜4に対する発呼情
報などの加入者状態遷移を逐次共通主記憶Vi17に保
持しておく。
This can be applied to all methods of detecting idle subscriber lines, and is highly versatile. In addition, in order to maintain the idle state of all representative subscriber lines in the common main storage device 7, each call path control IIV
Subscriber state transitions such as call information from R1!3.6 to the central control unit 1.4 are sequentially held in the common main memory Vi17.

(発明の効果〕 以上説明したように本発明は、マルチプロセッサ電子交
換システムの共通記憶装置に全代表加入回線の空塞状態
を持つことにより、呼の代表回線着信時において、異な
るプロセッサとの通信の必要のない空加入回線検出処理
が出来、さらに着信加入回線の空加入回線検出方法がど
のような場合であっても適用出来、これらのことにより
代表回線選択処理に要する時間が削減され、システムと
しての処理効率を向上させることが可能となる効果があ
る。
(Effects of the Invention) As explained above, the present invention has the vacant status of all representative subscriber lines in the common storage device of a multiprocessor electronic switching system, so that when a call arrives on the representative line, communication with different processors is prevented. It is possible to perform empty subscriber line detection processing without the need for a This has the effect of making it possible to improve processing efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の代表回線選択処理方式が適用されたマ
ルチプロセッサ電子交換システムの一実施例のブロック
図、第2図は第1図の交換システムにおける代表回線の
構成要素を示す図、第3図は空加入回線検出方法の代表
例を示す図である。 1.4・・・中央制御装置、2.5・・・主記憶装置、
3.6・・・通話路制御装置、7・・・共通主記憶装置
、8・・・データバス。
FIG. 1 is a block diagram of an embodiment of a multiprocessor electronic switching system to which the representative line selection processing method of the present invention is applied; FIG. 2 is a diagram showing the components of the representative line in the switching system of FIG. 1; FIG. 3 is a diagram showing a typical example of a method for detecting an idle subscriber line. 1.4...Central control unit, 2.5...Main storage device,
3.6... Communication path control device, 7... Common main storage device, 8... Data bus.

Claims (1)

【特許請求の範囲】[Claims] マルチプロセッサ交換システムにおいて、システムの共
通記憶装置上にシステム配下の全代表加入回線の空塞状
態をおき、代表回線選択処理時、最初に着信要求のあっ
た中央制御装置が直接共通記憶装置の空塞状態を走査し
て空加入回線を検出するマルチプロセッサ電子交換シス
テムにおける代表回線選択処理方式。
In a multiprocessor switching system, all representative subscriber lines under the system are placed in an empty/busy state on the system's common storage, and during representative line selection processing, the central control unit that received the first incoming call request directly fills the common storage with an empty block. A representative line selection processing method in a multiprocessor electronic switching system that scans the busy state and detects idle lines.
JP18890386A 1986-08-11 1986-08-11 Representative line selection and processing system in multi-processor electronic switching system Pending JPS6343489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18890386A JPS6343489A (en) 1986-08-11 1986-08-11 Representative line selection and processing system in multi-processor electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18890386A JPS6343489A (en) 1986-08-11 1986-08-11 Representative line selection and processing system in multi-processor electronic switching system

Publications (1)

Publication Number Publication Date
JPS6343489A true JPS6343489A (en) 1988-02-24

Family

ID=16231898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18890386A Pending JPS6343489A (en) 1986-08-11 1986-08-11 Representative line selection and processing system in multi-processor electronic switching system

Country Status (1)

Country Link
JP (1) JPS6343489A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0746638A (en) * 1993-07-29 1995-02-14 Nec Corp Method for controlling connection of incoming call to representative number subscriber and equipment therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182983A (en) * 1982-04-21 1983-10-26 Nec Corp Multiprocessor exchange

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182983A (en) * 1982-04-21 1983-10-26 Nec Corp Multiprocessor exchange

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0746638A (en) * 1993-07-29 1995-02-14 Nec Corp Method for controlling connection of incoming call to representative number subscriber and equipment therefor

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