JPS634336A - Arithmetic circuit for coefficient multiplication - Google Patents

Abstract

PURPOSE:To constitute an arithmetic circuit for coefficient multiplication which extends output data bit length without deteriorating an arithmetic result by providing plural read-only memories for storing the arithmetic result. CONSTITUTION:The circuit consists of a terminal 11 which receives 8-bit input data, a coefficient address generating circuit 12, an output terminal 13 which outputs 12-bit output data, a bus 15 which transmits the high-order 4 bits of the input data to ROMs 16 and 17 and the low-order 4 bits to a ROM 18, ROMs 16-18 which store the arithmetic result determined by input data information and coefficient information, and a 12-bit adding circuit 19 which adds the outputs of the ROMs 16-18 together. The output of the ROM 16 represents the high- order 8 bits of the 12 bits and the sum of the outputs of ROMs 17 and 18 represent the low-order 4 bits. Consequently, 8-bit data processing is accurately expanded to 12-bit data processing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an arithmetic circuit that outputs information obtained by multiplying a series of input data having a required bit length by a desired coefficient as output data in a digital system. It is.

[Prior Art] Fig. 2 is a schematic diagram of a conventional arithmetic circuit of this type disclosed in, for example, Japanese Patent Laid-Open No. 55-163983. In Fig. 2, 1 indicates an input terminal for 8-bit data. , 2 is a coefficient address generation circuit, 3 is a coefficient ROM, 4 is a multiplier,
5 is an 8-bit data output terminal.

Next, the operation will be explained. Assume now that 8-bit input data is supplied to input terminal 1 and arrives at multiplier 4. Then, the coefficient address generation circuit 2 generates a predetermined address in accordance with this timing, and the coefficient ROM 3
An 8-bit coefficient corresponding to the input data is read from. Thereafter, the multiplier 4 multiplies the input data of the input terminal 1 by the corresponding 8-bit coefficient read from the coefficient ROM 3. In this way, 8-bit operation output data is output from the output terminal 5 of the multiplier 4.

[Problems to be Solved by the Invention] However, in such a conventional arithmetic circuit, since the circuit is configured as described above, the multiplier 4 has a complicated circuit configuration.
In addition, there are problems such as the accuracy of the lower bit part of the calculation result becomes poor.

This invention was made to solve the above-mentioned problems, and by skillfully combining multiple readout memories with relatively small memory capacity and an adder circuit, calculation results can be obtained with a simple circuit configuration. To provide an arithmetic circuit for coefficient multiplication which can extend the bit length of output data without causing any deterioration.

[Means for Solving the Invention] A coefficient multiplication arithmetic circuit according to the present invention includes a plurality of read memories for storing arithmetic results determined from input data information and coefficient information, and reads the input data divided into bit lengths. is supplied to the input address of each readout memory, and is provided with an adder circuit that adds and outputs the arithmetic results from each readout memory.

[Function] In the coefficient multiplication arithmetic circuit according to the present invention, arithmetic results determined from input data information and coefficient information are stored in a plurality of read memories, and input data divided by bit length is stored in a plurality of read memories. By supplying the signal to the input address of each read memory, the required storage contents are output from each read memory, and then these memory outputs are added in an adder circuit and output as output data.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. 1st
In the figure, 11 is an input terminal that receives 8-bit input data, 12 is a coefficient address generation circuit, 13 is an output terminal that outputs 12-bit output data, 14 is a data bus that transmits the upper 4 bits of input data, and 15 is an output terminal that outputs 12-bit output data. is a data bus that transmits the lower 4 bits of input data, 16,
17 and 18 are ROMs (read-only memories) each having a storage capacity of IK x 8 bits, and these ROM1
6.17.18 are calculation results B 01. determined from input data information and coefficient information, respectively. Bo2. B.

(The contents of Box + Box l BO3 will be described later) are stored. Further, 19 is a 12-bit adder circuit, and in this adder circuit 19, each ROM 16, 17°1
The memory contents from 8 are added and the result of this addition is output from the output terminal 13 as output data.

Next, the operation will be explained in detail. Now, the 8-bit input data A0 appearing at the input terminal 11 is set as Ao” (at+as
tas+84+ai+az+at+ao). Also, this input data A. The upper 4 bits of ``AOL'' and the lower 4 bits of ``AOX'' (ailasla
sla4)A02" (a31a21ai!ao). Then, this divided input data A (,1 passes through the data bus 14, and the other divided input data A.2 passes through the data bus 1.
5, 8-bit ROM 16°17.1 at the same time
8 input addresses. Further, the coefficient to be multiplied by Ao is specified by the coefficient address generation circuit 12. Now let this coefficient be α. For simplicity, it is assumed that 0 α≦1.

By the way, the coefficient address specified by the coefficient address generation circuit 12 is A1111, A02 is 8, bit ROM1 is
It is synchronized with the time of arrival at the input address of 6, 17, and 18. Then, in the bit ROM 16 at 8, the operation result B
01 is also 8. The operation result B is stored in the bit ROM 17.
When O2 is 8, the operation results BQ3 are stored in the bit ROM 18, and when the address is accessed, each operation result is read out. Here, Bu engineering, B...
The contents of Bo are as follows.

Bo,: I N T [AoxαX24]BO2=I
NT [[INT [:A,,aX2']I N
T [Ao1α X 24 pieces x2']/2' pieces 3
,, = I N T [AO2Xα, however, I
NT[X] represents the integer part of X.

Therefore, the calculation result B stored in the ROM 16
o1 represents the upper 8 bits of the 12 bits 1 of A0α, and is the calculation result B0 stored in the ROM 17.
2 and the calculation result BO3 stored in the ROM 18 (Box + BO3) represents the lower 4 bits of the 12-bit representation of Aoa, so these calculation results B
l, 1. B.2. BO, 12-bit addition circuit 19
By performing the addition, the desired 12-bit output data can be output from the output terminal 13.

In this way, in this embodiment, three ROMs 16 to 18
By skillfully combining the adder circuit 19 and the adder circuit 19, it is possible to expand the bit length of the output data to 12 bits with a simple circuit configuration and without degrading the arithmetic result.

Therefore, if an arithmetic circuit with such a configuration is applied to the vertical interpolation circuit of a digital convergence correction device for a high-definition television, 8-bit data processing can be expanded to 12-bit data processing with high precision. Smoothing of the convergence current in the vertical direction is promoted. As a result, the negative influence of convergence correction on scanning line scanning can be eliminated.

[Effects of the Invention] As described above, according to the present invention, a plurality of readout memories and addition circuits are skillfully combined, so that the circuit structure is simple and the accuracy of the calculation results is not reduced. This has the effect of increasing the number of output bits, that is, extending the output bit length.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a coefficient multiplication arithmetic circuit according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional coefficient multiplication arithmetic circuit. In the figure, 11-input terminal, 12-coefficient address generation circuit, 13-output terminal, 14.15-data bus, 16-
, 17.18-ROM (read memory), 19-addition circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an arithmetic circuit that outputs information obtained by multiplying input data having a required bit length by a desired coefficient as output data,
A plurality of readout memories are provided for storing calculation results determined from the input data information and coefficient information, and the input data divided into bit lengths is supplied to the input address of each readout memory. ,
An arithmetic circuit for coefficient multiplication, characterized in that an adder circuit is provided for adding and outputting the arithmetic results from each of the read memories.