JPS6343016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an adaptive echo cancellation device using a learning identification method, and more particularly to an adaptive correction calculation method for an estimated echo path response.

[Technology background]

Generally, long-distance telephone lines, etc. have two wires,
In order to prevent part of the signal transmitted from the partner station from leaking at the 4-wire switching unit and being sent back to the partner station, an echo canceling device is installed in the 4-wire side circuit as shown in Figure 1. It has been inserted. Such an echo canceling device uses a learning identification method to estimate the impulse response determined by the absolute delay of the echo returning from the installed station to the subscriber side via the echo path and the transfer characteristics of the echo path. An adaptive echo cancellation device is used. A schematic configuration of such an adaptive echo canceling device is shown in FIG.

[Conventional technology and problems]

In the conventional adaptive echo cancellation device, the calculation algorithm for adaptively correcting the estimated value of the impulse response h of the echo path using the learning identification method is h^ _j+1 = h^ _j +Δh^ _j = h^ _j +αe _j x _j / | x _j | ² is used. A circuit configuration for implementing this is shown in FIG. In FIG. 3, reference numeral 1 denotes a transmitting section of the opposite station, 2 a receiving section of the opposite station, 3 an echo path, and 4 an adaptive echo canceling device.

In the echo canceling device 4 in Fig. 3, y^ _j = h^ _j *x _j (y _j : estimated echo path response, * is convolution operation) e _j = y _j −y _j h within one sample period. It is necessary to complete a series of processes ^ _j+1 = h^ _j +Δh^ _j , and high-speed processing is required.

Therefore, a high-speed arithmetic circuit adapted for high-speed processing,
It is necessary to use high-speed circuit components such as a high-speed A/D converter and a high-speed D/A converter in the device, which has the disadvantage of increasing costs and making the circuit relatively large.

[Purpose of the invention]

In view of the above-mentioned problems, an object of the present invention is to improve the adaptive correction calculation method in an adaptive echo canceling device, thereby reducing the amount of processing per sample period and adjusting the required internal processing speed as necessary. The purpose is to make it possible to alleviate the situation.

[Structure of the invention]

In order to achieve the above object, the present invention estimates the echo path response h using a learning identification method, obtains the expected echo signal from the input signal time series X, and subtracts it from the actual echo signal. In the adaptive echo cancellation device, let j be an integer and i, k,
When l and m are natural numbers (i≦k<l<m), a first register stores an input signal time series with a sampling period T, a second register stores an estimated echo path response, a first delay circuit that delays the output of the first register by a time kT;
a second delay circuit that delays the output of the delay circuit by a time (m−k)T; and at time jT, the output of the first register X register output
A first calculation circuit that calculates the estimated echo signal Y^j from hj by convolution calculation, and at time jT,
a second arithmetic circuit that calculates a cancellation residual signal ej-i by subtracting the output Y^j-i of the first arithmetic circuit at time (j-i)T from the actual echo signal; , the time (j--
k) Sum of squares of input signal time series up to T Σ |
The third arithmetic circuit that calculates X〓j−k｜ ² and the time jT
, from the output ej-l of the second arithmetic circuit at time (j-l)T and the output Σ|X〓j-l| ² of the third arithmetic circuit at time (j-l)T. A fourth arithmetic circuit that calculates the correction of the estimated echo path response, Δj−l=αej−l/|X〓j−l| ² , where α is a correction coefficient (0<α<2), and the time jT In,
Output Δj-m of the fourth arithmetic circuit at time (j-m)T and output X of the first register at time (j-m)T after passing through the first and second delay circuits 〓j−m and the output hj of the second register at time jT to the next time (j
+1) A fifth arithmetic circuit that calculates the estimated echo path response at T, hj+1=hj+Δj−m・X〓j−m, and stores it in the second register, and pipelines the processing in each of the circuits. There is provided an adaptive echo cancellation device characterized in that processing for one echo cancellation is performed in mT cycles.

[Embodiments of the invention]

Before describing embodiments of the present invention, the prior art adaptive echo canceling device shown in FIG. 1 described above will be described for comparison. An operating time chart of the apparatus of FIG. 3 is shown in FIG. 5a. In the echo canceling device 4 of FIG. 3, an input signal is encoded in an A/D converter 41 and stored in an x〓 register 42 as an input signal time series x _j . x at time jT = output x of register 42 = _j and h register 43
The output h _j of is given by the convolution circuit 45 as y^ _j =Σx _ji
h _i is calculated (), and an analog output y is obtained by the D/A converter 49 from the estimated echo output y^ _j (). In the analog subtraction circuit 50, the estimated value y is subtracted from the actual echo output y, and the residual signal e=
y−y^ is obtained (). This residual signal e is A/
It is converted into a digital output e _j in the D converter 48 (). On the other hand, in the arithmetic circuit 44, |x〓 _j
| ² is calculated, and in the arithmetic circuit 47, Δj=αe _j /
|x〓 _j | ² is obtained (). h register correction circuit 4
_{6 ,} time _{( j} +
1) An estimated value h _j+1 at T is obtained ().

In the prior art echo canceling device shown in Fig. 3,
It is necessary to perform the above-mentioned series of serial processing during one sample period T (for example, 125 μs), which requires an expensive high-speed arithmetic circuit, a high-speed A/D converter, and a high-speed D/A converter.

An adaptive echo cancellation system according to one embodiment of the present invention is shown in FIG. Corresponding parts in FIG. 4 have the same reference numerals as in FIG. 3. Fourth
In the echo canceling device shown in the figure, the series of processes that needed to be completed within one sample period in the device shown in FIG. 3 are all completed within one sample period by pipelining. do it. Note that the delay circuits 51 and 52
This is to prevent the data sampling position from shifting.

The operation time chart of each part in the apparatus of FIG. 4 is shown in b to g of FIG. 5. In this embodiment, the series of processes that needed to be completed within one sample period in a of FIG. Since it only needs to be completed within a certain period of time, the processing speed is significantly reduced. The input x〓 _j at time jT is, , 〓,
After processing 〓〓, 〓〓, at time (j+6)T
Generate h _j+6 . Therefore, at time jT, the estimated echo is calculated by the calculation h _j+1 = h _j +Δ _j-5 x〓j-5=h _j +αe _j-1 / |x _j-5 | ² x〓 _j-5. Modify road response. Compared to the original correction formula h _j+1 = h _j + Δ _j x〓 _{j =} h〓 _j + αe _j ／｜x _j | ² It's just getting smaller. Therefore, the method of the present invention has no effect on the convergence conditions of the learning identification method. In addition, the actual convergence of h requires several thousand
Since the number of corrections is made twice, the increase in the number of corrections by five does not pose any practical problem. As described above, according to the present invention, it is possible to significantly reduce the internal processing speed without causing any practical disadvantage to the convergence conditions or the number of convergence operations.

〔Effect of the invention〕

According to the present invention, it is possible to significantly reduce the required internal processing speed in an adaptive echo cancellation device, thereby making it possible to use low-cost, low-speed circuit components.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an application example of an adaptive echo canceling device, FIG. 2 is a diagram showing a general configuration of an adaptive echo canceling device, and FIG. 3 is a diagram showing a conventional adaptive echo canceling device. The circuit diagram, FIG. 4 is a circuit diagram of an adaptive echo canceling device as an embodiment of the present invention, and FIG.
5 is a diagram showing an operation time chart of the apparatus of FIGS. 3 and 4; FIG. Explanation of symbols, 1: Transmitter, 2: Receiver, 3: Echo path, 4: Echo cancellation device, 41: A/D converter,
42: x register, 43: h register, 44: arithmetic circuit, 45: convolution circuit, 46: correction circuit, 47: arithmetic circuit, 48: A/D converter, 4
9: D/A converter, 50: Analog subtracter, 5
1, 52: Delay circuit.

Claims (1)

[Claims] 1. In an adaptive echo canceling device that estimates an echo path response h using a learning identification method, obtains an expected echo signal from an input signal time series X, and subtracts it from an actual echo signal. , j is an integer, i, k, l, m are natural numbers (i≦
k<l<m), a first register 42 that stores the input signal time series with a sampling period T, a second register 43 that stores the estimated echo path response, and a a first delay circuit 51 that delays the output by a time kT; a second delay circuit 52 that delays the output of the first delay circuit by a time (m-k)T; Said first
a first arithmetic circuit 45 that calculates an estimated echo signal Y^j by a convolution operation from the output X〓j of the register and the output hj of the second register at the time jT; the output of the first arithmetic circuit at time (ji)T from
By subtracting Y^j−i, the canceled residual signal ej−i
a second arithmetic circuit 50 that calculates the time (j) based on the output X〓j−k of the first register at time (j−k)T that has passed through the first delay circuit at time jT; -k)T
The sum of the squares of the input signal time series up to Σ｜X〓j−k
| ² , and at time jT, the output ej-l of the second arithmetic circuit at time (j-l)T and the time (j-
l) Output Σ of the third arithmetic circuit at T |
Calculate ^the correction of ^the estimated echo path response from a fourth arithmetic circuit 47; at time jT, the output Δj-m of the fourth arithmetic circuit at time (j-m)T;
and the time (j-
m) Output of said first register at T
m and the output hj of the second register at time jT, the estimated echo path response at the next time (j+1)T, hj+1=hj+Δj−m・X〓j−m, is calculated and stored in the second register. A fifth arithmetic circuit 46 for storage is provided, and by pipeline processing the processing in each of the circuits, the processing for one echo cancellation is reduced to mT.
An adaptive echo canceling device characterized in that it performs a periodic response.