JPS6342792B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that sequentially reads musical score data stored in a memory and uses it for performance assistance such as displaying key press positions, and in particular, the present invention relates to an electronic musical instrument that sequentially reads out musical score data stored in a memory and uses it for performance assistance such as displaying key pressed positions, and in particular, for each predetermined note on the musical score or Data read from the memory and key press data from the keyboard are compared at regular intervals, and data read from the memory is continued only when a key press match is detected. This is designed to provide a performance assisting effect.

2. Description of the Related Art Conventionally, electronic musical instruments have been proposed that assist manual performance practice by sequentially reading musical score data stored in a memory, displaying key press positions, and performing automatic performance. However, in this type of electronic musical instrument, data reading from the memory proceeds independently of the progress of manual performance, so the player has to perform according to the key press position display and automatic performance. It is difficult to perform, and beginners in particular are often left out of the key press position display and automatic performance, making it difficult to achieve a sufficient performance practice effect.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel electronic musical instrument that can control the reading of musical score data from a memory in accordance with the progress of manual performance.

The electronic musical instrument according to the present invention compares the data read from the memory with the key press data from the keyboard every predetermined note on the musical score or every fixed period, and determines whether the key is pressed correctly. The data readout from the memory proceeds only when the key is pressed, and in the case of an erroneous key press or no key press, the data readout is, for example, temporarily stopped or progressed by going back several notes. Hereinafter, embodiments shown in the accompanying drawings will be described in detail.

FIG. 1 shows part of the content of the musical score used in the electronic musical instrument of the present invention, where M1 is the melody part,
M2 is a chord section, M3 is a bass section, and KT indicates a note serving as a key for detecting a correctly pressed key, that is, a key note. As this keynote KT, it is possible to apply a note selected in advance on the musical score, or it is possible to apply a note at the beginning of a measure at regular intervals, for example, every other measure. Keynote by way of KT
It is now possible to decide or select.

FIGS. 2 and 3 show the circuit configuration of an electronic musical instrument according to an embodiment of the present invention.

The musical score 10 has a musical note progression as illustrated in FIG. 1 corresponding to a predetermined performance piece written on its surface, and a magnetic tape on its lower surface records musical score data corresponding to a series of musical note progressions. A recording medium 10a such as the one shown in FIG.

The musical score data reading device 12 has a reception opening for receiving the musical score 10, and when the musical score 10 is inserted into the reception opening, it reads the musical score data from the recording medium 10a. Of the read data RD at this time, melody data RD ₁ is the melody memory 1 of the melody data generation circuit 14.
6, chord data RD ₂ , base data
RD ₃ and rhythm pattern data RD ₄ are stored in the chord memory 20 and base memory 2 of the automatic accompaniment section 18, respectively.
2 and the rhythm pattern memory 24, and the keynote position data _RD5 is supplied to the bar/beat memory 28 of the progress control circuit 26 and stored therein.
Note that the memories 16, 20, 22, 24, and 28 are all RAM (random access memory).
It is made up of

In the start/stop control circuit 30,
When the start switch 32 is turned on to start the operation, the on signal at this time is sent to the differentiating circuit 3.
4, it rises in synchronization with the system clock signal φ and is differentiated and converted into a start signal ΔST. Also,
Since the on signal of the switch 32 is designed to set the R-S flip-flop 36, a read control signal is generated from the inverter 38, which receives the output Q of the flip-flop 36, so as to maintain the "0" level during the read period. be done. This readout control signal is sent to the address counter 40 of the melody data generation circuit 14, the address counters 42 and 44 of the automatic accompaniment section 18, and the progress control circuit 26.
are supplied to the address counter 46 of
Each counter is reset and released.

In the melody data generation circuit 14, when the address counter 40 is reset, the start signal ΔST is supplied to the counter 40 via the OR gate 48, so that the counter 40 is set to 1.
The count advances and the first read address signal is supplied to the melody memory 16. Therefore, melody data corresponding to the first note (which is also the first keynote) is read out from the memory 16. Here, the data format of the read data RD ₁ from the memory 16 is as shown in the figure, p-bit key code data (including octave code and note code, representing pitch) KC, and q-bit note length data. It includes LC, 1-bit keynote bit KB, and last bit FB which is the most significant bit (MSB), and data RD ₁
The number of parallel bits is p+q+2. In addition, the keynote bit KB is "1" for data corresponding to the keynote, and the end bit FB is "1" for the end data, but for other data, both KB and FB are "0". .

Of the melody data first read out from the memory 16, the note length data LC converts the start signal ΔST from the OR gate 48 into the D-flip-flop 50.
The latch circuit 52 latches the clock signal φ in response to a signal obtained by delaying the clock signal φ by one bit time. The first note length data LC latched by the latch circuit 52 is combined with key code data KC and key note bits KB to form melody data MD.
On the other hand, it is supplied to the latch circuit 54.

Thereafter, when the first correctly pressed key detection signal KOT is generated, this signal KOT is supplied to the counter 40 via the OR gate 48, and the counter 40 is incremented by one count. Therefore, from memory 16, 2
The melody data corresponding to the th note is read out. The melody data (KC and LC) read from the memory 16 in this way precedes the original key press timing by one note. Also, at the same time that the melody data corresponding to the second note is read out from the memory 16, the latch circuit 54 is activated.
In response to the correct key press detection signal KOT from the OR gate 48, the first note length data LC from the latch circuit 52 is latched. Also, since the signal KOT at this time is supplied to the latch circuit 52 as the load signal LD via the flip-flop 50, the latch circuit 52
2 is slightly delayed (1 bit time of clock signal φ) from the latch timing of the latch circuit 54.
Latch the wavelength data LC. The second note length data latched by the latch circuit 52 is sent out as part of the melody data MD.

Further, the first code length data latched by the latch circuit 54 is supplied to the comparator 56 as one comparison input, and the other comparison input of the comparator 56 is as follows.
Counter 5 that counts the tempo clock signal TCL
8 counting outputs are provided. Here, counter 5
8 is an OR gate 60 in synchronization with the start signal ΔST.
After being reset by the detection reference timing signal REFT from
It is reset in response to the signals supplied through OR gates 48 and 60, and then begins counting.

When the counter 58 counts the tempo clock signal TCL and reaches the count value corresponding to the latch data of the latch circuit 54, that is, the first note length data,
Comparator 56 generates an initial match signal EQ. This coincidence signal EQ is supplied to the counter 40 via the OR gate 48, so the counter 40 increments by one count, the melody data corresponding to the third note is read out from the memory 16, and at the same time the latch circuit 54, the second note length data is latched, and a little later, the latch circuit 52 receives the third note length data.
The th note length data is latched. Also, the output signal of the OR gate 48 at this time is the output signal of the OR gate 60.
Since the counter 58 is reset via the clock signal, the counter 58 receives the clock signal again after this reset.
Count TCL. Then, when the counted value of the counter 58 reaches the value corresponding to the second mark length data of the latch circuit 54, the comparator 56 generates the match signal EQ as before, and the fourth mark length data is output from the memory 16. The melody data corresponding to the musical note is read out, and the same readout operation is repeated thereafter.

Then, from memory 16, the last bit is
End data with FB="1" is read out, and at this time, note length data corresponding to the last note is latched in the latch circuit 54. Therefore, after the end detection circuit 62 detects the signal of end bit FB="1" and makes the AND gate 64 conductive with the detection output,
When counter 58 reaches a count value corresponding to the last symbol length data of latch circuit 54, comparator 56 generates a final match signal EQ. This matching signal EQ is
The end signal FIN is supplied to the flip-flop 36 of the start/stop control circuit 30 via the AND gate 64 and reset.
Read control signal PLY from inverter 38 is “1”
Then, the counters 40, 42, 44, and 46 are reset, thereby completing the series of data read operations.

Of the melody data MD from the melody data generation circuit 14, p-bit key code data
KC is supplied to a keyboard performance section 66 and a correctly pressed key detection circuit 68, and q-bit note length data LC and 1-bit keynote bit KB are supplied to a correctly pressed key detection control circuit 70.

In the keyboard performance section 66, when the display select switch 72a is turned on, the display control circuit 72 selectively lights up the display element 74a, such as a lamp or light emitting diode, provided for each key of the keyboard 74 in accordance with the key code data KC. By doing so, the key to be pressed, that is, the position of the key to be pressed, is visually displayed. In this case, on the keyboard 74, the key code data KC is generated one note ahead of the original key press timing, as described above, so the key press position corresponding to the preceding note is displayed. Therefore, the player can perform key press operations that follow the displayed key press position, and can practice key presses efficiently.

The key switch circuit 76 includes a large number of key switches each linked to a large number of keys on the keyboard 74, and when a key is pressed on the keyboard 74, key code data KC' indicating the pitch of the pressed key is generated. Any key-on signal AKO indicating that a key has been pressed
and occurs. The key code data KC' and any key-on signal AKO are supplied to a correctly pressed key detection circuit 68, and are also supplied to a melody sound forming circuit 78.

The melody sound forming circuit 78 is key code data
A melody musical tone signal is electronically synthesized based on KC' and any key-on signal AKO, and this melody musical tone signal is supplied to an output amplifier 82 via a resistor 80. Further, the output amplifier 82 amplifies the input musical tone signal and supplies it to the speaker 84. Therefore, when a melody is played on the keyboard 74,
The melody sound that corresponds to the performance operation is emitted from speaker 8.
It is played from 4.

In the correct key press detection circuit 68, the key code data KC from the memory 16 and the key switch circuit 7
A comparator 86 is provided for comparing the key code data KC' from 6.
generates a match signal EQ when the input data KC and KC' match (the pitches match). This coincidence signal EQ is passed through the select gate 9 through the AND gate 88 which becomes conductive in response to the any key on signal AKO.
0 is supplied to one fixed contact a. The other fixed contact b of the select switch 90 is supplied with an any key-on signal AKO. Select switch 9
0 is used to select whether to detect a correctly pressed key when only the key press timing matches, or whether to use a correct key press when both the key press timing and pitch match, and when switching to contact b, Correctly pressed key detection is performed when only the key press timing matches, and when switching to contact a, correctly pressed key detection is performed when both the key press timing and pitch match.

Any key-on signal AKO or match signal EQ from select switch 90 is supplied to one input terminal of AND gate 92, and the output Q of R-S flip-flop 94 is supplied to the other input terminal of AND gate 92. The flip-flop 94 is set by the output signal of an OR gate 96 which receives the detection start signal DS from the correctly pressed key detection control circuit 70 and the start signal ΔST from the start/stop control circuit 30, and its reset input. A signal KOT obtained by deriving the output of AND gate 92 from D-flip-flop 98 in response to clock signal φ is supplied.

Now, assuming that the start signal ΔST is generated, the flip-flop 94 is set by the start signal ΔST, and the flip-flop 94 is set by the start signal ΔST.
4 generates a detection reference timing signal REFT consisting of its output Q. This signal REFT is
Since the AND gate 92 is made conductive, when the cutest any key-on signal AKO or the first match signal EQ is sent out via the select switch 90, the signal
AKO or EQ is supplied to flip-flop 98 through AND gate 92,
From 8 onwards, the first correctly pressed key detection signal KOT is generated in synchronization with the clock signal φ. In this way, the first correctly pressed key detection signal KOT is sent to the flip-flop 94.
It is generated on the condition that ΔST is set not by the detection start signal DS but by the start signal ΔST. Since this first correctly pressed key detection signal KOT resets the flip-flop 94, the detection reference timing signal
REFT returns from “1” to “0”, thereby
AND gate 92 becomes non-conductive. Therefore, the first correctly pressed key detection signal KOT returns to "0" with a delay of one bit time of the clock signal φ from the time of its generation, and the flip-flop 94 is released from reset.

Thereafter, when the detection start signal DS is generated in response to the second keynote, the flip-flop 94 is set in response to the signal DS and generates the detection reference timing signal REFT. The flip-flop 94 continues to be in the set state until the flip-flop 98 generates the second correctly pressed key detection signal KOT based on the correctly pressed key operation corresponding to the second keynote. 2nd correctly pressed key detection signal
When KOT is generated, the flip-flop 94 is reset in response to the signal KOT, and is then released from reset to prepare for a correctly pressed key detection operation based on the detection start signal DS corresponding to the next third keynote. Similarly, every time the detection start signal DS is generated in response to a keynote, the flip-flop 94 is set to enable the correct key press detection operation.

The correct key press detection control circuit 70 is for generating a detection start signal DS in response to a keynote.
A selection switch 100 is provided for selecting whether to set the keynote as a note at the beginning of every other measure or as a note predetermined on the musical score. This select switch 100 is connected to the select switch 102 of the advancement control circuit 26 by a mechanical coupling MC.
Therefore, the operation of the circuits 26 and 70 can be divided into two cases: when the switches 100 and 102 are switched to the fixed contact a side, and when the switches 100 and 102 are switched to the fixed contact b side. I will explain. However, in either case, the detection start signal generation operation corresponding to the first keynote is not performed, so the operation corresponding to the second and subsequent keynotes will be explained.

When the switches 100 and 102 are switched to the fixed contact a side as shown in the figure, the note at the beginning of every other measure is applied to the keynote as shown in FIG. The detection start signal DS is generated periodically approximately every two bars. That is, in the progress control circuit 26,
The beat counter 104, which has a counting capacity for two measures, is reset in response to the first correctly pressed key detection signal KOT supplied via the switch 102, and then obtained by inverting the detection reference timing signal REFT with the inverter 106. The temp clock signal TCL supplied from the variable tempo oscillator 110 is counted through the AND gate 108 which is made conductive by the signal, and beat data BD consisting of the counted output is supplied to the decoder 112 of the correct key press detection control circuit 70. Here, the decoder 112 outputs the count value immediately before the beat counter 104 reaches the count value for two measures, for example, "62".
Since the output signal = "1" is generated by decoding the beat data BD corresponding to ”, the decoder 112 outputs the first output signal = “1”.
This output signal is supplied to the correctly pressed key detection circuit 68 via the switch 100 as the first detection start signal DS. The time point at which the DS of this first detection start signal is generated is just before the end of the second bar, and slightly ahead of the timing at which the second keynote should be pressed.

When the first detection start signal DS is generated,
As described above, since the detection reference timing signal REFT becomes "1", the AND gate 108 becomes non-conductive and the beat counter 104 stops advancing. At this time, the correctly pressed key detection circuit 68 performs a detection operation based on the first detection start signal DS, but when the second correctly pressed key detection signal KOT is generated as a result, the detection reference timing signal REFT is set to “ 0"
become. Therefore, after the beat counter 104 is reset by the second correctly pressed key detection signal KOT,
The tempo clock signal TCL from the AND gate 108 which is conductive is counted by the signal obtained by inverting the signal REFT="0" by the inverter 106. Then, when the count value of the beat counter 104 reaches "62" again, the second detection start signal DS is generated from the decoder 112, and in the same manner, the second detection start signal DS is generated.
The operation of generating the signal DS is repeated for each measure.

In addition, in the progress control circuit 26, the correctly pressed key detection signal KOT from the switch 102 is applied to the OR gate 1.
14 to the bar counter 116 as a counting input, the bar counter 116 is reset in response to the start signal ΔST and then reset to the signal ΔST.
The KOT is counted and a count output (measure data) corresponding to the number of measures is supplied to the measure display circuit 118. Here, the bar display circuit 118 is equipped with a numerical display or a lamp array display, and each time the beat counter 104 reaches a count value for one bar, a signal indicating this is also supplied. For this reason, the measure display circuit 118 visually displays the progressing measure as a numerical value or lamp row lighting length based on the measure number signals from the counters 104 and 106.

Next, switches 100 and 102 are connected to fixed contacts b
The operation when switched to the side will be described. In this case, arbitrary multiple notes on the musical score are determined as keynotes in advance, and the keynote bit KB of the melody data corresponding to these notes is also set to "1" in advance.
, and a detection start signal DS is generated in response to such a keynote. Note that in this case, unlike the case of contact a switching described above, the keynote is not limited to being determined at regular intervals, so it is preferable to determine it at different intervals.In this way, the detection start signal DS are generated at different periods.

When the melody data corresponding to the second keynote is read from the memory 16, the latch circuit 120 reads the note length data from the latch circuit 52 in response to the keynote bit KB="1" signal at this time.
Latch LC. At this time, the note length data LC latched by the latch circuit 120 is the note length data one note before the second keynote (which is also the displayed note). Also, since the signal of keynote bit KB="1" at this time sets the R-R flip-flop 122, the counter 124
is reset by the output of the flip-flop 122 = "0", and then counts the tempo clock signal TCL.

Latch output of latch circuit 120 and counter 1
The 24 count outputs are supplied to the subtraction circuit 126 as inputs A and B, respectively, and undergo subtraction processing of (A-B). The subtraction output of the subtraction circuit 126 is supplied to the comparison circuit 128, and when the value indicated by the subtraction output matches a predetermined value n, for example "2", the comparison circuit 128
Generates a match signal. This match signal is the switch 1
00 to the correctly pressed key detection circuit 68 as the first detection start signal DS. in this way,
The first detection start signal DS is generated just before the end of the length of the note one note before the second keynote, that is, slightly before the timing at which the second keynote should be pressed. The timing depends on the value of n. Note that the value of n needs to be smaller than the value corresponding to the note length of the shortest note (for example, a 16th note) to be used.

Thereafter, in the same way as described above, every time the melody data corresponding to the keynote is read out from the memory 16, the detection start signal DS is generated immediately before the end of the musical score one note before the keynote.

On the other hand, in the progress control circuit 26, the first correctly pressed key detection signal KOT is detected by the address counter 46, which has been reset by the readout control signal.
is incremented by one count, so measure/beat memory 2
Keynote position data RD ₅ indicating the 1st measure and 1st beat is read from 8, and the preset data PD
as a beat counter 104 and a measure counter 116
supplied to At the same time, the first correctly pressed key detection signal KOT is sent to the beat counter 1 via the switch 102.
04 and measure counter 106
Since the signal is supplied as PS, the beat counter 104 and the bar counter 116 are preset with data indicating the first bar and data indicating the first beat from the memory 28, respectively. And beat counter 10
4 is a tempo clock signal from the AND gate 108 which is made conductive by a signal obtained by inverting the detection reference timing signal REFT="0" by the inverter 106.
TCL is counted, and when the count value corresponding to one bar is reached, a signal indicating this is supplied to the measure display circuit 118. When the count value corresponding to two bars is reached, the carry-out output CO is sent to the OR gate 114. It is supplied to the bar counter 116 via the bar counter 116.

Here, for the sake of simplicity, if we assume that the second keynote is the note on the first beat of the third measure, the correctly pressed key detection control circuit 70 will output the second keynote as described above. The first detection start signal DS corresponds to the timing when the key should be pressed.
is generated. Then, when a second correctly pressed key detection signal KOT is generated by the correctly pressed key detection operation based on this first detection start signal DS, this signal
Since KOT increments the counter 46 by one count, the second keynote position data RD ₅ is read from the memory 28. Of the read data RD ₅ , the data indicating the first beat is preset to the beat counter 104 in response to the signal KOT, and the data indicating the third bar is preset to the bar counter 116 in response to the signal KOT, 116 performs a counting operation in the same manner as last time. After this, in the same way as above, every time the correct key press detection signal KOT is generated, data is read from the memory 28, data is preset to the counters 104 and 116, and data is set based on the preset data of the counters 104 and 116. A counting operation is performed.

Note that the bar display circuit 118 displays the progressing bar based on the bar number signals from the counters 104 and 116, as in the case of switching the contact a described above.

Next, the automatic accompaniment section 18 is set to the auto chord section 18.
A. Auto bass section 18B and auto rhythm section 1
The explanation will be divided into 8C.

First, in the autocode section 18A, chord data is read out from the chord memory 20 in response to a reading address signal consisting of the count output of the address counter 42.
RD ₂ is read. That is, after the counter 42 is reset and released by the read control signal,
When the first correctly pressed key detection signal KOT resets the R-S flip-flop 132 via the OR gate 130, the output Q of the flip-flop 132 is
In response to the output of the inverter 134 inputting "0" becoming "1", the clock signal φ from the AND gate 136 is counted by four. The first series of chord data RD ₂ is read out from the memory 20 in accordance with the count output of the counter 42 at this time. Here, the data format of the chord data _RD2 includes three sets of key code data KC and one set of note length data LC, as shown. The three sets of key code data KC each indicate the pitch of the three tones that make up the chord, and each data KC has the highest bit of "1" representing a pitch mark, and the lower p
Bits represent pitches including octave chords and note chords. Also, one set of note length data
The most significant bit of LC is "0" and represents a note length mark, and the q bits below it represent the note length.

Three sets of key code data KC each consisting of p+1 bits are sequentially supplied to the chord constituent note memory 140. When the memory 140 receives the most significant bit = "1" of the key code data KC as a load signal, it sequentially captures p-bit chord pitch data for three tones in accordance with the clock signal φ and stores them in parallel. The held data is supplied to the chord forming circuit 142. The chord forming circuit 142 electronically synthesizes a chord signal having a percussive envelope every time chord pitch data is supplied from the memory 140, and this chord signal is supplied to the output amplifier 82 via a resistor 144. .
Therefore, when the chord pitch data corresponding to the first three sets of key code data KC is sent from the memory 140, the first chord is played from the speaker 84.

When one set of note length data LC is read out from the memory 20 after the first three sets of key code data KC,
The inverter 146 which receives the most significant bit of the code length data LC = "0" generates an output = "1" and sets the flip-flop 132. Therefore, AND gate 136 becomes non-conductive and data reading from memory 20 is temporarily stopped.

Further, the q-bit signal of the code length data LC is applied to the comparator 148 as one comparison input, and the counter 15 is applied as the other comparison input of the comparator 148.
A count output of 0 is added. The counter 150 is
After being reset by the first correctly pressed key detection signal KOT supplied via OR gates 130 and 152, the tempo clock signal TCL is counted.

When the count value of the counter 150 reaches a value corresponding to the first code length data LC, the comparator 14
8 generates the first match signal EQ. This match signal EQ causes flip-flop 132 to be reset via OR gate 130, so that AND gate 1
36 becomes conductive again and counter 42 counts the clock signal φ from AND gate 136. Therefore, the second chord data RD ₂ is read out from the memory 20 as before, and the key code data (chord pitch data) thereof is subjected to the chord signal forming process as before. As a result, the second chord is played from the speaker 84.

Further, the code length data of the second read data RD ₂ is subjected to code length measurement as in the previous time. That is, the first match signal EQ from comparator 148 is OR
Counter 150 via gates 130 and 152
After the reset, the counter 150 counts the tempo clock signal TCL.
Then, the count value of the counter 150 is determined by the comparator 148.
When the value corresponding to the second note length data as one comparison input is reached, the comparator 148 generates the second match signal EQ as before, and this match signal
Third chord data is read from the memory 20 in accordance with the EQ. Thereafter, in the same manner, new chord data is read from the memory 20 each time the matching signal EQ is generated from the comparator 148, and chord signal forming operations and note length measuring operations are performed based on the read data.

When the detection reference timing signal REFT is generated in response to the second keynote after the read operation based on the coincidence signal EQ as described above is repeated several times, this signal REFT is sent to the counter via the OR gate 152. 150 is reset. For this reason,
Comparator 148 detects the match signal that should have been generated.
No EQ is generated, and reading of chord data from memory 20 is also temporarily stopped. This readout halt state continues until the correct key press detection signal KOT corresponding to the second keynote is generated. That is, when this correctly pressed key detection signal KOT is generated,
Since flip-flop 132 is reset,
The counter 42 starts counting the clock readout φ,
Chord data RD ₂ corresponding to the second keynote is read out from memory 20, and chord performance and note length measurement based on this read data are performed in the same manner as described above. After this, the readout operation based on the coincidence signal EQ of the comparator 148 is repeated several times as described above, and when the timing to press the third keynote approaches, the second keynote is pressed. Similarly to the above case, the reading operation based on the signal REFT and the signal KOT is performed, and the chord performance is automatically performed by repeating such an operation.

In the auto base section 18B, base data is read from the base memory 22 in response to a read address signal consisting of the count output of the address counter 44.
RD ₃ is read. That is, after the counter 44 is reset and released by the read control signal,
A first address signal is supplied to the memory 22 in response to the first correctly pressed key detection signal KOT supplied via the OR gate 154. Therefore, the first base data RD ₃ is read from the memory 22. The format of the read data _RD3 at this time includes p-bit key code data KC and q-bit code length data LC as shown in the figure.

Key code data KC is base sound forming circuit 15
6. The bass sound forming circuit 156 electronically synthesizes a bass sound signal according to the key code data KC, and this bass sound signal is generated by the resistor 15.
8 to an output amplifier 82. Therefore, when the first base data RD ₃ is read from the memory 22, the first bass sound is produced from the speaker 84.

Further, the code length data LC is supplied to the comparator 160 as one comparison input, and the count output of the counter 162 is supplied as the other comparison input of the comparator 160. The counter 162 is reset in response to the first correctly pressed key detection signal KOT supplied via the OR gates 154 and 164, and then counts the tempo clock signal TCL.

When the count value of the counter 162 reaches the value corresponding to the first code length data LC, the comparator 16
0 generates the first match signal EQ. This match signal EQ is supplied to the counter 44 via the OR gate 154, so the counter 44 increments by one count in response to the signal EQ, and the second base data RD ₃ is read out from the memory 22. Similarly, each time the comparator 160 generates the matching signal EQ, a new base data _RD3 is read from the memory 22, and the base sound corresponding to the read data is output to the speaker 8.
It is played from 4.

When the detection reference timing signal REFT is generated in response to the second keynote after the readout operation based on the coincidence signal EQ as described above is repeated several times, this signal REFT is sent to the counter via the OR gate 164. 162 is reset. For this reason,
Comparator 160 generates a match signal that should have been generated.
No EQ is generated, and therefore the base data reading operation from the memory 22 is also temporarily stopped. This readout halt state continues until the correct key press detection signal KOT corresponding to the second keynote is generated. That is, when this correctly pressed key detection signal KOT is generated,
The counter 44 increments by one count, and the base data corresponding to the second keynote is retrieved from the memory 22.
RD ₃ is read out, and based on this read data, bass sound performance and note length measurement are performed in the same manner as described above. After this, the match signal of comparator 160
The readout operation based on the EQ is repeated several times as described above, and eventually when the timing to press the third keynote approaches, the signals REFT and KOT are activated as in the case of the second keynote described above.
A reading operation based on the above is performed, and by repeating such an operation, a bass performance is automatically performed.

The autorhythm section 18C reads rhythm pattern data from the rhythm pattern memory 24 in accordance with the beat data BD from the progression control circuit 26 described above.
RD ₄ is read out and supplied to the rhythm sound source circuit 166. The rhythm sound source circuit 166 sends out a rhythm sound signal by driving an appropriate rhythm sound source based on the rhythm pattern data RD ₄ from the memory 24, and this rhythm sound signal is supplied to the output amplifier 82 via a resistor 168. be done. For this reason,,
When the rhythm pattern data RD ₄ is read out from the memory 24, a rhythm sound is also played from the speaker 84.

As mentioned above, the beat counter 104 that generates the beat data BD starts counting based on the first correctly pressed key detection signal KOT, and then performs an AND gate every time the detection reference timing signal REFT is generated in response to a keynote. Since the supply of the tempo clock signal TCL via the keynote stops, the counting operation is temporarily stopped, and then when the correct key press detection signal KOT corresponding to the keynote is generated, the counting operation is resumed. Rhythm pattern data RD ₄ is read out from 24 in response to the beat data generation operation of the beat counter 104 . Therefore, the timing of generation and stop of the rhythm sound from the autorhythm section 18C is the same as the timing of generation and stop of the accompaniment sound from the autochord section 18A and the autobase section 18B.

Next, the score-related operations of the electronic musical instrument will be explained with reference to FIGS. 4 and 5. However, regarding the operation of the automatic accompaniment section 18, the operation of the auto chord section 18A will be described as a representative, and the operation of the auto bass section 18B and the auto rhythm section 18C will be described as the operation of the auto chord section 1.
Since the operation is similar to that of 8A, the explanation will be omitted.

Figure 4 shows the timing at which keys should be pressed in accordance with the note progression up to the first half of the third measure of the musical score in Figure 1.
It shows the progress of key press position display and the progress of chord accompaniment. Now, when the start signal ΔST is generated by turning on the start switch 32, melody data corresponding to the quarter note, which is the first note and the sharpest key note, is read out from the memory 16. The key code data KC ₁ of this read data is used to display the pressed key position as shown in FIG.
The display element of the key corresponding to the pitch of the diacribe lights up. Furthermore, the code length data _LC1 of the read data at this time is latched in the latch circuit 52 as shown in FIG.

Next, when the key whose display element is lit is pressed on the keyboard 74, the first correctly pressed key detection signal KOT is generated from the correctly pressed key detection circuit 68, and in response to this signal KOT, the second melody is output from the memory 16. First chord data is read out from the memory 20, respectively. Key code data KC ₂ of the second melody data read at this time is the fifth melody data.
As shown in the figure, the keyboard 74 is used to display the pressed key position.
Then, the display element of the key corresponding to the pitch of the eighth note, which is the second note, lights up. In addition, the latch circuit 5
As shown in FIG. 5, the first note length data LC ₁ latched at 2 is transferred to the latch circuit 54, and the note length data LC ₂ of the second melody data is latched in the latch circuit 52. Ru.

On the other hand, the counter 58 receives the first correctly pressed key detection signal.
Since the tempo clock signal TCL is counted after being reset by KOT, when the counted value reaches a value corresponding to the first note length data (data corresponding to a quarter note) _LC1 of the latch circuit 54, the comparator 56
The first match signal EQ is generated from. For this reason,
The third melody data is read out from the memory 16 and is used to display the key press position in the same manner as the previous time. A similar reading/display operation is performed for the first note of the third measure and the second keynote, 4.
It is performed up to the diacritic note. Further, in parallel with such operations, chord data is sequentially read out from the memory 20 in the autocode section 18B, and chord accompaniment is automatically performed based on the read data.

Here, while the key press position is being displayed for the quarter note, which is the first note of the third measure and the second keynote, if the timing to press the key for this quarter note comes just before, A detection start signal DS is generated from the correctly pressed key detection control circuit 70,
Detection reference timing signal according to this signal DS
REFT becomes “1”. Therefore, since the counters 58 and 150 are reset in response to the signal REFT, data reading from the memories 16 and 20 is temporarily stopped, and along with this, the key press position display and the chord accompaniment are also temporarily stopped. Ru.

After this, there is a slight delay d from the timing when the second keynote, the quarter note, should be pressed.
(For example, after a delay equivalent to an eighth note), when a key corresponding to the quarter note is pressed, the correctly pressed key detection circuit 68 generates a second correctly pressed key detection signal KOT. This signal KOT increments the counter 40 and resets the flip-flop 132, so that the melody data corresponding to the eighth note, which is the second note of the third measure, is sent from the memory 16, and the melody data of the third measure is sent from the memory 20. Chord data corresponding to the first chord is read out, and key press position display and chord accompaniment are restarted with each data readout. Note that if no key is pressed in response to the second keynote, or if a wrong key is pressed, the key press position display and chord accompaniment will not be resumed until the correct key is pressed.

FIG. 6 shows a circuit configuration of an electronic musical instrument according to a second embodiment of the present invention, in which the same parts as in the first embodiment are given the same reference numerals and details thereof will be explained in detail. The feature of this second embodiment is that an automatic interlude section 170 is provided so that an interlude is automatically inserted when a correctly pressed key is not detected after a certain period of time from the start of correctly pressed key detection. be.

Correct press key detection circuit 68 is correct press key detection control circuit 70
At the same time as starting the correct key press detection operation in response to the detection start signal DS from the automatic interlude section 170, the R-S flip-flop 172 is set by the detection start signal DS. The output Q="1" of the flip-flop 172 at this time is supplied to the AND gate 174 as one input. In addition, the detection start signal DS is sent to the timer counter 176.
It is designed to reset the counter 1.
76 counts the tempo clock signal TCL after being reset by the signal DS, and when the count reaches 10, supplies the carry-out output to the AND gate 174 as the other input. The output signal of AND gate 174 is supplied as a set input to R-S flip-flop 178, and the output Q of flip-flop 178 is used to determine the interlude insertion timing as described below. In addition, flip-flop 17
2 and 178 are reset by a correctly pressed key detection signal KOT generated from a correctly pressed key detection circuit 68.

Now, if it is assumed that the correct key press detection signal KOT is generated after the detection start signal DS is generated and before the counter 176 reaches 10 counts, the flip-flop 172 is reset by the signal KOT, so the flip-flop 178 is ANDed. Since it is not set by the output signal of gate 174, no interlude is included. On the other hand, assuming that the counter 176 reaches 10 counts after the detection start signal DS is generated, and then the correct key press detection signal KOT is generated, the flip-flop 175 is set when the counter 176 reaches the 10 count. After that, flip-flops 172 and 178
is reset by the correct key press detection signal KOT, so during the setting period of the flip-flop 178, an interlude is inserted as follows.

That is, when flip-flop 178 is set, its output Q="1" is output to inverter 180.
The address counter 182 is reset and released via the address counter 182. At the same time, the output Q="1" of the flip-flop 178 rises and is differentiated by the differentiating circuit 184.
A differentiated output signal from differentiating circuit 184 is supplied to counter 182 via OR gate 186. Therefore, the counter 182 increments by one count,
A first read address signal is supplied to an interlude memory 188 consisting of a RAM. Here, interlude memory 1
Reference numeral 88 indicates the interlude data RD ₆ previously read from an external recording means such as the recording medium 10a in FIG. 2 via a reading device.
is written. Therefore, memory 1
The first interlude data RD ₆ is read out from the counter 88 in response to the first read address signal from the counter 182 , and the key code data thereof is supplied to the interlude sound forming circuit 190 .

The interlude sound forming circuit 190 electronically synthesizes an interlude sound signal according to the key code data from the memory 188, and this interlude sound signal is supplied to the output amplifier 82 via a resistor 192. Therefore, when the first interlude data RD ₆ is read out from the memory 188, the first interlude sound is produced from the speaker 84.

First interlude data read from memory 188
Of the RD ₆ , the code length data is supplied to the comparator 194 as one comparison input, and the count output of the counter 196 is supplied as the other comparison input of the comparator 194. As mentioned above, when the output Q of the flip-flop 178 becomes "1", the counter 196 outputs the output of the inverter 198 which receives this output Q as an input.
The reset is canceled by "0", and then the tempo clock signal TCL is counted.

When the count value of the counter 196 reaches a value corresponding to the first symbol length data as one comparison input of the comparator 194, the comparator 194 outputs the first match signal EQ.
occurs. This coincidence signal EQ is the OR gate 186
is supplied to the counter 182 via the counter 1
82 is incremented by 1 count. Therefore, the second interlude data RD ₆ is read out from the memory 188, and is subjected to the interlude signal forming process and note length measurement as in the previous time. As a result, the second interlude sound is produced from the speaker 84. Thereafter, the third and subsequent interlude sounds are sequentially generated based on the same interlude data reading operation as described above. Such an interlude sound generation operation is stopped when the flip-flop 178 is reset by the correctly pressed key detection signal KOT.

As mentioned above, an interlude is inserted every time the flip-flop 178 is set, but the interlude is a rhythmic and relatively simple musical tone that is generated to help the performer proceed to the next key press. is preferred.

7 to 11 show the circuit configuration of an electronic musical instrument according to a third embodiment of the present invention.
The same parts as in the embodiment are given the same reference numerals, and detailed explanation thereof will be omitted. The feature of this third embodiment is that when a correctly pressed key is not detected during the correctly pressed key detection operation, the readout address is returned and the data is read out, thereby returning the pressed key position display and accompaniment by several notes. This means that it can be restarted.

In the start/stop control circuit 30 of FIG. 7, when the start switch 32 is turned on, the output Q="1" of the flip-flop 36 is sent out as the read control signal PLY. In addition, the differentiation circuit 34
generates a start signal ΔST in synchronization with the on-timing of the switch 32.

R-S flip-flop 200 is switch 32
This is to prevent the automatic accompaniment operation from starting until the first key depression operation is performed after the switch is turned on, and is set by the on signal of the switch 32. flipflop 200
When is set, its output Q="1" is supplied via inverter 202 to AND gate 204 as one input. Since the read control signal PLY is supplied to the other input of the AND gate 204, the output of the inverter 202 becomes "0" in response to the output Q of the flip-flop 200 being "1".
Then, the operation command signal OPT consisting of the output of the AND gate 204 becomes "0". Also, the output Q of the flip-flop 200 is output from the AND gate 206.
is supplied as one input to AND gate 20
The other input of 6 is the keyboard playing section 66 in FIG.
Any key-on signal AKO is supplied from. Therefore, the first key press signal KON1 is generated from the AND gate 206 based on the first key press operation.
This first key press signal KON1 is designed to reset the flip-flop 200 via the D-flip-flop 208 which is timed by the clock signal φ, so that when there is a first key press operation, the first key press signal KON1 is reset. As the flip-flop 200 is reset via the flip-flop 208, the operation command signal OPT becomes "1".

The R-S flip-flop 210 is provided to limit the return position at the beginning of the performance to one key note, and is set by the ON signal of the switch 32. When flip-flop 210 is set, its output Q="1" is applied through inverter 212 to AND gate 214, rendering it non-conductive. For this reason,
The ON/OFF signal of the return position selection switch 216 is applied to the other input of the AND gate 214.
AND gate 214 as long as 0 is set.
The return position designation signal RTN consisting of the output is "0" regardless of the operating state of the switch 216,
Specifies the return position for one keynote. and,
When the first correctly pressed key detection signal KOT is generated in response to the second keynote, the flip-flop 210 is reset by this signal KOT.
The output of the inverter 212 becomes "1" and the AND gate 214 becomes conductive. In this state, the return position designation signal RTN is "1" or "0" depending on whether the switch 216 is on or off.
and specify the return position of 2 keynotes or 1 keynote, respectively. Therefore, in the correct key press detection operation corresponding to each keynote after the third keynote, the return position for two keynotes or one keynote can be arbitrarily set depending on whether the switch 216 is turned on or off. Can be set. Furthermore, as mentioned above, the reason why the return position specification is limited to one keynote in the initial performance stage before the detection of the correctly pressed key corresponding to the second keynote is because it is impossible to go back two keynotes. It is something.

In the melody data generation circuit 14 of FIG. 8, when the read control signal PLY becomes "1" when the start switch 32 is turned on, the signal PLY
The counter 40 is reset and released by the output of the inverter 218 which inputs the signal = "0". At almost the same time, the counter 40 has an OR gate 220.
Since the start signal ΔST is supplied via
The counter 40 increments by one count, and the melody data corresponding to the first note (which is also the first keynote KT as shown in FIG. 12) is read out from the memory 16. The key code data KC of the read data at this time is supplied to the keyboard performance section 66 shown in FIG. 9, and the keyboard performance section 66 displays the pressed key position corresponding to the first note as shown in FIG. 12. . Furthermore, the code length data LC of the read data at this time is latched in the latch circuit 52.

Next, a first key press signal is generated based on the first key press operation.
When KON1 is generated, this signal KON1 is OR
Since the signal is supplied to the counter 40 via the gate 220, the melody data corresponding to the second note is read out from the memory 16. Therefore, as shown in FIG. 12, the keyboard playing section 66 displays the pressed key position corresponding to the second note, while the latch circuit 54 transfers and latches the first note length data from the latch circuit 52. , the second mark length data is latched in the latch circuit 52.

Furthermore, when the first key press signal KON1 is generated,
As described above, since the operation command signal OPT becomes "1", the output signal from the inverter 222 which receives this signal OPT as input cancels the reset of the counter 58 via the OR gate 224, and the counter 58 is reset.
is the tempo clock signal after this reset is released.
Count TCL. When the count value of the counter 58 reaches a value corresponding to the first code length data of the latch circuit 52, the comparator 56 sends out a match signal EQ via the AND gate 226 which is rendered conductive by the signal OPT. This coincidence signal EQ is supplied to the counter 40 via the OR gate 222, so the melody data corresponding to the third note is read out from the memory 16, and is used for displaying the pressed key position and measuring the note length as before. Ru. The same operation is repeated until the pressed key position corresponding to the second keynote KT is displayed as shown in FIG. 12. Note that in FIG. 12, the progression of key press position display is different from that in FIG. 4, and is shown using musical notes of a length corresponding to the actual display time.

As the key press position display progresses as described above, the 10th
In the progression control circuit 26 shown in the figure, the operation command signal OPT
Inverters 228 and 23 whose input is ="1"
The beat counter 104 and the bar counter 116, which are reset by the output signal of 0, each perform a counting operation, and these counters 104
The bar display circuit 118 displays the progressing bar in accordance with the bar number signal from 116 and 116.

Furthermore, in the automatic accompaniment section 18 in FIG.
Since it is supplied to the output amplifier 82 in the figure, the speaker 8
From 4 onwards, an autorhythm sound is played.

Further, in the automatic accompaniment section 18, an accompaniment tone forming circuit 234 electronically synthesizes an accompaniment tone signal CH based on accompaniment data RD ₀ automatically read out from an accompaniment memory 232 consisting of a RAM, and synthesizes an accompaniment tone signal CH via a resistor 236. Since the signal is supplied to the output amplifier 82 shown in FIG. 9, automatic accompaniment sound is also produced from the speaker 84. Here, accompaniment data RD ₀ is previously written into the accompaniment memory 232 from an external recording means such as the recording medium 10a of FIG. 2 via a reading device. In this case, the accompaniment data RD ₀ uses, as an example, chord data in which the chord type (major, minor, seventh, etc.), root note name, and note length are expressed in binary code. The accompaniment sound forming circuit 234 may form a bass sound signal using the base data.

When reading accompaniment data from memory 232, when start switch 32 is turned on, address counter 236 is reset by read control signal PLY supplied via inverter 238. Then, when the first key press signal KON1 is generated, this signal KON1 is output to the OR gate 24.
0 to the counter 236, so the counter 236 increments by 1 count and the memory 232
The first read address signal is supplied to the first read address signal. Therefore, the first accompaniment data RD ₀ is read from the memory 232, and data K of the chord type and root note name of this read data RD ₀ is sent to the accompaniment tone forming circuit 232.
As a result, the first accompaniment tone is generated as shown in FIG. Also, the code length data L of the read data RD ₀ at this time is stored in the comparator 242.
is supplied as one comparison input to comparator 242
The count output of the counter 244 is supplied as the other comparison input.

The counter 244 receives an operation command signal supplied via an inverter 246 and an OR gate 248.
After the reset is canceled by OPT, the tempo clock signal TCL is counted, and when the count value of the counter 244 reaches a value corresponding to the first note length data as one comparison input of the comparator 242, the comparison starts. 242 generates an initial match signal EQ. This coincidence signal EQ is the operation command signal OPT
Through the AND gate 250, which is conductive by
Furthermore, the counter 236 via the OR gate 240
Since the second chord data RD ₀ is read out from the memory 232, it is used for chord performance and note length measurement as in the previous time.

By the way, the first key press signal KON1 is sent to the OR gate 252 in the correct key press detection circuit 68 in FIG.
The signal is supplied to the two-stage D-flip-flop 254 via the D flip-flop 254, where it is delayed by two bit times of the clock signal φ and then sent out as the latch signal KTL. This latch signal KTL is supplied to primary latch circuits 256, 258, and 260 of FIG. 8, primary latch circuits 262 and 264 of FIG. 10, and primary latch circuit 266 of FIG. 11, respectively.
Therefore, when the latch circuit 52 latches the note length data corresponding to the second note (the note following the first keynote) and is delayed by one bit time of the clock signal φ, the latch circuit 256 latches the note length data corresponding to the second note (the note following the first keynote). The latch circuit 258 transfers the note length data corresponding to the first keynote from the circuit 54 to the latch circuit 5.
The note length data corresponding to the second note from 2 is
The latch circuit 260 transfers the address signal corresponding to the second note from the counter 40 to the latch circuit 260.
2 is the beat data BD corresponding to the first beat from the beat counter 104, and the latch circuit 264 is the measure data corresponding to the first measure from the measure counter 116.
Latch circuit 266 latches the address signals corresponding to the first chord from counter 236, respectively.

In addition, the first key press signal KON1 is delayed by 4 bit times of the clock signal φ in the correct key press detection circuit 68 of FIG. Latch signal PSM2 in the form
Sent as . This latch signal PSM2 is applied to the secondary latch circuits 274, 276 and 278 in FIG.
and secondary latch circuits 280 and 282 of FIG.
and a secondary latch circuit 284 in FIG. 11, respectively. Therefore, after the latch circuit 52 latches the note length data corresponding to the second note, the latch circuit 274 responds to the first keynote from the latch circuit 256 at a time delayed by two bit times of the clock signal φ. The note length data
The latch circuit 276 transfers the note length data corresponding to the second note from the latch circuit 258 to the latch circuit 276.
78 is the address signal corresponding to the second note from the latch circuit 260, the latch circuit 280 is the beat data corresponding to the first beat from the latch circuit 262, and the latch circuit 282 is the address signal corresponding to the first measure from the latch circuit 264. The corresponding measure data is sent to latch circuit 2.
84 latches address signals corresponding to the first chord from latch circuit 266, respectively.

It should be noted that the timing shown in FIG.
A latch signal PSM1 is generated from the OR gate 270, and is applied to the tertiary latch circuits 286, 288, and 290 in FIG. 8, the tertiary latch circuits 292 and 294 in FIG. 10, and the tertiary latch circuit 296 in FIG. However, at this time, these three
Next latch circuit 286, 288, 290, 292,
294 and 296 have corresponding secondary latch circuits 274, 276, 278, 280, 282 and 2
Since 84 is not latched, nothing is latched.

After this, when the timing to press the second keynote KT, which is the first note of the third measure, approaches, the first detection start signal DS is generated from the correct key press detection control circuit 70 in FIG. In response to this signal DS, the operation of the first correctly pressed key detection period _T1 is started as shown in FIG. That is, the first detection start signal DS is supplied as an input in to a 10-stage/1-bit shift register (S/R) 298, and is sequentially shifted in accordance with the tempo clock signal TCL. 1 to 9 of shift register 298
The output of the stage is ANDed through OR gate 300.
AND gates 302 and 304 are each supplied as one input to gates 302 and 304.
is conductive during the first positive key press detection period _T1 corresponding to the period in which the shift register 298 holds the input in at stages 1 to 9. Note that the comparison circuit 128
The value of n is preferably set to "4" or "5" corresponding to about half of the positive key press detection period _T1 .

If a key is pressed correctly during this initial key press detection period _T1 , the match signal EQ or any key-on signal AKO is supplied from the switch 90 to the AND gate 302.
2 generates the first correctly pressed key detection signal KOT. Since this signal KOT resets the flip-flop 210 of FIG. 7 as described above, the return position can then be selected using the switch 216.

Also, since the AND gate 304 is supplied with the coincidence signal EQ from the note length measuring section in FIG. 8 approximately in the middle of the detection period _T1 , the AND gate 304
4 sends out a keynote timing signal KNT. This keynote timing signal KNT is OR
Through gate 252, flip-flop 2
54 as a latch signal KTL.
Therefore, the latch circuit 256 receives note length data corresponding to the second keynote, the latch circuit 258 receives note length data corresponding to the note following the second keynote, and the latch circuit 260 receives note length data corresponding to the second keynote. The latch circuit 262 receives the address signal corresponding to the next note, the latch circuit 262 receives the beat data corresponding to the first beat, and the latch circuit 264 receives the measure data corresponding to the third measure.
The latch circuit 266 latches each address signal corresponding to the first chord of the third bar in the same manner as before.

On the other hand, since the first correctly pressed key detection signal KOT is configured to set the R-S flip-flop 308 for storing the correctly pressed key through the OR gate 306, an AND gate which receives the output Q of this flip-flop 308 is set. 310 becomes conductive when the first positive key press detection signal KOT is generated. When the detection period _T1 ends and the output of the 10th stage of the shift register 298 becomes "1", this "1" signal is supplied to the D-flip-flop 212, which is timed by the clock signal φ. The latch signal PSM1 is supplied to the OR gate 270 through the AND gate 310, and in response, the OR gate 270 outputs the latch signal PSM1.
Send out. Further, at a time delayed by one bit time of the clock signal φ from the time when the latch signal PSM1 is generated, the latch signal PSM2 is sent from the flip-flop 272, and at the same time, the flip-flop 308 is transferred to the flip-flop 312.
It is reset by the output of Note that the R-S flip-flop 314 for memory of no key press, which was set by the detection start signal DS, is connected to the OR gate 3.
06 and 316, the AND gate which has the output Q of the flip-flop 314 as one input is reset by the 10 of the shift register 298 as the other input. Even if the output of the stage becomes "1", the AND condition does not hold.

As described above, when the latch signal PSM1 is generated based on the output of the 10th stage of the shift register 298, the latch circuit 286 receives the note length corresponding to the first keynote from the latch circuit 274 in response to this signal PSM1. The data is latch circuit 288
is the note length data corresponding to the second note from the latch circuit 276, the latch circuit 290 is the address signal corresponding to the second note from the latch circuit 278, and the latch circuit 292 is the note length data corresponding to the second note from the latch circuit 278.
Beat data corresponding to the first beat from 0 is latched in the latch circuit 294, measure data corresponding to the first measure from the latch circuit 282 is latched in the latch circuit 296, and the latch circuit 296 is latched in the latch circuit.

Furthermore, when the latch signal PSM2 is generated as described above after the latch signal PSM1 is generated, the latch circuit 274 receives the note length data corresponding to the second keynote from the latch circuit 256 in response to this signal PSM2. , the latch circuit 276 receives note length data corresponding to the note following the second keynote from the latch circuit 258, and the latch circuit 278 receives note length data corresponding to the note following the second keynote from the latch circuit 260. The address signal is latch circuit 2
80 is the beat data corresponding to the first beat from the latch circuit 262, and the latch circuit 282 is the measure data corresponding to the third measure from the latch circuit 264.
The latch circuit 284 receives three signals from the latch circuit 266.
The address signals corresponding to the first chord of the bar are each latched.

By the way, contrary to the above, the initial key press detection period
If no key is pressed correctly during _T1 , the AND gate 318 is conductive due to the output Q of the flip-flop 314, which is set in response to the first detection start signal DS, so the shift register 29
8's 10th stage output = "1" is AND gate 3
18 as a return command signal PSLD. This return command signal PSLD is supplied as a preset signal PS to the counter 40 and latch circuits 52 and 54 in FIG. 8, the counters 104 and 116 in FIG. 10, and the counter 236 in FIG. 11, respectively. 54 has a selector 32
0, the latch circuit 52 from the selector 322, the counter 40 from the selector 324, the counter 104 from the selector 326, the counter 1
16 receives preset data from the selector 328, and counter 236 receives preset data from the selector 330.
PD is preset. At this time, selector 3
20, 322, 324, 326, 328 and 33
0, the return position designation signal PTN is always "0" as described above, so the inverters 332, 334, 336, 338, which receive this signal RTN as input.
The outputs of 340 and 342 = "1" are received as selection signals SA, respectively, and the input A is selectively sent out. Therefore, the latch circuit 54 receives the note length data corresponding to the first keynote from the latch circuit 274, and the latch circuit 52 receives the note length data corresponding to the first keynote from the latch circuit 274.
The note length data corresponding to the second note from 76 is stored in the counter 40 as the second note from the latch circuit 278.
The address signal corresponding to the th note is sent to the counter 104, the beat data corresponding to the first beat from the latch circuit 280 is sent to the counter 116, and the measure data corresponding to the first measure from the latch circuit 282 is sent to the counter 116.
The counter 236 is preset with an address signal corresponding to the first chord from the latch circuit 284, respectively. In FIG. 9, the return command signal PSLD passes through a D-flip-flop 344 timed by the clock signal φ, and further passes through the OR gate 31.
Since the flip-flop 314 is reset through the clock signal φ6, the signal PSLD becomes "1" in response to the output of the 10th stage of the shift register 298, and then becomes "0" in synchronization with the clock signal φ.
Return to

When the counter 40 and latch circuits 52 and 54 in FIG. 8, the counters 104 and 116 in FIG. 10, and the counter 236 in FIG. Operation of the illustrated circuit will essentially be resumed one keynote step back. In other words, the keyboard playing section 66
Then, based on the read data from the memory 16, the key press position display is restarted from the key corresponding to the note next to the first keynote, and the measure display circuit 118 resumes displaying the pressed key position.
Measure display is restarted from the first measure in accordance with the measure number signals from the counters 104 and 116, and the automatic accompaniment section 18 restarts accompaniment tone signal formation processing from the first chord based on the data read from the memory 232. Therefore, the performer can resume key pressing practice from the first keynote by referring to these displays or the accompaniment.

As the operation restarted in this way progresses and the timing to press the second keynote approaches again, the correctly pressed key detection operation is performed in the same way as described above, and as a result, the correctly pressed key is detected. If detected, the operation moves on to the second note of the third measure, but if no key press is detected, a problem arises as to whether to perform the return operation or the forward operation.
Therefore, in this embodiment, as shown in FIG. 9, the number of return operations can be set arbitrarily, and after the return operation has been performed the set number of times, the next operation is performed even if no key is pressed correctly. That is, the return number selection switch 346 selectively supplies the outputs of the 1st to 4th stages of the 4-stage/1-bit shift register 348 to the OR gate 350, and the shift register 348 selects the outputs of the 1st to 4th stages of the 4-stage/1-bit shift register 348. NOR gate 352 with eye output as input
The output signal of is taken in as input in, and this is sequentially shifted in accordance with the return command signal PSLD. Now, if the switch 346 is set to select the third stage output of the shift register 348 as shown in the figure, the output of the NOR gate 352 = "1" will be set to the shift register 348 in response to the first return command signal PSLD. is taken into the first stage. The signal captured at this time is shifted to the third stage in accordance with the second and third return command signals PSLD, and the output of the third stage = "1" if the key press is not detected twice thereafter. is switch 3
46 is supplied to OR gate 350 via. At this time, the output signal of the OR gate 350 = “1” is
When the fourth detection start signal DS for the second keynote is supplied from the D-flip-flop 354 timed by the clock signal φ to the AND gate 356, the OR
The signal is supplied to gate 306. In response, the OR gate 306 generates an output signal = "1", but since this output signal acts in the same way as the above-mentioned correctly pressed key detection signal KOT, the 3rd measure is detected as if the correct key was pressed. Shifts to the action after the second note. Note that the output signal of the AND gate 356 is applied to the D-flip-flop 3 which is timed by the clock signal φ.
58 and further via the OR gate 360, the shift register 348 is reset even when the return command signal PSLD is generated in response to the third keynote. Works the same as above.

The above is an example of repeating the return operation three times, but if the switch 346 is set to select the output of the 1st, 2nd, or 4th stage of the shift register 348, the return operation will be repeated once for each setting. , 2 or 4 return operations are repeated as described above. In addition, when the number of returns is set to two or more, if a correctly pressed key is detected during the first return operation before reaching the set number of returns, the correctly pressed key detection signal KOT is activated by the OR gate. Since the shift register 348 is reset via the key press 360, the remaining return operation is not performed, and the operation in the case of a key press described above proceeds.

Since there may be cases where the return operation as described above is not desired, a forced advance switch 362 is provided in this embodiment as shown in FIG. 9 in order to cope with such a case. That is, if the switch 362 is turned on before each positive key press detection period, the R-S flip-flop 364 is set in response to the on signal. At this time, the output Q of flip-flop 364 is OR
is fed through gate 350 to AND gate 356 so that the AND
When the detection start signal DS is supplied to the gate 356, the AND gate 356 outputs the output signal = “1”.
The output signal is supplied to the OR gate 306, and in response, the OR gate 306 generates an output signal="1". Since the output signal of the OR gate 306 at this time also acts in the same manner as the above-mentioned correctly pressed key detection signal KOT, the operation in the case of a correctly pressed key will proceed thereafter. Note that the output signal of the AND gate 356 at this time resets the flip-flop 364 via the flip-flop 358, so if you do not want the return operation to occur during the next correct key press detection period, you can turn on the switch 362 in advance. good.

The above-described operation for the second keynote with or without a key press is performed in the same way for each of the third and subsequent keynotes.

Here, for each keynote after the third keynote, if the return position selection switch 216 in FIG. 7 is turned on, the return operation for two keynotes will be performed. Explain in detail. As mentioned above, when a correctly pressed key is detected during the correctly pressed key detection period _T1 corresponding to the second keynote, the latch signal PSM1 is activated.
Accordingly, the latch circuit 286 receives the note length data corresponding to the first keynote, the latch circuit 288 receives the note length data corresponding to the second note, and the latch circuit 290 receives the address corresponding to the second note. The latch circuit 292 latches the beat data corresponding to the first beat, the latch circuit 294 latches the measure data corresponding to the first measure, and the latch circuit 296 latches the address signal corresponding to the first chord. ing. If no key press is detected during the key press detection period corresponding to the third keynote, the return command signal PSLD is generated as described above, and the counter 40, latch circuits 52 and 54, counters 104 and 116, The counter 236 is caused to perform a data preset operation. At this time, selector 3
20,322,324,326,328,330
The latch circuits 286, 288, 290, 292, 294, and 29 respectively receive the return position designation signal RTN=“1” from the return position selection switch 216 as the selection signal SB, and
Data or signals from 6 are selectively transmitted. Therefore, the latch circuit 54 receives note length data corresponding to the first keynote from the latch circuit 286, the latch circuit 52 receives note length data corresponding to the second note from the latch circuit 288, and the counter 40 receives note length data corresponding to the second note from the latch circuit 288. The address signal corresponding to the second note from the latch circuit 290 is sent to the counter 104, the beat data corresponding to the first beat from the latch circuit 292 is sent to the counter 116, and the beat data corresponding to the first bar from the latch circuit 294 is sent to the counter 116. The bar data is preset in the counter 236 with an address signal corresponding to the first chord from the address circuit 296, respectively.

Therefore, in the keyboard performance section 66, the key press position display is restarted from the key corresponding to the note next to the first keynote based on the read data from the memory 16, and in the measure display circuit 118, the key press position display is resumed from the key corresponding to the note next to the first keynote. The bar display is restarted from the first bar in response to the bar number signal, and the automatic accompaniment section 18 restarts the accompaniment tone signal forming process from the first chord based on the read data from the memory 232. Therefore,
The performer can refer to these displays or the accompaniment and resume key pressing practice from the first keynote, that is, from the note returned by two keynotes.

Note that when the automatic key press position display and automatic accompaniment are completed up to the last note, the memory 16 shown in FIG.
The end data is read from. The end detection circuit 62 generates the end signal FIN in response to the end bit FB="1" signal of the end data, and this signal FIN
causes flip-flop 36 of FIG. 7 to be reset. As a result, both the read control signal PLY and the operation command signal OPT return to "0", thereby completing the series of data read operations.

In the above explanation, an example was shown in which melody data read from a musical score is used to display key press positions, but the melody data is temporarily stored in the memory (RAM) of an automatic melody sound generation system (not shown). Melody sounds may be automatically generated based on the data read from this memory. In this case as well, the readout timing of the melody data from the memory can be controlled in accordance with the correct/incorrect detection output of the manual performance in the same manner as shown in the above example.

As described above, according to the present invention, the musical score data from the memory and the key press data from the keyboard are appropriately compared, and data reading is continued only when a key is correctly pressed, so that the key press position is displayed. , automatic melody performance, automatic accompaniment (auto chord, auto bass, auto rhythm), etc. can be effectively prevented from becoming independent, and performance practice efficiency can be greatly improved.

In addition, data comparison for determining the correct key press is not performed for every note, but is performed for each pre-selected note or at a certain periodic timing (timing of musically important notes), so it is possible to compare the data to determine the correct key press. It is possible to practice playing according to the rules, and it also has the advantage that it is easier for the performance practitioner to acquire a sense of measures and phrases. In other words, when performing music, it is important that the musical score and performance match each measure or phrase, but even if there is some variation in note length within a measure or phrase, it is hardly noticeable. Rather, the individuality of the performer may be expressed through this variation. Therefore, the electronic musical instrument according to the present invention is convenient for those who have practiced to a certain extent to be able to press each note accurately, and to practice according to the flow of a piece of music. It is something.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing part of the contents of the musical score used in the electronic musical instrument of the present invention, FIGS. 2 and 3 are circuit diagrams showing the electronic musical instrument according to the first embodiment of the present invention, and FIG. 5 is a time chart for explaining the circuit operation of the first embodiment, FIG. 6 is a circuit diagram showing an electronic musical instrument according to the second embodiment of the present invention, and FIGS. 7 to 11 12 is a circuit diagram showing an electronic musical instrument according to a third embodiment of the present invention.
The figure is a time chart for explaining the circuit operation of the third embodiment. 10... Musical score, 10a... Recording medium, 12...
Musical score data reading device, 16...melody memory,
18... Automatic accompaniment section, 20... Chord memory, 22
... Base memory, 24 ... Rhythm pattern memory, 28 ... Measure/beat memory, 66 ... Keyboard performance section, 68 ... Correctly pressed key detection circuit, 74 ... Keyboard, 7
8... Melody sound forming circuit, 142... Chord forming circuit, 156... Bass sound forming circuit, 166...
Rhythm sound source circuit, 170...Automatic interlude section, 188
...Interlude memory, 190...Interlude sound formation circuit, 2
16... Return position selection switch, 232... Accompaniment memory, 234... Accompaniment sound forming circuit, 346...
Return count selection switch, 362...forced advance switch.

Claims (1)

[Scope of Claims] 1 (a) a keyboard; (b) musical tone forming means for forming a musical tone signal based on key press data from the keyboard; (c) a storage device for storing musical score data, comprising: The musical score data includes pitch data and note length data for each note, and also includes keynote signals for each of the plurality of notes selected in advance; (e) means for generating a tempo clock signal; (f) each time musical score data including a keynote signal is read from the storage device, reading means for sequentially reading data; (e) means for generating a tempo clock signal; (g) detection control means for generating a detection start signal based on the note length data and the tempo clock signal; (g) detecting key press data from the keyboard and from the storage device according to the detection start signal from the detection control means; and detecting means for detecting the presence or absence of a correctly pressed key by comparing the pitch data in the musical score data, and controlling the reading of musical score data by the reading means in accordance with the detection output from the detecting means. An electronic musical instrument. 2. In the electronic musical instrument according to claim 1, the reading means reads the musical score data to be read next during the period from when the detection output indicates that a key is not pressed correctly until it indicates that a key is pressed correctly. An electronic musical instrument configured to stop. 3. In the electronic musical instrument according to claim 1, when the detection output indicates that no key is pressed correctly within a certain period of time, the readout means returns the readout address by at least one note and reads the data. An electronic musical instrument characterized by: 4. The electronic musical instrument according to claim 3, wherein the readout means is configured such that the number of notes to be returned to the readout address can be selected by a return position selection switch. 5. The electronic musical instrument according to claim 3, wherein the reading means is configured to be able to continue reading data without returning the read address by a forced progress switch. 6. The electronic musical instrument according to claim 3, wherein the reading means is configured so that the number of times the return reading operation is to be performed can be selected by a return number selection switch. 7 (a) a keyboard; (b) musical tone forming means for forming a musical tone signal based on key press data from the keyboard; (c) a storage device for storing musical score data; and (d) a (e) means for generating a tempo clock signal; (f) means for measuring a time corresponding to the length of each performance section of a certain length based on the tempo clock signal; (g) a detection control means for generating a detection start signal; What is claimed is: 1. An electronic musical instrument comprising: a detection means for detecting the presence or absence of a musical score, and controlling readout of musical score data by the readout means in accordance with a detection output from the detection means. 8. In the electronic musical instrument according to claim 7, the reading means reads the musical score data to be read next during a period from when the detection output indicates that a key is not pressed correctly until it indicates that a key is pressed correctly. An electronic musical instrument configured to stop. 9. In the electronic musical instrument according to claim 7, when the detection output indicates that no key is pressed correctly within a certain period, the readout means returns the readout address by at least one note and reads the data. An electronic musical instrument characterized by: 10. The electronic musical instrument according to claim 9, wherein the readout means is configured so that the number of notes to be returned to the readout address can be selected by a return position selection switch. 11. The electronic musical instrument according to claim 9, wherein the reading means is configured to be able to continue reading data without returning the read address by a forced advance switch. 12. The electronic musical instrument according to claim 9, wherein the reading means is configured so that the number of times to perform the return reading operation can be selected by a return number selection switch. 13 a keyboard, and first musical tone forming means for forming musical tone signals based on key press data from the keyboard;
a first storage device for storing musical score data; a first reading means for sequentially reading out the musical score data from the first storage device; key data and the first
a detection means for detecting the presence or absence of a correctly pressed key by comparing the musical score data from a storage device; a stop means for stopping reading of musical score data by the first reading means; a second storage device for storing interlude data; and a stop means for stopping reading of musical score data by the first reading means; It is characterized by comprising a second reading means for sequentially reading out the interlude data, and a second tone forming means for forming an interlude sound signal based on the interlude data read from the second storage device. electronic musical instruments. 14 a keyboard, and first musical tone forming means for forming musical tone signals based on key press data from the keyboard;
a first storage device for storing melody data; first reading means for sequentially reading out the melody data from the first storage device; detection control means for generating a detection start signal based on a tempo clock signal; a detecting means for detecting the presence or absence of a correctly pressed key by comparing key press data from the keyboard and melody data from the first storage device in response to the detection start signal; and accompaniment data for the melody data. a second storage device that stores the accompaniment data; and a second storage device that sequentially reads out the accompaniment data from the second storage device.
reading means, and a second tone forming means for forming an accompaniment tone signal based on the accompaniment data read from the second storage device, An electronic musical instrument characterized in that reading of melody data by the means and reading of accompaniment data by the second reading means are controlled.