JPS634225B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electronic dictionary.

In recent years, electronic dictionaries that electronically perform translation processing between, for example, English and Japanese have been developed. However, this type of electronic dictionary stores word information such as English and Japanese words, idioms, and sentences in its memory, and both English and Japanese words are A, B, C... or A,
The words are arranged in dictionary order such as A, U, etc., and the address information in which the translated word information is stored is stored in pairs with the word information. Arranging the word information in this way has the advantage that both English and Japanese can be searched in dictionary order, but since address information is stored for all word information, the storage capacity increases and a large amount of word information cannot be stored. Furthermore, when translating, it is necessary to read the translated word address held in the input word information and read out the translated word information according to that address, which slows down the translation speed.

This invention was made in view of the above circumstances,
To provide an electronic dictionary that requires less storage capacity than conventional ones, has a faster translation speed, and can search both a first language and a second language in dictionary order.

An embodiment in which the present invention is applied to an electronic dictionary that can translate into English and Japanese will be described below with reference to the drawings.
FIG. 1 is a plan view of the electronic dictionary. Various key groups are arranged on the top surface of the main body 1 of the electronic dictionary, 3 is a power on and all clear key, 4 is a power off key, 5 is a Japanese input mode instruction key, 6 is an English input mode instruction key, and 7 is a Input word or sentence (also referred to as word information in this example)
key to instruct translation of , 8 is single character correction key, 9
is a lowercase letter designation key, and 10 is a space key.
On the other hand, the remaining keys are English or Japanese input keys; after operating the above Japanese key 5, the kana written on each key is entered, and after operating the English key 6, the kana written on each key is entered. The alpha value that is displayed is entered. The display section 11 is comprised of, for example, a 20-digit 5.times.7 liquid crystal dot matrix display device.

Figure 2 stores English and Japanese word information.
This shows the configuration of the ROM (Read Only Memory) 15. As is clear from the drawing, in the row addresses 0 to 2499, English words and their translated Japanese words are stored as a pair of data, and each A pair of data is arranged and stored in alphabetical order. Furthermore, a space is written between the English word and the Japanese word in the pair of data, and an end mark is written after the Japanese word. On the other hand, the line address
After address 2500, the address data of Japanese words are stored as 6-digit data in the alphabetical order of the corresponding words. In this case, the column addresses of the ROM 15 range from 0 to 15, and of the 6-digit address data above, the upper 4 digits are the row address, and the lower 2
The digits indicate column addresses. For example, in the case of the first word "arch", this word is stored as a pair of data with the English word "ARCH" at row address 30, and the column address of the first character is
Therefore, the address data for the word "arch" is "003010" and is stored at the beginning of the row address 2500 as shown. Also, after this address data "003010", address data "097810" for the word "Ai" is stored, and thereafter, the address data of Japanese words are similarly stored in an array as 6-digit data in the same order as "Ai". has been done.

FIG. 3 shows a circuit for searching English or Japanese words stored in the ROM 15. In the figure, reference numeral 16 denotes an input register, into which a word to be translated is input using a key. The words in this input register 16 are displayed on the display section 11, and the words in the input register 16 are also displayed on the comparison circuit 11.
7 and is compared with data in a data register 18, which will be described later.

The data register 18 not only inputs and stores English or Japanese words read from the ROM 15 via the AND gate 19, but also temporarily stores address data of the Japanese words read from the ROM 15.

The data in this data register 18 is
In addition to being displayed at 1, it is also provided to the comparison circuit 17 via the AND gate 20. Thus, the Japanese address data in the data register 18 is applied to the latch 23 via an AND gate 21 and an OR gate 22 to designate an address for the ROM 15.

The comparison circuit 17 compares the data from the input register 16 and the data from the data register 18, and the comparison result signal is "1" at a binary logic level until both data match, and "0" when they match. is outputted and given to the AND gate 19 as a gate control signal, and also given to a control section (not shown). This comparison circuit 17 compares the English data from the data in the data register 18 until the space code is detected when translating into Japanese, and compares the Japanese data from the space code to the end mark when translating into English. It is. The control section is a circuit that controls all operations of the electronic dictionary, and in the case of Japanese translation, while the comparison result signal is "1",
While the increment operation for the address counter (not shown) attached to the ROM 15 is continued, the increment operation is stopped when a comparison result signal of "0" is input. On the other hand, in the case of English translation, while the comparison result signal is "1", the +6 circuit described later increments the address data by 6, and when it becomes "0", this increment operation is stopped. It's getting old.

The address register 24 is a register in which address data output from the control unit after key operation of the translation instruction key 7 is preset and stored at addresses 0 (for Japanese translation) and 2500 (for English translation). This address data is then given to the latch 23 via the AND gate 25 and the OR gate 22, as well as +
6 circuit 26 as well. This +6 circuit 2
6 is a circuit that sequentially adds 6 addresses to the preset data address 2500 in the case of English translation, and the new address data is given to the address register 24 via an AND gate 27.

Data read from the ROM 15 is input to the AND gate 19. The data output from this AND gate 19 is the register 1
8 and end mark determination circuit 28. The end mark determination circuit 28 is a circuit that determines the above-mentioned end mark, and its determination signal is used as each gate control signal for the AND gates 20 and 27, and is also applied to the set input terminal S of the SR type flip-flop 30 via the OR gate 29. The configuration is such that this flip-flop is set. This flip-flop 30 is also set by the key operation signal of the translation instruction key 7, and this key operation signal is applied to the set input terminal S via the OR gate 29. Further, the set output signal of the flip-flop 30 is applied to the AND gate 21 via the inverter 31, and directly to the AND gate 21.
5 to gate control, while delay circuit 3
2 is entered. This delay circuit 32 is a ROM
It has a delay time characteristic equal to the time required to read out 6-digit address data from the area below row address 2500 of 15, and its delayed output is applied as a reset signal to the reset input terminal R of flip-flop 30 via AND gate 33. In addition to being
It is given to latch 23 via OR gate 34 as a read command. In addition, the above translation instruction key 7
The key operation signal of the latch 2 is also transmitted through the OR gate 34.
3 as a read command. Furthermore, a mode signal MODE is inputted to both AND gates 27 and 33 as a gate control signal. This mode signal MODE is a signal that is output as "1" when the Japanese input mode key 5 is operated, and as "0" when the English input mode instruction key 6 is operated.

Next, the operation of the above embodiment will be explained. First, the operation during Japanese translation will be explained. For example, the English word "LOVE"
Assume that the translated word ``Ai'' is obtained by inputting ``Ai''.
After operating the key 3 to turn on the power, the English input mode instruction key 6 is operated. As a result, the mode signal MODE is thereafter output as "0", and the AND gates 27 and 33 are opened, so that the operations of the +6 circuit 26 and the delay circuit 32 are invalidated during this Japanese translation. Next, operate the alphabet keys,
When the English word "LOVE" is input, this data is input to the input register 16, displayed on the display section 11, and also provided to the comparison circuit 17. Next, when the translation instruction key 7 is operated, since the English input mode is currently set, the control unit outputs the row address 0 as address data and presets it in the address register 24. In addition, the flip-flop 30 is set by the key operation signal of the translation instruction key 7, so that its set output becomes "1", the AND gate 25 is opened, and the AND gate 21 is closed. Further, the key operation signal is given to the latch 23 as a read command, whereby the address data at address 0 from the address register 24 is latched into the latch 23 via the AND date 25 and the OR gate 22. And this latch 2
From the address data of address 0 latched to 3
ROM15 starts addressing, and from then on
An address counter attached to the ROM 15 sequentially addresses addresses 1 to 2499.

On the other hand, when address 0 of the ROM 15 is addressed, "A, Hitotsuno" is read out one character at a time as a pair of data for an English word and a Japanese word.
The signals are applied to the end mark matching circuit 28, respectively. As a result, the above-mentioned pair of data is input to the data register 18, and the end mark determination circuit 28 detects the end mark after "no", outputs a determination signal of "1", and opens the AND gate 20. Therefore, the English data in the data register 18 is applied to the comparison circuit 17 via the AND gate 20. The comparison circuit 17 compares the input English word "LOVE" with the English word "A" at address 0,
Since they do not match, a comparison result signal of “1” is output, and
Continue to open AND gate 19. The control unit also continues the increment operation of the address counter.

Next, "ABLE, DEKIL" is sequentially read character by character and applied to the data register 18 and the end mark determination circuit 28 via the AND gate 19.
However, in this case as well, the end mark after "ru" is detected and a comparison result signal of "1" continues to be output. Thereafter, a pair of data is sequentially read out from the ROM 15 by the operation of the address counter attached to the ROM 15 in the same manner, and the same operations as described above are repeated. Then, when address 978 is addressed and a pair of data "LOVE, I" is read out, the comparison circuit 17 detects a match between the data in the input register 16 and the data in the data register 18, and the comparison result is "0". Output the signal, and gate 1
9 is then closed. The control unit also outputs a command to stop the increment operation to the address counter. This stops the increment operation and
Further, "LOVE, I" is displayed on the display section 11, respectively.

Next, the operation in the case of English translation will be explained. For example, assume that the word "ai" is input and the translated word "LOVE" is obtained. First, the Japanese input mode instruction key 5 is operated, and from then on, the mode signal MODE is output as "1", and the AND gates 27 and 33 are output.
will be developed together. Next, operate the kana keys and enter the word "ai". As a result, the word "eye" is input to the input register 16, displayed on the display section 11, and also provided to the comparison circuit 17. Next, when the translation instruction key 7 is operated, the address data of address 2500 is outputted from the control section in accordance with the Japanese input mode, and is preset in the address register 24. Furthermore, the flip-flop 30 is set by the key operation signal of the translation instruction key 7, and a read command is given to the latch 23, so that the address data preset in the address register 24 is read.
Address 2500 is latched to latch 23, and ROM15
row address 2500 is addressed. For this reason, first, six-digit address data "003010" is read out character by character from the ROM 15 and input into the data register 18. Further, at the time when all of the above address data is input to the data register 18, the output of the delay circuit 32 becomes "1", the flip-flop is reset, and a read command is given to the latch 23. However, flip-flop 30
is reset, AND gate 21 is opened and AND gate 25 is closed. Therefore, the above address data "003010" in the data register 18 is applied to the AND gate 21 and the OR gate 22.
is applied to the latch 23 through the latch 23, and is latched. Therefore, the ROM 15 is addressed by the address data "003010", that is, the row address 30,
Column address number 10 is addressed, and the word "arch" is read out along with the word "ARCH" and input into the data register 18 and also provided to the end mark determination circuit 28. In other words, when translating into Japanese
I specified the first address in ROM15 where the English words are stored and read out the English word and the following Japanese word, but when translating into English, I specified the first address in ROM15 where the Japanese words are stored. Then, it reads out the Japanese word and the English word that precedes it. The end mark written at the end of the word "arch" is determined by the end mark determination circuit 28, and a determination signal of "1" is output, and at the same time, the data "arch" in the register 18 is determined by the comparison circuit. 17 and is compared with the data "I" in the input register 16, the flip-flop 30 is set and the AND gate 27 is opened. Therefore, the comparison circuit 17 detects a mismatch between the two data. While outputting a comparison result signal of "1", the output of the +6 circuit 26, that is, the address data "2506" obtained by adding six to the address data "2500" is input to the address register 24. This address data "2506" is passed through the opened AND gate 25 and OR gate 22 to the latch 2.
Then, the output of the delay circuit 32 becomes "1", and when a read command is given to the latch 23, it is latched. Then, the ROM 15 is addressed based on this address data "2506", and the next six-digit address data "097810" is successively output and input into the data register 18. This address data "097810" is the flip-flop 30
ANDGATE 2 was reset and opened again.
1 is applied to the latch 23 via the OR gate 22 and is latched. As a result, the ROM 15 is addressed by the address data "097810", the word "eye" is read out together with the word "LOVE", and is input to the data register 18 and also provided to the end mark determination circuit 28. When the end mark determination circuit 28 outputs a determination signal of "1", the data "eye" in the data register 18 is applied to the comparison circuit 17 via the AND gate 20.
However, in this case, the comparison circuit 17 detects a match between the data "eye" in the input register 16 and the data "eye" in the register 18, and outputs a comparison result signal of "0". As a result, the control unit will
Outputs a command to stop the increment operation by the circuit 26 (and gate 19 is also closed)
On the other hand, "I, LOVE" is displayed on the display section 11, respectively.

In the above embodiment, an electronic dictionary with English translation and Japanese translation functions was exemplified, but of course, an electronic dictionary in other languages may be used. In addition, the address data may be arranged in alphabetical order instead of the address data arranged in alphabetical order in the above embodiment, and furthermore, the arrangement may be based on Japanese rather than English. .

As explained above, according to the present invention, the word information of one language does not include address data, so the storage capacity can be reduced, and since the word information and translation information are stored as a pair, translation is possible. It has the effect of increasing speed. Furthermore, the first language and the second
Both languages can be searched in lexicographical order, which is very effective both internally and operationally.

[Brief explanation of the drawing]

Fig. 1 is a plan view of an electronic dictionary according to an embodiment of the present invention, Fig. 2 is a circuit configuration diagram of the main part, and Fig. 3 is a plan view of an electronic dictionary according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a storage state of a ROM. 5...Japanese input mode instruction key, 6...English input mode instruction key, 7...Translation instruction key, 15
...ROM, 16...Input register, 17...
Comparison circuit, 18...Data register, 23...Latch, 24...Address register, 26...+6
Circuit, 28... End mark judgment circuit, 30...
Flip-flop, 32...Delay circuit.

Claims (1)

[Claims] 1. A data group consisting of a pair of word information in the first language and its translation word information in the second language is
a first memory arranged and stored in dictionary order of the language; and a second memory arranged and stored in the dictionary order of the second language, address information of the first memory storing word information of the second language. an electronic dictionary, and means for reading word information of the first language and the second language by addressing the first memory and the second memory.