JPS6342136A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6342136A
JPS6342136A JP61186314A JP18631486A JPS6342136A JP S6342136 A JPS6342136 A JP S6342136A JP 61186314 A JP61186314 A JP 61186314A JP 18631486 A JP18631486 A JP 18631486A JP S6342136 A JPS6342136 A JP S6342136A
Authority
JP
Japan
Prior art keywords
pads
layer
chip
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61186314A
Other languages
English (en)
Inventor
Mikio Bessho
別所　幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61186314A priority Critical patent/JPS6342136A/ja
Publication of JPS6342136A publication Critical patent/JPS6342136A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8513—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にゲートアレイ品種の半
導体装置に関する。
〔従来の技術〕
従来、この種の半導体装置は、１ゲ一トアレイ品種が有
する最多のパッケージビン数のパッドをチップが有して
いた。そして、それ以下のパッケージビン数のものに対
しては任意のパッドを選んで外部端子に接続していた。
第２図及び第３図はそれぞれ従来の半導体装置の第１及
び第２の例の平面図である。
第２図及び第３図において、１は電極引出し用のパッド
、３′及び３″はチップ、４は外部端子、５は導線であ
る。
第２図に示す第１の例は、Ａパッケージへの正しい接続
、第３図に示す第２の例はＢパッケージへの正しい接続
である。
このように、使用するパッケージにより、同一配置のパ
ッドのうち使用するパッドが異なるので、第４図に示す
ように、第２図に示す接続を誤って接続することがあっ
た。
〔発明が解決しようとする問題点〕
上述した従来の半導体装置は、同一配置の同一形状をし
た複数のパッドから任意のパッドを選んで外部端子に接
続するので、配線誤りをするという欠点がある。
本発明の目的は、配線誤りの発生を防止できる半導体装
置を提供することにある。
〔問題点を解決するための手段〕
本発明の半導体装置は、半導体集積回路に搭載するチッ
プと、該チップに設けられる電極引出し用の複数のパッ
ドと、該パッドのうち外部端子に接続すべきパッドの近
傍に設けた認識マークとを含んで構成される。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図は本発明の一実施例の平面図である。
第１図において、１は電極引出し用のパッド。
２は認識マーク、３はチップ、４は外部端子、５はパッ
ドと外部端子を接続する導線である。
このように、還定されたパッド１の近傍に認識マーク２
を付加することにより、間違ったパッドに配線すること
を防止できる。
ゲートアレイの場合、パッド１が２層目のアルミニウム
層で形成されているため、認識マーク２も同様に２層目
のアルミニウム層に設けることにより、製造工程の拡散
プロセスを変更すること無く、簡単に適用できる。
〔発明の効果〕
以上説明したように本発明の半導体装置は、外部端子と
接続すべきパッドに認識マークを設けることにより、配
線誤りを防止できるという効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の平面図、第２図及び第３図
はそれぞれ従来の半導体装置の第１及び第２の例の平面
図、第４図は第２図の半導体装置の配線誤りの状態を示
す平面図である。 １・・・パッド、２・・・認識マーク、３．３’、３”
・・・チップ、４・・・外部端子、５・・・導線。 ＄　　、ｉ’　　Ｉ！］ χ　２　図 梯　４　図

Claims (1)

    【特許請求の範囲】
  1. 半導体集積回路に搭載するチップと、該チップに設けら
    れる電極引出し用の複数のパッドと、該パッドのうち外
    部端子に接続すべきパッドの近傍に設けた認識マークと
    を含むことを特徴とする半導体装置。
JP61186314A 1986-08-08 1986-08-08 半導体装置 Pending JPS6342136A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61186314A JPS6342136A (ja) 1986-08-08 1986-08-08 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61186314A JPS6342136A (ja) 1986-08-08 1986-08-08 半導体装置

Publications (1)

Publication Number Publication Date
JPS6342136A true JPS6342136A (ja) 1988-02-23

Family

ID=16186162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61186314A Pending JPS6342136A (ja) 1986-08-08 1986-08-08 半導体装置

Country Status (1)

Country Link
JP (1) JPS6342136A (ja)

Similar Documents

Publication Publication Date Title
US5780925A (en) Lead frame package for electronic devices
EP0538003B1 (en) Method of manufacturing inversion type ICs and IC module using same
JPH04307943A (ja) 半導体装置
US6791166B1 (en) Stackable lead frame package using exposed internal lead traces
US6121690A (en) Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge
JPS61117858A (ja) 半導体装置
KR930000614B1 (ko) 반도체 집적회로장치
JPS6342136A (ja) 半導体装置
JP2913858B2 (ja) 混成集積回路
JPH0661297A (ja) 半導体装置
JPH0621329A (ja) 樹脂封止型半導体装置
KR200169976Y1 (ko) 반도체 패키지
JPS595636A (ja) 半導体装置
JPS63308331A (ja) 半導体装置
JPH01145842A (ja) 半導体装置
KR100206975B1 (ko) 반도체 패키지
KR950004211Y1 (ko) 디램 모듈
JPS5828359Y2 (ja) 半導体集積回路装置
JPH04239736A (ja) 半導体装置の電極構造
JPS6081852A (ja) 半導体装置
JPH01205457A (ja) システム化半導体装置
JPH02189944A (ja) 半導体集積回路装置
JPS6047448A (ja) 半導体集積回路装置
JPH0669405A (ja) 半導体集積回路
JPH07106462A (ja) 半導体装置