JPS6341225B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for increasing the capacity of a mask ROM.

When increasing the capacity of ROM (Read Only Memory), which is a mask programmable ROM (abbreviated as mask ROM) in which information is written by changing the impurity introduction mask during the manufacturing process, the memory capacity (number of bits) can be doubled. However, using the current process diffusion mask pattern would double the chip size. For example, FIG. 1 shows an example of a mask layout pattern in the diffusion and contact process for 4 bits of a memory cell with a gate length l=5 μm, and the hatched areas are isolation regions formed by selective oxidation. FIG. 2 shows a MOSFET matrix circuit corresponding to FIG. In these memory cells, the L portion does not function as a gate because it is masked during diffusion. The dimensions of one cell are, for example, a=15 μm and b=17 μm.
In this case, if the chip size is 5 mm square, the maximum memory capacity will be 32K bits. If it is desired to increase the memory capacity to 64K bits using such a mask pattern, a minute mask with a gate length l = 3 μm must be used, which is difficult to achieve with current mask technology.

In view of the above points, the present invention was conceived to realize a 64K-bit mask ROM using a mask with a gate length of 5 μm by changing the layout pattern of the mask, and its purpose is to increase memory density or This is due to the reduction in chip size.

The gist of the present invention for achieving the above object is that in a MOSROM in which information is written by changing the impurity introduction mask, the contact positions to the diffusion layer are arranged alternately across the conductive layer constituting the gate. A mask MOSROM characterized in that one contact is also used as a contact for obtaining an output from two memory cells that share a conductive layer constituting the gate.
It is in. In addition to the above structure, the present invention also provides two types of threshold values by selectively introducing high concentration impurities into the semiconductor surface under the gate.

FIG. 3 shows an example of a mask layout pattern for 4 bits of a memory cell to which the present invention is applied. Such a ROM is manufactured using selective oxidation technology, polycrystalline silicon technology, or the like. In this case, the gate length l = 5 μm, the dimensions of one cell are a′ = 22 μm, b =
15 μm, with source contacts S ₁ , S ₂ ... and drain contacts D ₁ , D ₂ , with gates G ₁ , G ₂ in between.
The positions of D ₃ ... are arranged alternately (staggered), and one electrode serves as an electrode for two cells. When writing information here, the following three types of threshold values can be selected by changing the mask when introducing impurities.

(a) In case of write 0. For example, in a memory cell connecting the source _S1 and the drain _D1, a part of the thick selective oxide film 1 is connected to the diffusion layers 2 and 3 as shown in FIG.
By choosing a pattern that extends to the gate area between the MOSFETs, it is masked and does not function as a MOSFET.

(b) When the intermediate threshold low voltage Vth is set to 0.5V, for example, between the source S ₂ and the drain D ₁ or between the source S ₂ and the drain D ₂ , the gate part is A thin gate insulating film 4 is formed on the gate insulating film 4, and a mask pattern for the selective oxide film is selected so that the surface of the (P ^- type) Si substrate 5 underneath becomes a channel portion.

(c) When threshold V _th = 5V. For example, between the source S ₂ and the drain D ₄ , as shown in FIG. A mask pattern that forms .

FIG. 4 is a MOSFET matrix circuit diagram representing FIG. 3. L in the same figure is a cell in the case of writing 0 corresponding to a in FIG.
H is a cell when V _th is low corresponding to c, and H is a cell when V _th is high corresponding to c in the figure.
Information from MOSFETM ₁ is obtained by applying a predetermined signal to the word line G ₁ , grounding the data line L ₁ by an appropriate switch element (not shown), and connecting the data line L ₂ to the power supply via an appropriate load means. This allows the data to be read out via the data line _L2 . Note that at this time, the other data lines L ₃ and L ₄ are made floating or connected to the power supply.

According to the present invention described in the embodiments above, the following effects can be obtained.

(1) The number of decoders is the same as 32K bits, but 1
Two addresses can be extracted from the book's decoder output. For example, a cell is formed by using an M mask for 32K bits and an H mask for the remaining 32K bits.

(2) Chip size can be reduced if the memory capacity is the same. For example, if a 64K-bit chip is designed using the same cells as a 32K-bit chip, the chip size can be reduced by approximately 20% compared to the conventional pattern.

The invention is not limited to the above embodiments. The mask pattern of the diffusion layer can have various other patterns.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a conventional diffusion mask layout pattern of a memory cell, and FIG. 2 is a matrix memory circuit diagram corresponding to FIG. FIG. 3 is a plan view showing an example of a diffusion mask layout pattern of a memory cell according to the present invention, and FIG.
FIG. 3 is a matrix memory circuit diagram corresponding to the figure.
FIGS. 5a to 5c are cross-sectional views showing different cell configurations depending on code writing. 1... Selective oxide film, 2, 3... Diffusion layer (source/drain), 4... Gate oxide film, 5... Si
Substrate, 6... Ion-implanted P layer.

Claims (1)

[Claims] 1. In a MOSROM in which information is written by changing the mask for impurity introduction, the contact positions to the diffusion layer are arranged alternately across the conductive layer constituting the gate, and one contact A mask characterized in that the conductive layer constituting the gate is also used as a contact for obtaining output from two memory cells that share a common conductive layer.
MOSROM. 2. In a MOSROM in which information is written by changing a mask for introducing impurities, the contact positions of the diffusion layer on the semiconductor surface are arranged alternately across the conductive layer that constitutes the gate, and one contact is connected to the gate. It doubles as a contact to obtain output from two memory cells that share a common conductive layer, and it also serves as a contact to obtain output from two memory cells that share a common conductive layer.It also serves as a contact to obtain output from two memory cells that share a common conductive layer, and is made to have different types by selectively introducing impurities into the semiconductor surface under the gate at a higher concentration than the substrate. A mask MOSROM characterized by having a threshold value of .