JPS6339035A - Information processor - Google Patents

Abstract

PURPOSE:To improve the performance of a central processing unit CPU by disabling the reading of a register which stores the arithmetic result requested to an internal arithmetic processor and a flag which displays the state of the arithmetic result. CONSTITUTION:A CPU1 writes 1 to a general-purpose register 10 where the arithmetic result is written and a register 11 which displays a read unable state of an address line 100 when the instruction of an elementary function is executed. At the same time, 1 is set to a register 13 which displays a read unable state to a flag register 12 storing the state of the arithmetic result. An internal arithmetic processor 2 receives a control command and the operand data and starts the arithmetic processing. Then the CPU1 finishes the execution to the elementary function instruction with end of the arithmetic instruction and carries out a machine word instruction to update the register 10 and a machine word instruction to read out the register 10 as long as an exceptional interruption is inhibited. Then the arithmetic result is written to the register 10; while the state of the arithmetic result is written to the register 12 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a central processing unit that controls an internal arithmetic processing unit.

[Conventional technology]

Conventionally, this type of central processing unit waits for the internal arithmetic processing unit to complete an operation before executing the next machine language instruction.

[Problem that the invention seeks to solve]

The above-mentioned conventional central processing unit has the disadvantage that when the internal arithmetic processing unit is instructed to perform arithmetic processing on an elementary function, the performance of the central processing unit decreases because the instructing unit waits until the calculation is completed.

[Means for solving problems]

The information processing device of the present invention is a central processing unit capable of instructing one or more internal arithmetic processing units, and includes means for instructing the internal arithmetic processing unit to execute a first machine language instruction; means for storing an operation result using one machine language instruction; a first display means for displaying that reading is not possible for the storage means; and a first display means for displaying that reading is not possible for the flag storing the state of the operation result. 2, and in a state where updating by the execution result of the first #R machine language instruction is limited to the register and the flag, and exception interrupts for operation results are prohibited, the first machine language instruction is displayed. means for starting execution of a second machine language instruction scheduled to be executed next; and a third machine language instruction that updates the register or the flag in execution after the second machine language instruction; Or, after updating the flag, the first . means for canceling the read-unable display on the second display means; means for stopping execution of the fourth machine language instruction by a fourth machine language instruction for reading the register or the flag; and the internal arithmetic processing unit. means for interrupting the central processing unit upon completion of the computation; means for writing into the register when the first display means is displaying the display by the interrupt; and and means for writing into the flag register.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, one embodiment of the present invention includes a central processing unit 1 and an internal arithmetic processing unit 2.
An information processing device that enables a central processing unit 1 to instruct one or more internal arithmetic processing units 2, which instructs the internal arithmetic processing units by a first machine language instruction, and outputs the arithmetic results. a general-purpose register 10 that stores the register 10, a first register 11 that indicates that this register 10 is not readable, a flag register 12 that stores the state of the operation result, and a first register 11 that indicates that the flag 12 is not readable. 2 register 13, a fetch data register 14 that sets operand data from the main storage device (not shown), and a fetch data register 14 that sends operand data to the internal arithmetic processing device 2 and receives data of the arithmetic result from the internal arithmetic processing device 2. a communication data register 15 for setting, a communication control register 16 for sending control commands to the internal arithmetic processing unit 2, and an operation end interrupt pending register 2 for setting the end of an operation.
0, an AND gate 17.19 connected to registers 11 and 13, respectively, and this AND gate 17.19.
The OR gate 112, which is connected to the microprogram and inhibits execution of the microprogram, is used.

When the central processing unit 1 executes an instruction of an elementary function, it sets °“1” ( read-disabled state) is written via the control line 101. In addition, the control line 1 sets "1" (readout disabled state) to the register 13 that indicates that reading is disabled for the flag register 12 that stores the state of the operation result (result is zero, result is positive, result is negative).
Set via 02. Thereafter, operand data is set in the fetch data register 14 from the main memory (not shown) via the data line 103. The operand data of the fetch data register 14 is set in the communication data register 15 via the data line 104 in order to send the operand data to the internal arithmetic processing unit 2 . Control commands (SIN calculation, COS calculation, etc.) from the control line 105 are sent to the communication control register 1 under microprogram control.
Sera I on 6th. Thereafter, the internal arithmetic processing unit 2 receives control commands from the communication control register 16 through the control line 106, and Oberan l-data from the communication data register 15 through the data line 107 and bus line 108.
Then, arithmetic processing is started.

The central processing unit 1 terminates execution of the elementary function instruction when the internal arithmetic processing unit 2 completes the operation instruction. This central processing unit 1 determines by microprogram control whether or not exception interrupts are prohibited for the operation results of elementary function instructions, and if 5 exception interrupts are not prohibited, it waits for the operation results of the internal arithmetic processing unit. If exception interrupts are disabled, an opcode branch is performed to execute the next machine language instruction, and then the next machine language instruction is executed.

In the case of a machine language instruction that updates the general-purpose register 10, the general-purpose register 10 sets operand data via the data line 109, and also stops the control line 101 and sets 'Q' (readable state).Arithmetic result When updating the flag register 12 that stores the state of the flag, "Qoo (readable state)" is set via the control line 102.

In the case of a machine language instruction that reads the general-purpose register 10, the value of the output control line 109 of the register 11 indicating that reading is not possible is the same as the address line 100 of the general-purpose register 10, and the control line 110 indicates that the general-purpose register 10 is to be read. The value of the output control line 111 of the AND game I-17 is obtained by the value of . The value of the output control line 111 passes through the OR gate 18 and becomes the microinstruction execution inhibition control line 112, thereby inhibiting the execution of the microprogram. Similarly, when referencing the flag register 12 that stores the state of the operation result with a branch instruction, etc., the value of the output control edge 113 of the register 13 indicating that reading of the flag register 12 is disabled and the control line that refers to the flag register 12 This is the value of the output control line 115 of the AND gate 19 obtained by the value of 114. The value of the output control line 115 passes through the logic gate 18 and becomes the value of the microinstruction execution inhibit control line 112, thereby inhibiting the execution of the microprogram.

When the internal arithmetic processing unit 2 completes the instructed computation, the internal arithmetic processing unit 2 sends the data to the computation end interrupt pending register 20 through the computation end control line 116. At the same time, the calculation result is bus line 108
and is set in the communication data register 15 through the data line 117.

The microprogram is the operation end interrupt pending register 20.
When the value of the register 11 that indicates that the general-purpose register 10 cannot be read by reaping the interrupt that occurred in When the value of the register 13 indicating impossibility is "1", the state of the operation result is written.

〔Effect of the invention〕

As explained above, the present invention makes it impossible to read the registers that store the results of operations requested to the internal arithmetic processing unit and the flags that display the status of the results of operations, so that machine language instructions to be executed next can be read internally. It can be executed without using the calculation results of the processing unit, and has the effect of improving the performance of the central processing unit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. 1...Central processing unit, 2...Internal arithmetic processing unit, 1
0... General-purpose register, 11... General-purpose register read-disabled display register, 12... Flag register for storing calculation results, 13... Flag read-disabled display register, 14... Fetch data register, 15...
Communication data register, 16...Communication control register, 1
7.19...AND gate, 18...OR gate.ゝ(-/

Claims (1)

[Claims] In a central processing unit capable of instructing one or more internal arithmetic processing units, means for instructing the internal arithmetic processing units to execute a first machine language instruction; a first display means for displaying that reading is not possible for the storage means; a second display means for displaying that reading is not allowed for the flag storing the state of the operation result; A second machine language instruction scheduled to be executed next to the first machine language instruction is updated with the execution result of the first machine language instruction being limited to the register and the flag, and exception interrupts for operation results are prohibited. means for starting execution of the machine language instruction; and after updating the register or the flag by a third machine language instruction that updates the register or the flag in execution after the second machine language instruction, respectively. means for canceling the read-unable display on the first and second display means; means for stopping execution of the fourth machine language instruction by a fourth machine language instruction for reading the register or the flag; means for interrupting the central processing unit upon completion of an operation by the arithmetic processing unit; means for writing in the register when the first display means is displaying the information due to the interrupt; and means for writing into the flag register when the flag register is present.