JPS6338900B2 - - Google Patents
Info
- Publication number
- JPS6338900B2 JPS6338900B2 JP56209993A JP20999381A JPS6338900B2 JP S6338900 B2 JPS6338900 B2 JP S6338900B2 JP 56209993 A JP56209993 A JP 56209993A JP 20999381 A JP20999381 A JP 20999381A JP S6338900 B2 JPS6338900 B2 JP S6338900B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- output
- bits
- code
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 108010076504 Protein Sorting Signals Proteins 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 9
- 238000003780 insertion Methods 0.000 description 7
- 230000037431 insertion Effects 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
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- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
【発明の詳細な説明】
（技術分野）
本発明は、高速２値デイジタル伝送方式に用い
る符号変換回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a code conversion circuit used in a high-speed binary digital transmission system.
（背景技術）
従来、高速２値デイジタル伝送方式においては
第１図Ａに示すように、スクランブラのみからな
る符号変換装置が用いられることが多い。この装
置を用いた場合、デイジタル信号系列のマーク率
を1/2に収束させ、ランダム化することにより定
常的な伝送特性の確保、ジツタ抑圧等が確率的に
行われる。しかし信号パターンによつては、長い
同符号連続が生じる可能性があり、符号間干渉の
増加、タイミング抽出不能等、伝送品質の劣化を
生み出す欠点を持つている。(Background Art) Conventionally, in high-speed binary digital transmission systems, a code conversion device consisting only of a scrambler is often used, as shown in FIG. 1A. When this device is used, by converging the mark rate of the digital signal sequence to 1/2 and randomizing it, steady transmission characteristics are ensured, jitter suppression, etc. are stochastically performed. However, depending on the signal pattern, long sequences of the same code may occur, which has drawbacks such as increased intersymbol interference and inability to extract timing, resulting in deterioration in transmission quality.
また第１図Ｂに示すように、スクランブラと共
に２値ｍビツトをｎ（一般にｎ＝ｍ＋１）ビツト
に符号変換する装置を用いることもある。この場
合、最悪同符号連続数を決定できるが、一般に伝
送路上昇率（伝送速度の上昇率）が大きすぎ、さ
らに符号変換回路の構成が非常に複雑なものにな
り、高速デイジタル伝送方式には不適である。第
１図Ｃにｍ＝３とした場合の符号変換回路のブロ
ツク図を示す。この回路では、ゲート数120個、
フリツプフロツプ20個程度が必要となる。 Further, as shown in FIG. 1B, a device for converting the code of binary m bits into n (generally n=m+1) bits may be used together with a scrambler. In this case, the worst-case number of consecutive identical codes can be determined, but the rate of increase in the transmission path (rate of increase in transmission speed) is generally too large, and the configuration of the code conversion circuit becomes extremely complex, making it difficult to use in high-speed digital transmission systems. Not suitable. FIG. 1C shows a block diagram of the code conversion circuit when m=3. This circuit has 120 gates,
Approximately 20 flip-flops are required.
（発明の課題）
本発明は従来の技術の上記欠点を改善して、符
号間干渉の低減及び確実なタイミング抽出を図る
ことによりデイジタル伝送方式の信頼性を高める
ことを目的とし、２値信号系列のｍビツト目（ｍ
は自然数）にそのパルスの直前あるいは数ビツト
前の補符号を挿入して同符号連続を抑圧するもの
で、その特徴は、入力データをうけ入れる入力端
子と、入力端子の２値信号系列をｋビツト（ｋは
自然数）シフトし、その出力Ｑ及びその補出力
を与える手段と、パルス間隔T0のクロツクパル
スを１／ｍ（ｍは２以上の整数）に分周してパル
ス幅T0のパルスCMをmT0毎に与える分周回路と、
分周回路の出力と前記Ｑ及びとの論理積（S1＝
ＱCM，R1＝QCM）を与える手段と、該論理積手
段の出力（S1，R1）をｋ＋１ビツトだけシフト
するシフト手段と、補符号挿入の為のフリツプフ
ロツプとを有し、該フリツプフロツプは前記Ｑに
従つてオン／オフするとともに前記S1がシフトさ
れたパルスS2によりセツトされ前記R1がシフト
されたパルスR2によりリセツトされ、該フリツ
プフロツプの出力に接続される出力端子とを有
し、入力２値信号系列のｍビツト毎にそのｋビツ
ト前のパルスの補符号を挿入して同符号連続を抑
圧するごとき符号変換回路にある。(Problems to be solved by the invention) The present invention aims to improve the reliability of a digital transmission system by improving the above-mentioned drawbacks of the conventional technology and by reducing intersymbol interference and reliable timing extraction. m-th bit (m
is a natural number) and inserts a complementary code immediately before or several bits before the pulse to suppress the same code consecutively.The feature is that it has an input terminal that accepts input data and a binary signal series of the input terminal that is Means for bit shifting (k is a natural number) and providing the output Q and its supplementary output; and means for dividing the clock pulse with a pulse interval T 0 into 1/m (m is an integer of 2 or more) to generate a pulse with a pulse width T 0 . A frequency divider circuit that gives C M every mT 0 ,
The logical product of the output of the frequency dividing circuit and the Q and (S 1 =
QC M , R 1 =QC M The flip-flop is turned on and off according to the Q, and is set by the pulse S2 shifted from the S1 and reset by the pulse R2 shifted from the R1 , and has an output terminal connected to the output of the flip-flop. The code converting circuit has a code conversion circuit which inserts a complementary code of the pulse k bits before every m bits of an input binary signal sequence to suppress the same code consecutively.
（発明の構成及び作用）
第２図は本発明の回路であり、１は２値信号入
力端子、２はクロツク入力端子、３は符号変換さ
れた信号の出力端子である。また４は１ビツトシ
フトレジスタ、５は１／ｍ分周回路、６はリセツ
トパルス発生部、７はセツトパルス発生部、８は
位相調整用ゲート回路、９，１０は２ビツトシフ
トレジスタ、１１は補符号挿入部を示している。
この回路の動作を第３図に示すタイムチヤートに
従い説明する。なお、使用したフリツプフロツプ
は、Ｄ−TYPE MASTER−SLAVEとする。(Structure and operation of the invention) FIG. 2 shows a circuit according to the invention, in which 1 is a binary signal input terminal, 2 is a clock input terminal, and 3 is an output terminal for a code-converted signal. Further, 4 is a 1-bit shift register, 5 is a 1/m frequency dividing circuit, 6 is a reset pulse generation section, 7 is a set pulse generation section, 8 is a phase adjustment gate circuit, 9 and 10 are 2-bit shift registers, and 11 is a compensation circuit. The code insertion part is shown.
The operation of this circuit will be explained according to the time chart shown in FIG. The flip-flop used is D-TYPE MASTER-SLAVE.
今、第３図ａに示す２値信号が入力されたとす
る。この信号系列は４により、Q1，1端子にク
ロツク同期して出力されるｃ，ｄ。一方、クロツ
クは５によりｅに示すようなmT0（T0：パルス間
隔）毎に、パルス幅をT0とするクロツクパルス
CMへ変換されるｅ。このCMパルスとQ1及び1と
の論理積をとることにより、６，７においてリセ
ツト及びセツトパルスが作られる。すなわち、ｍ
−１ビツト目の信号が“１”であればリセツトパ
ルスを、又逆に“０”であればセツトパルスが作
られるｆ，ｇ。この制御パルスをｍビツト目に挿
入するため、制御パルスを９，１０により２ビツ
ト分の位相シフトを行うｈ。次に１１において、
上記演算分の遅延時間を８で補償した２値信号系
列に対し、ｍビツト毎にセツトあるいはリセツト
制御して３より出力するｉ。 Assume now that the binary signal shown in FIG. 3a is input. This signal series is outputted from terminals Q 1 and 1 in clock synchronization by signals c and d. On the other hand, the clock is a clock pulse whose pulse width is T 0 every mT 0 (T 0 : pulse interval) as shown in e by 5.
e converted to C M. By ANDing this C M pulse with Q 1 and 1 , reset and set pulses are created at 6 and 7. That is, m
If the -1st bit signal is "1", a reset pulse is generated, and conversely, if it is "0", a set pulse is generated. In order to insert this control pulse into the m-th bit, the control pulse is phase-shifted by 2 bits using 9 and 10. Next, in 11,
For the binary signal series whose delay time for the above calculation is compensated by 8, set or reset control is performed every m bits and output from 3.
このような動作をするため、最悪同符号連続長
をｍビツトに抑圧することができる。 Because of this operation, the worst case continuous length of the same code can be suppressed to m bits.
直前ビツトの補符号をとる回路を実施例として
示したが、４に示すシフトレジスタをｋ（ｋ＝２，
３，……，ｍ）段に、又９，１０に示すシフトレ
ジスタをｋ＋１段に縦続接続する場合、ｋ−１ビ
ツト前までの任意のパルス位置の補符号をｍビツ
ト目に挿入することができる。 Although a circuit that takes the complementary sign of the immediately preceding bit has been shown as an example, the shift register shown in 4 is constructed by k (k=2,
When the shift registers shown in 9 and 10 are connected in cascade to the k+1 stage, it is possible to insert the complementary code of any pulse position up to k-1 bits before the m-th bit. can.
また、１／ｍ分周回路の構成例を第４図Ａに示
す。この回路は従来の回路技術で、任意のｍに対
して構成できる。第４図Ｂは第４図Ａの動作を示
す図である。 Further, an example of the configuration of a 1/m frequency dividing circuit is shown in FIG. 4A. This circuit can be constructed for any m using conventional circuit technology. FIG. 4B is a diagram showing the operation of FIG. 4A.
第５図に、本発明回路を用いた伝送方式の構成
を示す。１２は速度変換部、１３はフレーム構成
部、１４はスクランブラ、１５は補符号挿入部、
１６は伝送路、１７はフレーム同期検出部、１８
はデスクランブラ、１９は速度変換部である。 FIG. 5 shows the configuration of a transmission system using the circuit of the present invention. 12 is a speed conversion unit, 13 is a frame configuration unit, 14 is a scrambler, 15 is a complementary code insertion unit,
16 is a transmission path, 17 is a frame synchronization detector, 18
1 is a descrambler, and 19 is a speed converter.
入力された２値信号系列は、まず１２において
速度変換され、補符号、フレーム同期パルス、対
局監視制御情報等を挿入するサービスパルスが確
保される。この信号系列は、１３によりフレーム
構成された後、１４においてスクランブラにより
ランダム化される。その際、サービスパルスには
スクランブルはかからないようにする。次に、本
発明回路１５により補符号を周期的に挿入し、伝
送路１６へ送出する。受信側では、まずフレーム
同期が１７でとられた後、１８はデスクランブル
を行う。最後に１９で速度変換して、全てのサー
ビスパルスを除去し、２値信号系列のみを出力す
る。補符号挿入パルスに対してスクランブルをか
けないため、受信側におけるデスクランブルは、
同期のみとれていれば補符号挿入パルスには無関
係に実行でき、１９における速度変換により補符
号挿入パルスは除去される。 The input binary signal sequence is first speed-converted in step 12, and service pulses for inserting complementary codes, frame synchronization pulses, game monitoring control information, etc. are secured. This signal sequence is constructed into a frame at step 13 and then randomized at step 14 by a scrambler. At this time, the service pulse should not be scrambled. Next, the circuit 15 of the present invention periodically inserts a complementary code and sends it to the transmission line 16. On the receiving side, frame synchronization is first established at 17, and then descrambling is performed at 18. Finally, speed conversion is performed at step 19 to remove all service pulses and output only a binary signal sequence. Since the complementary code insertion pulse is not scrambled, descrambling on the receiving side is
If only synchronization is achieved, it can be executed regardless of the complementary code insertion pulse, and the complementary code insertion pulse is removed by the speed conversion in step 19.
本符号変換回路より構成される伝送路符号の電
力スペクトラムは第６図のようになり、この符号
を用いた効果を第７図に示す。最悪同符号連続を
抑圧することにより、符号間干渉量増加の抑圧、
タイミング特性の改善等が図れる。第７図は
400MHzで動作する光中継器の符号間干渉量耐力
特性測定結果である。スクランブラのみの伝送符
号では、24ビツト連続は頻繁に起り得る。この伝
送路符号が10ビツトまでに制限されると、許容符
号間干渉量は約４％まで増加する。光中継器の設
計において、ジツタ及び識別レベル変動等、同符
号連続耐力特性に影響を与える劣化要因に対し、
許容干渉量は2.5％とされている。ゆえに同符号
連続を制限することにより、安定な中継器動作が
得られることを解る。 The power spectrum of the transmission line code constructed by this code conversion circuit is as shown in FIG. 6, and the effect of using this code is shown in FIG. Suppressing the increase in the amount of inter-symbol interference by suppressing the worst-case same-symbol sequence,
Timing characteristics can be improved. Figure 7 is
These are the results of measuring the intersymbol interference tolerance characteristics of an optical repeater operating at 400MHz. In scrambler-only transmission codes, 24-bit sequences can occur frequently. If this transmission line code is limited to 10 bits, the amount of allowable intersymbol interference increases to about 4%. In the design of optical repeaters, we take into account deterioration factors that affect the same code continuous tolerance characteristics, such as jitter and discrimination level fluctuations.
The allowable amount of interference is 2.5%. Therefore, it can be seen that stable repeater operation can be obtained by restricting the same code sequence.
（発明の効果）
以上説明したように本発明によれば、一定の複
数毎に挿入するビツトをその前に現われる特定ビ
ツトの補符号とするので、最悪同符号連続を抑圧
することができる。このため、符号間干渉量増加
の抑圧、タイミング特性の改善等が図れ、中継器
の動作が安定化し、通信品質の良好な高速デイジ
タル伝送方式を実現できる。(Effects of the Invention) As described above, according to the present invention, since the bits inserted every certain number of bits are the complementary codes of the specific bits that appear before them, it is possible to suppress the worst case of consecutive identical codes. Therefore, it is possible to suppress an increase in the amount of intersymbol interference, improve timing characteristics, etc., stabilize the operation of the repeater, and realize a high-speed digital transmission system with good communication quality.
第１図Ａと第１図Ｂは従来のデイジタル伝送方
式の構成図、第１図Ｃは第１図Ｂにおける符号変
換回路のブロツク図、第２図は本発明による符号
変換回路のブロツク図、第３図は第２図の回路の
動作タイムチヤート、第４図Ａは11分周回路の
例、第４図Ｂは第４図Ａの回路の動作を示す図、
第５図は本発明を用いるデイジタル伝送方式の構
成図、第６図は本発明を用いた場合の電力スペク
トラムを示す図、第７図は光中継器の符号間干渉
耐力特性を示す図である。
１……２値信号入力端子、２……クロツク入力
端子、３……２値信号出力端子、４……１ビツト
シフトレジスタ、５……１／ｍ分周回路、６……
リセツトパルス発生部、７……セツトパルス発生
部、８……位相調整用ゲート、９，１０……２ビ
ツトシフトレジスタ、１１……補符号挿入部、１
２……速度変換部、１３……フレーム構成部、１
４……スクランブラ、１５……補符号挿入部、１
６……伝送路、１７……フレーム同期検出部、１
８……デスクランブラ、１９……速度変換部。
1A and 1B are block diagrams of the conventional digital transmission system, FIG. 1C is a block diagram of the code conversion circuit in FIG. 1B, and FIG. 2 is a block diagram of the code conversion circuit according to the present invention. 3 is an operation time chart of the circuit in FIG. 2, FIG. 4A is an example of an 11 frequency divider circuit, FIG. 4B is a diagram showing the operation of the circuit in FIG. 4A,
FIG. 5 is a block diagram of a digital transmission system using the present invention, FIG. 6 is a diagram showing a power spectrum when the present invention is used, and FIG. 7 is a diagram showing intersymbol interference tolerance characteristics of an optical repeater. . 1...Binary signal input terminal, 2...Clock input terminal, 3...Binary signal output terminal, 4...1-bit shift register, 5...1/m frequency dividing circuit, 6...
Reset pulse generation section, 7... Set pulse generation section, 8... Phase adjustment gate, 9, 10... 2-bit shift register, 11... Complementary code insertion section, 1
2... Speed conversion section, 13... Frame configuration section, 1
4...Scrambler, 15...Complementary code insertion section, 1
6...Transmission line, 17...Frame synchronization detection unit, 1
8... Descrambler, 19... Speed converter.
Claims (1)
子の２値信号系列をｋビツト（ｋは自然数）シフ
トし、その出力Ｑ及びその補出力を与える手段
と、パルス間隔T0のクロツクパルスを１／ｍ（ｍ
は２以上の整数）に分周してパルス幅T0のパル
ス（CM）をmT0毎に与える分周回路と、分周回
路の出力と前記Ｑ及びとの論理積（S1＝CM，
R1＝QCM）を与える手段と、該論理積手段の出
力（S1，R1）をｋ＋１ビツトだけシフトするシ
フト手段と、補符号挿入の為のフリツプフロツプ
とを有し、該フリツプフロツプは前記Ｑに従つて
オン／オフするとともに前記S1がシフトされたパ
ルスS2によりセツトされ前記R1がシフトされた
パルスR2によりリセツトされ、該フリツプフロ
ツプの出力に接続される出力端子がもうけられ、
入力２値信号系列のｍビツト毎にそのｋビツト前
のパルスの補符号を挿入して同符号連続を抑圧す
ることを特徴とする符号変換回路。1. An input terminal for receiving input data, means for shifting the binary signal sequence of the input terminal by k bits (k is a natural number) and providing the output Q and its complementary output, and a clock pulse with a pulse interval T 0 of 1/m. (m
is an integer of 2 or more) and gives a pulse (C M ) of pulse width T 0 every mT 0 , and the logical product of the output of the frequency dividing circuit and the above Q and (S 1 = C M ,
R 1 =QC M ); shift means for shifting the output (S 1 , R 1 ) of the AND means by k+1 bits; and a flip-flop for inserting a complementary code. an output terminal is provided which is turned on and off according to Q and is set by a pulse S2 shifted from said S1 and reset by a pulse R2 shifted from said R1 , and connected to the output of said flip-flop;
1. A code conversion circuit characterized in that a complementary code of a pulse k bits before is inserted for every m bits of an input binary signal sequence to suppress consecutive same codes.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56209993A JPS58114542A (en) | 1981-12-28 | 1981-12-28 | Code converting circuit |
| CA000401079A CA1186763A (en) | 1981-04-20 | 1982-04-15 | Consecutive identical digit suppression system in a digital communication system |
| GB8211095A GB2098432B (en) | 1981-04-20 | 1982-04-16 | Consecutive identical digit suppression system |
| DE3214150A DE3214150C2 (en) | 1981-04-20 | 1982-04-17 | Circuit arrangement for limiting the number of identical successive bits in a sequence of bits in a digital transmission device |
| NLAANVRAGE8201608,A NL185969C (en) | 1981-04-20 | 1982-04-19 | BIT INSERT SYSTEM FOR AVOIDING TOO MANY OF CONSEQUENTLY IDENTICAL BITS. |
| FR8206678A FR2504327A1 (en) | 1981-04-20 | 1982-04-19 | SYSTEM FOR REMOVING IDENTICAL NUMBERS CONSECUTIVE OF A DIGITAL TRANSMISSION SYSTEM |
| US06/369,838 US4502143A (en) | 1981-04-20 | 1982-04-19 | Consecutive identical digit suppression system in a digital communication system |
| IT8267523A IT1212659B (en) | 1981-04-20 | 1982-04-20 | Data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56209993A JPS58114542A (en) | 1981-12-28 | 1981-12-28 | Code converting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114542A JPS58114542A (en) | 1983-07-07 |
| JPS6338900B2 true JPS6338900B2 (en) | 1988-08-02 |
Family
ID=16582076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56209993A Granted JPS58114542A (en) | 1981-04-20 | 1981-12-28 | Code converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114542A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6859465B1 (en) * | 1999-11-22 | 2005-02-22 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for constant throughput rate adaptation |
-
1981
- 1981-12-28 JP JP56209993A patent/JPS58114542A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58114542A (en) | 1983-07-07 |
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