JPS6338328U - - Google Patents
Info
- Publication number
- JPS6338328U JPS6338328U JP1986131950U JP13195086U JPS6338328U JP S6338328 U JPS6338328 U JP S6338328U JP 1986131950 U JP1986131950 U JP 1986131950U JP 13195086 U JP13195086 U JP 13195086U JP S6338328 U JPS6338328 U JP S6338328U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- connection wiring
- wiring
- contact hole
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000000605 extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986131950U JPH0436114Y2 (US20030204162A1-20031030-M00001.png) | 1986-08-28 | 1986-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986131950U JPH0436114Y2 (US20030204162A1-20031030-M00001.png) | 1986-08-28 | 1986-08-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6338328U true JPS6338328U (US20030204162A1-20031030-M00001.png) | 1988-03-11 |
| JPH0436114Y2 JPH0436114Y2 (US20030204162A1-20031030-M00001.png) | 1992-08-26 |
Family
ID=31030878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986131950U Expired JPH0436114Y2 (US20030204162A1-20031030-M00001.png) | 1986-08-28 | 1986-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0436114Y2 (US20030204162A1-20031030-M00001.png) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276748A (ja) * | 1988-04-28 | 1989-11-07 | Fuji Electric Co Ltd | 半導体素子の突起電極 |
| JP2014068015A (ja) * | 2012-09-25 | 2014-04-17 | Samsung Electronics Co Ltd | バンプ構造体、電気的接続構造体、及びその形成方法 |
| JP2015228472A (ja) * | 2014-06-03 | 2015-12-17 | 株式会社ソシオネクスト | 半導体装置およびその製造方法 |
-
1986
- 1986-08-28 JP JP1986131950U patent/JPH0436114Y2/ja not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276748A (ja) * | 1988-04-28 | 1989-11-07 | Fuji Electric Co Ltd | 半導体素子の突起電極 |
| JP2014068015A (ja) * | 2012-09-25 | 2014-04-17 | Samsung Electronics Co Ltd | バンプ構造体、電気的接続構造体、及びその形成方法 |
| JP2015228472A (ja) * | 2014-06-03 | 2015-12-17 | 株式会社ソシオネクスト | 半導体装置およびその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0436114Y2 (US20030204162A1-20031030-M00001.png) | 1992-08-26 |
