JPS6338182A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit device which enables a scan test with a small number of control input pins by providing scan registers, gate circuits, latch circuits, etc., between circuit blocks to be tested and at their connection parts. CONSTITUTION:The scan registers 8a-16a, latch circuits 75 and 76, AND gates 70 and 72, OR gates 71, 73, and 74, etc., are incorporated between a combinational block 35 and asynchronous circuit blocks 36 and 37 including order circuits and a their connection parts. Consequently, an input to the circuit block to be tested is fixed at a prescribed value by the gate circuits interposed at the outputs of the scan registers 8a-16a in a scan mode and also held as test data in the last period by the latch circuits 75 and 76. Consequently, the input signal to the circuit block to be tested is prevented from varying during scanning. Further, a positive type clock signal and a negative signal having the same timing with it are controlled in test operation with one control signal, and the test data never varies at the time of mode switching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more specifically to a test circuit for a semiconductor integrated circuit device using a scan canvas.

[Conventional technology]

With advances in microfabrication technology, the degree of integration of semiconductor integrated circuits has improved dramatically and is likely to continue to increase in the future. As the degree of integration (number of gates) increases, the difficulty of testing semiconductor integrated circuit devices increases exponentially. Here, the testability of a device is determined from two points: (observability (easiness in observing failures at each terminal) and controllability (ease in setting each terminal to a desired logical value)). Deep terminals in a large-scale logic network deteriorate both observability and controllability.

There is a scan test method as a test method for semiconductor integrated circuit devices. In this scan test method, register circuits having a shift register function are inserted into appropriate locations in a logic circuit network, and these register circuits are combined into a single shift register. They are connected via a bus, and during test operation, a test pattern is serially input from outside the chip, predetermined data is set in each register, and desired logic signals are applied to the logic circuits connected to the data output terminals of these registers. By operating these registers, inputting the results in parallel into the registers from the parallel input terminals of these registers, and then outputting them serially to the outside of the chip for observation, it is possible to observe the deep terminals of large-scale logic circuit networks. , which aims to improve controllability.

The basic idea of a scan test method for level-sensitive synchronous circuits is disclosed in Japanese Patent Laid-Open No. 52-28614.

Here, since the target circuits include asynchronous sequential circuits, the description will be made with reference to Japanese Patent Application Laid-Open No. 56-74668 as a conventional example.

Figure 3 shows an example of a conventional scanpath method test circuit for asynchronous sequential circuits, 35 is a combinational circuit block, 36°37 is an asynchronous circuit block including a sequential circuit, and 8 to 16 are asynchronous circuit blocks including sequential circuits. Scan registers 26 to 34 provided between each circuit block are data selectors that select and output either the output of the corresponding circuit block or the output of the scan register. The output signal of each circuit block is directly connected to the data input terminal of the scan register and the data input terminal of the data selector, and the test data input terminal TD of the data selector
is connected to the output terminal Q of the corresponding scan register.

Further, 1 is a test mode selection terminal, and this terminal 1 is each mode selection terminal M of the scan register and data selector.
Connected to S. 2 is a scan-in terminal, and 3rd is a scan-out terminal.

The scan-in terminal 2 is connected to the scan-in terminal Sl of the scan register 8, and the output terminal Q of the scan register 8 is connected to the scan-in terminal Sl of the scan register 9. In this way, the output terminal Q of each scan register is connected to the scan-in terminal Sl of the scan register 8. It is sequentially connected to the scan-in terminal SI of the next scan register, and as a result, a shift register path is formed between the scan-in terminal 2 and the scan-out terminal 38. 3 to 5 are normal data input terminals, and 6 is a scan clock input terminal, which is connected to the clock input terminal T of the scan register.

FIG. 4 shows an example of the scan register, in which MS is a mode selection terminal, D is a data input terminal, S is a scan-in terminal, and T is a clock input terminal. Also, 51 is an inverter gate, 52.53 is a two-man AND gate, and 54
55 is an edge trigger type D-type flip-flop (hereinafter referred to as D-FF), and Q is a data output terminal.

FIG. 5 is an example of the data selector shown in FIG. 3 above, where MS is a mode selection terminal, TD is a test data input terminal, D is a data input terminal, 60 is an inverter gate, 6
1.62 is a two-man powered AND gate, 63 is a two-man powered OR gate, and Y is an output terminal.

Next, the operation will be explained.

First, the normal operation will be explained. In this case, "H" is applied to the test mode selection terminal 1 (MS), and the scan clock terminal 6 (TS or T) is fixed to "L". As a result, the input/output terminals between the corresponding circuit blocks are directly connected through each data selector.

To explain this with reference to FIG. 5, when "H" is applied to the mode selection terminal MS, the data selector outputs data from the data input terminal to the output terminal Y via the AND gate 62 and the OR gate 63. Since the output of the circuit block is directly connected to the data input terminal of this data selector, the input/output terminals between the corresponding circuit blocks are directly connected.

On the other hand, during the test operation, the scan mode and test mode are sequentially repeated as described below to test each circuit block.

■ Scan mode (a) Apply "H" to test mode selection terminal 1 to set scan mode. As a result, the scan register selects the input data from the scan-in terminal SI,
In the data selector, input data from the data input terminal becomes valid.

(b) Furthermore, the test data set in each scan register is sequentially scanned in from the scan-in terminal 2 in synchronization with the clock applied to the scan clock terminal 6.

(C) At the same time, the output data of each circuit block taken in during the previous test is sequentially scanned out from the scan-out terminal 38.

To explain this operation with reference to FIGS. 4 and 5, first, in the scan register, the mode selection terminal MS is
When H is applied, data from the scan-in terminal Sr is sent to the AND gate 53. D-FF5 is synchronized with the clock applied to the clock terminal T via the OR gate 54.
5, and the data held at the same time is output from the output terminal Q. At this time, "H" is also applied to the mode selection terminal MS of the data selector, and therefore, the data from the data input terminal is output to its output terminal Y.

■ Test mode (al) After setting desired data in each scan register, apply "L" to test mode selection terminal 1 to enter test mode.

(b) As a result, the output data of the scan register is applied to each circuit block via the test data input terminal TD of the data selector.

(e) At the same time, apply desired test data to data input terminals 3 to 5.

fdl Next, when the operation of the circuit block is completed, one clock is applied to the scan clock input terminal 6.

As a result, the output signal of each circuit block is held in the D-FF in the scan register through the data input terminal of the corresponding scan register.

These operations will be explained with reference to FIGS. 4 and 5.
First, in the scan register, when "L" is applied to the mode selection terminal MS, the data from the data input terminal is
D gate 52. It is held in the D-FF 55 in synchronization with the clock applied to the clock input terminal T via the OR gate 54.

At this time, "L" is also applied to the mode selection terminal MS of the data selector, so the data from the test data input terminal TD is sent to the output terminal Y of the AND gate)61. O
It is output via the R gate 63.

In this way, each circuit block 35 to 37 can be tested, but in this circuit, the data selector selects the output data of each circuit block during the scan operation, so the scan register Even if the output values of the sequential circuits change sequentially, the state of the circuit block 36 including the sequential circuit does not change. Therefore, as in this example, scan testing is possible even if the circuit block surrounded by the scan canvas is an asynchronous sequential circuit.

[Problem that the invention attempts to solve]

Since the conventional device is configured as described above, a scan test can also be performed on blocks including asynchronous sequential circuits. However, in general, when switching from test mode to scan mode, the data given to the sequential circuit changes from the serially input signal value to the output signal value of the adjacent circuit block. There is a problem in that it is difficult to set inputs so that the state of the sequential circuit does not change, and in many cases it is not possible to effectively perform a scan test.

The present invention has been made to solve the above-mentioned problems, and provides a semiconductor integrated circuit device that includes a circuit block including an asynchronous sequential circuit and that can be easily scan tested with a small number of control signal input bins. With the goal.

[Means for solving problems]

A semiconductor integrated circuit device according to any of the inventions provides a scan method between the circuit blocks under test, in which the input and output terminals are put into a through state during normal operation and input data is output as is, and the input data is held and output during test operation. It is connected to a register and an output terminal of this scan register, and outputs the output data of the scan register in the test mode during normal operation and test operation, and the first fixed data and the first fixed data in the scan mode during test operation. The first fixed data outputs the second fixed data having the opposite logical value to the first fixed data, or the output data of the scan register of the previous cycle. a second gate circuit, a launch circuit, and a negation circuit connected to a control input of the first or second gate circuit; The input of the circuit is connected to the same control signal.

[Effect]

In the present invention, the input of the circuit block under test in the scan mode can be fixed to a predetermined value by the gate circuit inserted into the output of the scan register, and can be held at the test data of the previous cycle by the latch circuit. Therefore, it is possible to prevent the input signal of the circuit block under test from changing during scanning. Also, during testing, a positive type clock signal and a negative signal with the same timing can be controlled with one control signal, and the test data does not change when switching from test mode to scan mode, reducing the number of pins. This allows easy scan testing of circuit blocks containing asynchronous sequential circuits.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and 35 to 37 are the circuits under test.
A test circuit according to an embodiment of the present invention is incorporated into these connections. 8a to 16a are scan registers, the details of which will be described later.

75 and 76 are scan registers 10a, respectively.

This is a launch that is connected to the output terminal of 11a and has a through function.When the E input is "H", the launches 75 and 76 propagate the input data as is to the Q output, and when it becomes "L"・The notched contents are held and output to the output Q. 70.72 is an AND gate provided between the scan register and the circuit block, 71, 73.74 is an OR gate similarly provided between the scan register and the circuit block, and 77.78.79 is the control input of the OR gate. Connected inverter. Also, 81.82 is a -77 child control input terminal, 80.90.91 is a gate control input terminal, and 3
6a to 36c and 37a to 37c are inputs of the circuit blocks to be tested. Here, circuit block 3 in this embodiment
In 6.37, the human power 36a and 37b are active H inputs, the inputs 36b and 37c are active L inputs, and the human power 36c and 37a have input data H-L.
.

The input is such that the internal state changes regardless of whether it changes in the L or H direction. Further, 7 is a normal mode input terminal for switching between normal operation and test operation.

Further, the scan register in this embodiment is different from the conventional one and is configured as shown in FIG.

That is, in FIG. 6, 56 is an inverter, 57°, 58 is an AND gate, and 59 is an OR gate, and the other configurations are the same as those shown in FIG. The scan register configured in this way propagates the input data as is to the output Q when the normal mode signal NM is "H", and conversely, when the normal mode signal NM is "L", it is the same as the conventional register shown in FIG. It is a function.

Next, the operation will be explained.

First, normal operation will be explained. During normal operation, the normal mode input cuff is “■(1, latch control input 81.8
2 “H”, gate control input 80°90.91 “H”
Apply. As a result, all scan registers are D
The signal propagates as it is from the input to the Q output, and
The inputs of the latches 75 and 76 and the gates 70 to 74 propagate as they are to the outputs. Therefore, data between circuit blocks can be propagated as is without being affected by the test circuit, and desired normal operation can be performed.

Next, a test operation, that is, a case where the normal mode entry cuff is set to "L" will be described. In this case, the scan mode and test mode are switched by the signal at the test mode selection terminal 1.

By repeating these two modes, the circuit under test is tested.

Next, these two modes will be explained.

■ Scan mode Setting the test mode selection terminal 1 to "H" sets the scan mode. In this mode, by applying a clock to the scan crofter input terminal 6, test data can be scanned in and scanned out to the scan registers forming the scan path. An example of this operation is shown in FIG. In the figure, the scan mode is when input 1 is set to "I(". In this embodiment, scan data is output to the output terminal Q of the scan register during scan operation, so a signal corresponding to this data is output. Change happens.

However, in scan mode the latch control input 81.
If 82 is set to 1L'', the input 36 to the circuit under test
c, 37a can hold data before the scan operation. Furthermore, if all the gate control inputs 80 and 90 are set to "L", the inputs 36a and 37b are fixed to "L" and the inputs 36b and 37c are fixed to "H".

In this way, since the input of the circuit block under test can be fixed during the scan mode, the state of the circuit block can be maintained.

■ Test mode In test mode, set test mode selection terminal 1 to “L”. In this mode, the contents of the scan register are input to the circuit block under test, and then the output of the circuit block under test is taken into the scan register.

An example of this operation is shown in FIG. In the figure, the test mode is when input 1 is set to "L".

In this test mode, as shown in FIG. 2, pulses are output to the inputs 36a, 36b, and 37b.
Assuming that it is not output to the input 37c, the output data of the scan registers 8a, 9a, 12a, and 13a are "H", "L", and "H", respectively.

It is also assumed that the scan registers 10a and 11a are outputting "H" and "L", respectively. These test data are applied to the latch circuits 75 and 76 and the gate 7.
By setting 0 to 73 in a through state, they can be applied to the circuit block under test. In FIG. 2, the outputs of launches 75 and 76 are launch control signals 81e and 8, respectively.
They are output in synchronization with the rising edge of 2e, and each signal 3
5ce and 37ae, and these data are held in cheers 3 and 76, respectively. Also game-170-73
The output of each is 90p pulse.

Since they are output only during periods of 90p, 80p, and 80p, the waveforms are 36al), 36bp, and 37bp, respectively.

It will be like 37ce.

After applying the test data to the circuit block to be tested in this manner, the test result output from the circuit block is input into the scan register by passing a pulse 6p to the scan clock input terminal 6.

This test result data is sequentially scanned out during the next scan operation.

In this embodiment, since a latch or an AND or OR gate is connected to the output of the scan register, the operation of the circuit under test can be stopped in the scan mode by controlling its control input, and moreover, the operation of the circuit under test can be stopped at any timing. A test pulse of "■(" or "L" of Test data can be generated without having to think about this, and scan tests can be easily performed.

Also, normally when an AND circuit and an OR circuit are provided, different control signals are connected to their control inputs, but in this embodiment, an inverter is connected to the control input terminal of the OR circuit. A positive type signal and a negative type signal with the same timing can be controlled with one control input, and the number of pins on the integrated circuit can be reduced.

In the above embodiment, an inverter is provided at the control input terminal of the OR gate. However, an inverter may be provided at the control input terminal of the AND gate 70, 72, and the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the case where the control inputs of the AND circuit and the OR circuit of the same stage are connected is explained, but if the timing of the inputs of the circuit blocks 36 and 37 is the same, then the control inputs of each gate circuit 70 to 73 can be controlled. It is also possible to connect all of the inputs to the same control signal.

〔Effect of the invention〕

As described above, according to the present invention, the circuit under test professional,
The output data of the above-mentioned scan register is inputted to the output of the scan register during normal operation in the test mode during normal u operation and eggplant 1- operation, and the first υ1 constant data is input in the scan mode during test operation. A first and second gate circuit and a latch circuit are provided for holding and outputting second fixed data having an opposite logical value to the first fixed data, or output data of the scan L disk before the scan operation, and test data. Since the output of the circuit block can be controlled by the control input, the operation of the circuit under test can be stopped during scan operation, and the test data for each circuit block can be given only from the scan data, so the output of other circuit blocks can be controlled. Test data can be generated without considering data values, and scan tests can be easily performed. Moreover, test pulses with arbitrary timing can be applied to the circuit under test. Furthermore, the above 1. The same control signal is connected to the control input terminal of the second gate circuit, so that a positive type signal and a negative type signal with the same timing can be controlled with one control input. This has the effect of reducing the number of pins in the product circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining a test operation in the device, and FIG. 3 is a circuit diagram of a conventional semiconductor integrated circuit device. 4 is a diagram showing a specific example of the scan register circuit in the device shown in FIG. 3, FIG. 5 is a diagram showing a specific example of the selection circuit in the device shown in FIG. 3, and FIG.
FIG. 1 is a diagram showing an example of the configuration of a scan register circuit in the device shown in FIG. DESCRIPTION OF SYMBOLS 1...Test mode selection terminal, 2...Scan in terminal, 6...Scan clock input terminal, 7...Normal mode input terminal, 8a to 16a...Scan register, 35...Combination circuit block, 36.
37...Asynchronous circuit block including sequential circuit, 3 days...
・・Scan out terminal, 70.72 ・・2-person power AN
D circuit, 71°73.74-2 manual OR circuit, 75.1
6-launch circuit, 77.78.79...inverter,
80,90°91...Gate control input, 81.82.
...Latch control input. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor integrated circuit device, at least one of which transmits data between a plurality of circuit blocks including a sequential circuit, and is capable of testing each of the circuit blocks using a scan test method, are provided between each circuit block corresponding to the number of bits of data to be propagated, and during normal operation, the output data of the previous stage circuit block is output as is, and during test operation, the output data of the previous stage circuit block or scan test is provided. It holds and outputs test data in synchronization with an external clock, and each circuit is connected by a shift register path so that the entire circuit has one shift register function. The output terminal of a predetermined scan register is connected to a predetermined input terminal of a predetermined circuit block, and output data of the corresponding scan register is provided during normal operation and test mode during test operation. It is output as it is to the next stage circuit block, and in the scan mode during test operation, the first
fixed data, a second fixed data having an opposite logical value to the first fixed data;
first and second gate circuits that output fixed data to the next circuit block; an inverter connected to the control input terminal of the first or second gate circuit; At the output terminal of the register,
An output terminal is connected to a predetermined input terminal of a predetermined circuit block, and during normal operation and test mode during test operation, the output data of the corresponding scan register is output as is to the next stage circuit block, and the test is performed. A latch circuit that holds and outputs the output data of the corresponding scan register before the scan operation in the scan mode during operation, and a test data setting means for setting serial data for testing from outside the device to each of the scan registers. , comprising test result output means for sequentially outputting the data of each of the above scan registers to the outside of the device as serial data, and operation switching means for switching between normal operation and test operation, and between scan mode and test mode, The control input terminal of the first or second gate circuit and the input terminal of the inverter provided at least in the same stage among the plurality of first and second gate circuits are connected to the same control signal input. A semiconductor integrated circuit device characterized by: