JPS6337950B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital dimming device using transmission control, which transmits a digital signal to a transmission line and enables dimming of a lighting load by remote control.

FIGS. 1 to 4 show an example of a conventional digital light control device using transmission control. As shown in Figure 1, a plurality of receivers 2 with different addresses are connected to the transmission line 1, and the transmitter 3 sends 4-bit address data AD as shown in Figure 2.
and 4-bit control data CD are transmitted together with a synchronizing signal SD to control the dimming of the lighting load 4 connected to the receiver 2 called up by the address data AD. Figure 3 shows the conventional receiver 2
First, the reception 4-bit detection circuit 5 compares whether or not the address data AD sent via the transmission line 1 matches its own address data. Then, the next 4 bits are received and the control data is
The CD is input in parallel to the time axis conversion circuit 6. A zero-cross detection circuit 7 is connected to the time axis conversion circuit 6 to detect the zero-cross point of the commercial power supply voltage and output a zero-cross detection pulse PZ. The trigger pulse is sent to the triack Q after a time period corresponding to the magnitude has elapsed. Specifically, the time axis conversion circuit 6 is composed of a 4-bit counter, etc., and this 4-bit counter is set by the zero-cross detection pulse PZ, and the 4-bit counter is incremented every time a clock pulse is input from the clock generation circuit 8. 4-bit control data input in parallel from the reception 4-bit detection circuit 5
When CD and the data of the 4-bit counter match, a match signal is output from a comparator that compares both data, thereby generating a trigger pulse for the triack Q.

However, in such a method, when the data input from the received 4-bit detection circuit 5 to the time axis conversion circuit 6 is changed, the brightness of the lighting load 4 changes suddenly, as shown by the broken line in FIG. There was a drawback of doing so. In order to improve this problem, it is conceivable to increase the number of transmitted bits to reduce the change in brightness per stage, but this poses a problem of slowing down the transmission time. In other words, the time for one signal transmission shown in Figure 2 cannot be made too fast in order to maintain reliability in signal transmission, so if we divide the brightness level into 200 levels, If the signal transmission time per cycle is 0.1 seconds, it will take 20 seconds to change from the darkest state to the brightest state, which poses a problem of significantly worsening operability.

The present invention has been made in view of these drawbacks of the conventional example, and provides transmission control that allows the dimming level to be smoothly changed without increasing the number of bits of the actual control data used for transmission. The purpose of this invention is to provide a digital light control device.

The configuration of the present invention will be described below with reference to illustrated embodiments. FIG. 5 shows a block diagram of an embodiment of the present invention, and when compared with the conventional example shown in FIG. 3, the clock pulse generation circuit 8 used for phase control is
In addition to the above, another clock pulse generation circuit 9 is provided, an 8-bit up-down counter 10 is provided for counting the clocks of this clock pulse generation circuit 9, and the 4-bit signal output from the reception 4-bit detection circuit 5 is provided. The difference is that a 4-bit comparator 11 is provided to input the control data CD. 8-bit up-down counter 1
The upper 4 bits of 0 are input to the B input of the 4-bit comparator 11, and are compared with the A input connected to the 4-bit reception detection circuit 5. When a match output is obtained, the inhibition circuit 12 is activated and the clock pulse generation circuit is activated. This is to prevent the clock pulse from 9 from being input to the 8-bit up-down counter 10. Furthermore, a comparison output representing the magnitude relationship between the A input and B input of the 4-bit comparator 11 is input to the input terminal of the up-down operation switching circuit 13 that switches between the count-up operation and the count-down operation of the up-down counter 10. be.

The operation of the embodiment shown in FIG. 5 will be explained below based on the time chart shown in FIG. Assuming that the dimming level is "7" at current time _t1 , and information of dimming level "8" is taken in at time _t2 , at this point the A input and B input of the 4-bit comparator 11 match. output, i.e. “A=
B" output goes to L level, so the clock pulse output from the clock pulse generation circuit 9 passes through the inhibition circuit 12 and is input to the up-down counter 1.
It is input to 0. On the other hand, 4-bit comparator 11
The comparison output representing the magnitude relationship between the A input and B input of , that is, the "A>B" output becomes H level,
Therefore, the up-down counter 10 operates as an up-counter. Currently, the upper 4 bits of the up-down counter 10 are outputting "0111" representing decimal number "7", and therefore the level "7" is being input to the B input of the 4-bit comparator 11. It is. When a clock pulse is input from the clock pulse generation circuit 9 to the up-down counter 10, the up-down counter 10
_The lower 4 bits Q ₄ , Q ₃ , Q ₂ , Q ₁ are sequentially incremented as shown in FIG.
Bits Q ₈ , Q ₇ , Q ₆ , and Q ₅ become "1000" representing decimal number "8", and since the A input and B input match, the comparison output, that is, the "A>B" output becomes L level, Further, the coincidence output, that is, the "A=B" output becomes H level, and therefore the clock pulse output from the clock pulse generation circuit 9 is blocked by the inhibit circuit 12 and the up-down counter 1
0 stops.

Next, the embodiment shown in FIG. 7 has two types of clock pulse generation circuits 8, one for 50 Hz and one for 60 Hz, which input clock pulses to the time axis conversion circuit 6. Power frequency determination circuit 1 that determines whether the power frequency is 50Hz or 60Hz based on pulses
The two types of clock pulse generating circuits 8a and 8b are selectively connected by the output of the clock pulse generator 4. FIG. 8 shows the clock pulse generation circuits 8a, 8b and their switching circuit 15. As shown in the figure, two inverters are connected in series, and the oscillation frequency is controlled by the time constant of the feedback resistor and capacitor. It is determined. Furthermore, the switching circuit 15 inputs a clock pulse to one input terminal of two AND gates, and the power supply frequency determination circuit 14 to the other input terminal.
The frequency of the clock pulse is switched by inputting the judgment output or its negative logic and calculating the logical sum of the outputs of both AND gates.

Next, FIG. 9 shows the specific structure of the reception 4-bit detection circuit 5, in which 8-bit transmission data sent serially via the transmission line 1 is taken into an 8-bit shift register 16. is converted into parallel data. Among these, the upper 4 bits are address data AD as shown in FIG. 2, and the lower 4 bits are control data CD for dimming. The upper 4 bits of address data AD are sent to address comparison circuit 1.
7 is compared with the address assigned to the receiver 2, and 18 is its address setting switch. Next, the lower 4 bits of control data CD are output to a latch circuit 19 for control data, and this latch circuit 19 captures and receives the control data CD only when the output of the AND gate 20 becomes H level. It is latched as the output of the 4-bit detection circuit 5. As shown in FIG. 2, the output of a transmission end detection circuit 21 that detects the synchronization signal SD at both ends of the transmission data is applied to one input of the AND gate 20.
The output of the address comparator circuit 17 is applied to the other input, so that the output of the latch circuit 19 for control data is updated only when the receiver 2 is called and new control data CD are taken in. The data is updated, and in other cases the old data is maintained as is.

Next, FIG. 10 shows the detailed structure of the zero cross detection circuit 7 and the time axis conversion circuit 6. First, the zero-cross detection circuit 7 performs full-wave rectification of the commercial power supply 22 with a diode bridge DB, divides the full-wave rectified pulsating current with bleeder resistors R ₁ and R ₂ , and applies this divided voltage to the transistor T. The transistor Tr is always on by applying it to the base of _r ,
It is configured so that it is turned off only when the AC power supply voltage reaches zero volts, and as a result, the collector voltage of the transistor T _r becomes H level only at the zero cross point of the AC power supply voltage, and therefore this is the zero cross detection. It is designed to be output as pulse PZ. Next, time axis conversion circuit 6
consists of an 8-bit counter 23 and a comparison circuit 24, and the 8-bit counter 23 is reset when a zero-cross detection pulse PZ is input, and is sequentially incremented each time a clock pulse is input. 8 bit counter 23
Each bit Q ₁ ', Q ₂ '..., Q ₈ ' is input to a comparison circuit 24 composed of an exclusive OR circuit 25 and an AND circuit 26, and the output Q of the 8-bit up-down counter 10 _{1 , Q2,} . At this time, the output of the 8-bit up-down counter 10 is transferred to the inverter 30.
Since it is inverted by
If so, a trigger pulse is output at the same time as the 8-bit counter 23 is reset, and therefore the lighting load 4 controlled by the triax Q becomes the brightest at this time. Incidentally, since the output of the AND circuit 26 is actually at the TTL level, when triggering the high power triac Q, the pulse is amplified using an auxiliary thyristor or the like.

Furthermore, FIG. 11 shows the specific structure of the power supply frequency determination circuit 14, and the m-bit counter 27 is reset by the zero-cross detection pulse PZ and counts the clock pulses of the clock pulse generation circuit 28. After operation approx.
The configuration is such that the most significant bit Q _n becomes H level after 9 msec has elapsed. Figure 12 shows the same time chart as above, and figure a shows the power supply frequency.
Zero cross detection pulse PZ for 50Hz,
It has a period of 10msec. On the other hand, figure b shows the zero-cross detection pulse PZ when the power supply frequency is 60Hz.
, and has a period of approximately 8.3 msec. Therefore, if it is assumed that the most significant bit Qm of the m-bit counter 27 becomes H level after approximately 9 msec has elapsed after the input of the zero-cross detection pulse PZ as shown in FIG.
The output of 9 becomes H level when the power supply frequency is 50Hz, but becomes L level when the power supply frequency is 60Hz. Figure 13 shows the change in the conduction angle of the triax Q due to the switching of the clock pulses for 50 Hz and 60 Hz, and Figure a shows the conduction angle of the triax when the power supply frequency is 60 Hz. If the power frequency is switched from 60 Hz to 50 Hz without doing this, the ratio of the conduction angle to the power cycle will be different, as shown in FIG. On the other hand, in figure c, the power supply frequency is
At the same time as switching from 60Hz to 50Hz, the frequency of the clock pulse is also reduced to 5/6, making the period longer. In this way, the ratio of the conduction angle to the power supply period will be the same as in the case shown in Figure a. ,
The brightness of the lighting load 4 will no longer change depending on the power supply frequency.

The present invention is configured as described above, and includes a plurality of receivers that control dimming of a lighting load, a transmitter that sends address data and control data for dimming to each receiver, and a transceiver. In a digital light control device that uses transmission control and consists of interconnected transmission lines, each receiver includes an address comparison circuit, a latch circuit that latches the control data of its own station, and an up-down circuit that has a larger number of bits than the control data. A counter and a comparator are provided to compare the upper bits of the up-down counter and the output of the latch circuit,
Every time the control data for dimming output from the latch circuit is updated to new data, an up-down counter with a larger number of bits than this control data is sequentially incremented to create a quasi-fine dimming level. Even if the number of bits of control data for dimming actually transmitted to the receiver via the transmission line is small, the brightness of the lighting load will not change suddenly when the dimming level is changed. This has the advantage that the brightness changes very smoothly, and there is no need to increase the number of bits of control data used for transmission control, so there is no need to increase the transmission speed of control data. Therefore, the reliability of control data transmission can be maintained at a high level, and the signal processing time on the receiver side, which takes in signals from the transmission line, can be sufficiently long. This has the advantage that the reliability of the entire optical device can be maintained at a high level. Furthermore, in the present invention, since the number of bits of control data on the transmission line is the same as in the conventional case, it is difficult to use the conventional dimming receiver in which the brightness changes suddenly when the dimming level is changed. It is also possible to connect two devices on the same transmission line, so you can choose a dimming receiver depending on whether smooth changes in brightness are required or not. It is possible.

Note that in a light control device such as the present invention, in which a phase control counter is reset by a zero-cross detection pulse of the power supply voltage, and a thyristor is triggered when the value of this counter has counted up to a predetermined value, , whether the power frequency is 50Hz
The brightness changes depending on whether it is 60Hz or not, but as shown in the example in Figure 6, there are two types: 50Hz and 60Hz.
A clock pulse generation circuit is provided in advance for
If both are switched and used according to the output of the power supply frequency determination circuit, the brightness of the lighting load will not change due to changes in frequency, and the brightness will be controlled according to the transmitted data. Therefore, it is particularly convenient for remote dimming control using transmission control, where brightness cannot be checked on site.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall configuration of a digital dimming device using transmission control according to the present invention, Fig. 2 is an explanatory diagram showing an example of the same transmission data, and Fig. 3 is a block diagram of a conventional dimming receiver. 4 is an explanatory diagram of the same operation as above, FIG. 5 is a block diagram of an embodiment of the digital light control device using transmission control of the present invention, FIG. 6 is an explanatory diagram of the same as above, and FIG. 7 is an explanatory diagram of the same as above. A block diagram of another embodiment, FIG. 8 is a main logic circuit diagram of the same as above, FIG. 9 is a block diagram of the receiving 4-bit detection circuit of the same as above, and FIG. The block diagram, Figure 11 is a block diagram of the power frequency determination circuit, Figures 12 a to c, and the first
Figures 3a to 3c are explanatory views of the same operation. 1 is a transmission line, 2 is a receiver, 3 is a transmitter, 4 is a lighting load, 7 is a zero cross detection circuit, 8 and 9 are clock pulse generation circuits, 10 is an up/down counter, 11 is a comparator, 12 is an inhibition circuit, 13
17 is an address comparison circuit, 19 is a latch circuit, and 24 is a comparison circuit.

Claims (1)

[Claims] 1. A plurality of receivers that control dimming of a lighting load;
A transmitter that sends address data and control data for dimming to each receiver via a transmission line is provided, and each receiver compares the address data on the transmission line with the address data of its own station. The output of the latch circuit is used as one comparison input, and the upper bit of the up-down counter, which has more bits than the control data, is used as the other comparison input. an up-down operation switching circuit of the up-down counter connected to a comparison output that compares and determines the magnitude of both comparison inputs of the comparator; and an inhibition circuit connected to a coincidence output that determines whether both comparison inputs of the comparator match. a first clock pulse generation circuit that supplies clock pulses to the up-down counter via the inhibition circuit; a phase control counter having the same number of bits as the up-down counter and connected to the second clock pulse generation circuit; A zero-cross detection circuit that is connected to the reset terminal of the control counter and outputs a zero-cross detection pulse of the commercial power supply voltage, a comparison circuit that compares the output of the phase control counter and the output of the up-down counter, and a A digital light control device using transmission control, characterized in that it is connected to a power control element for controlling the phase of a lighting load. 2. A power frequency determination circuit that is connected to the output of the zero-cross detection circuit and determines the power frequency of the commercial power supply, a set of clock pulse generation circuits with an oscillation frequency ratio of 5:6, and 50Hz and 60Hz power supplies, respectively. 2. The digital light control device using transmission control according to claim 1, further comprising a switching circuit for selectively connecting the outputs of both clock pulse generation circuits to the clock input terminal of a phase control counter according to the frequency.